First thought on DAQ for the next pixel beam test Chiodini Gabriele Monday pixel meeting - June 25, 2001

First thought on DAQ for the next pixel beam test

Chiodini GabrieleMonday pixel meeting - June 25, 2001

Gabriele Chiodini - Monday pixel meeting -6-25-01

Overview

• Experimental setup• Outer and inner board for

pixel plane• Power supplies• PCI+Mezzanine cards• Initialization + trigger +

readout• Data storage• PC+software+run and cal

analysis +E.Logbook+GPIB• What to purchase and test


Experimental setupCounting room:

• PC• PCI bus extender box• Nim crate (Scintillator counters, discriminators,…)

• Beam control and monitor

Thermo controlled Hut:• Pixel Telescope• Scintillators• Power supplies (HV, LV, LC)• Cooling system for Irradiated sensors• Nim crate?• PC for debugging? Must control the PC in the counting room.

LVDS lines.CMOS?

GPIBPMT’s HV and output

50-100 feet


Outer and inner board for pixel planes (1)

•The telescope is made by pixel detector instrumented by FPIX1 readout chip• Pixel detectors under study are:

• instrumented by preFPIX2Tb readout chip irradiated (must be kept cold) and not irradiated.• Eventually 5 chips FPIX1 pixel module laminated to pixel sensor.

• The strongly desired solution is not to use any outer board and drive directly by LVDS digital line FPIX1 and preFPIX2Tb inner boards.


Outer and inner board for pixel planes (2)

• FPIX1 inner used for EMI tests is LVDS compatible but need to relocate the pixel in the middle.It is the only modification? What about the FPIX1 CMOS control line?

• preFPIX2Tb inner board need to add LVDS drivers and receivers. A lot of lines but a lot of space on the existing preFPIX2Tb inner board.Space must be saved for cooling irradiated detectors.

• The inner boards must have a hole underneath the chip. MS it is an issue with 10-50 GeV beam.


Outer and inner board for pixel planes(3)

FPIX1:• Vddd and Vdda 3-3.3V (not Vmid=1.5V anymore?).• Ibbp=-0.7uA and Ibbf=-5nA.• 4 Thresholds.• Charge injection.• 3 LVDS control lines• 9 CMOS control lines• 18 LVDS output lines• 2 CMOS output lines

preFPIX2Tb:• Vddd, Vdda and Vprot 2.5V.• Charge injection.• 8 2.5V CMOS control lines• 29 2.5V CMOS output lines


Power suppliesHigh Voltage:• One Keithley per detectors? Very expensive solution. One Keithley for more than one detectors? One option could be :

• Upstream (downstream) FPIX1’s togheter• preFPIX2Tb each with is own HV.

Low voltage:• Tektronix PS has 3 separated lines.• Group LV lines toghether? On boards? Between planes?

Buy few (one spare) beam test dedicated multi channels HV-LV power supplies:• Start experience with these devices.• We won’t have empty bench test (module, laser, probe station, … debugging).

Current sources for FPIX1:• CPPM module has N output lines. • Group all together upstream (downstream) FPIX1?


PCI cards+mezzanine(1)

• Several PCI+mezzanine cards inserted in the bus extender box.• Each PCI+mezzanine card control and readout one or more pixel planes. How many FPIX1 and preFPIX2Tb?• Eventually one PCI+mezzanine card control and readout a module.• What function the FPGA on the mezzanine performs? (For example generate read_clk and BCO_clk).


PCI cards +mezzanine(2)•The FPGA in each PCI card must count a

coincidence signal common to the system and provided to the mezzanine card:

• scintillators• pin diodes• FPIX1_chip_has_data or/and preFPIX2Tb_core_has_data of some boards (in this case must be provide by the mezzanine card to the coincidence modules)

• The FPGA in each board readout the corresponding board/boards and attach to the hits the coincidence number.• The FPGA store the hits in the available 1Mbyte bank memories.• The FPGA in each PCI card must count the spill number.

Header End of events

HIT1 HITN HIT=chipid+bco+row+col+adc

In one run the event is characterized by a coincidence number in order to tag sub event read it out from different PCI boards.


Initialization, trigger and readout (1)

FPIX1:• Can be daisy-chain in the initialization and in the readout. Need to connect shift-out to shift-in and token_out to token_in to between nearby boards.A PCI+mezzanine card can be enough to deal with all FPIX1 boards because the control and output signals can be shared. Chip_has_data signals are Or-ed together.• It is possible to have all the FPIX1’s independent? A lot of PCI+mezzanine cards.• Free running BCO_clock and Read_clock to have Timestamp information and chip_has_data pushed out.

preFPIX2Tb:• Initialized by broadcasting command and data on a common 2-bit bus and running the BCO clock.• The readout signals, output data and readback (shift_out) must be kept independent for each preFPIX2Tb.• Look to me we need one PCI-card for each preFPIX2Tb.• Free running BCO_clock and Read_clock to have Timestamp information and chip_has_data pushed out.



Readout:• Continuous mode for FPIX1.• Read_clk and BCO_clock free running for both FPIX1 and preFPIX2Tb in order to have Timestamp.• Read_clk and BCO_clock are provided by the FPGA:

• Not necessary the same for FPIX1 and preFPIX2Tb. preFPIX2TB is faster.• Can we have one master clock for all FPGA?

• For sure BCO information inside a chip and between chip connected to the same PCI-card are the same.• FPIX1 BCO has 6 bit. preFPIX2Tb BCO has 8 bit.

• It will be nice to have synchronous FPGA with preFPIX2Tb BCO 4 times faster than FPIX1 BCO.

• If all chips must have the same BCO we must have one FPGA from different PCI card synchronized.PS.Timestamp for a single chip are extremely useful to see if hits of small charge in one cluster are associated or not to the next BCO clock. To study that we need the 53MHz RF and understand if correlated with the track time arrival.



• The spill counter and the coincidence counter in every FPGA reset at the beginning of each run.• When data reset the boards?

• Each spill?• Every milliseconds?• Delay in broadcasting the reset signals and implication• How to broadcast the reset signal? Throughout a master reset broadcasted to all the mezzanine cards?

• All the hits are readout, associated with the coincidence number and stored on a memory bank.• When the memory bank is full the FPGA switches to the other ones and start to fill it. In the meantime the PC empty the full memory bank and save the data in is own RAM memory (if the FPGA switches again memory bank it must way the memory is emptied by the PC.• At the end of the spill the PC save the data on the disk and attach the spill number.• If the spill arrives and the PC didn’t complete the writing to the disk loose the spill.• After the writing to the disk the PC reinitialize the PCI-card, reset all the telescope and wait the next spill.


PC• Window PC: The advantage is that we are already working and developing software tools for bench tests:

• Jungo driver license. • C-functions and Labview VI’s.• Quartus software for FPGA’s.• FPGA firmware downloadable through PCI-bus.• …

• Linux PC: The advantages are:• Remote control by the net.• Automatic ftp file transfer.• AFS disk space.• … The disadvantages are:• Jungodriver license.• A new software developing branch from bench test. How much painful or painless?• …


PC+Software+….• Code: C-functions. All the clever functions and right and read files in order to be fast.• GUI: Labview. Star, stop buttoms, configuration file selection ...• Plots: Generated by C-function and displayed by Labview.

• Monitor HV, LV and currents• Monitor cooling performace: T and umidity• (Eventually PAW) Hits statistic per plane, single event, basic track projection in x-z and y-z plane,… .

• Electronic logbook? Which one?

PS:• Labview can not manage C-structures.• When Labview does a C-call loose the control until the c-call is finished.• Right now I don’t know how to stop by labview a run started by labview through a C-call.

• GPIB card in the PCI bus extender to control power supplies, current sources, calibration pulser, cooling system. C-code (at leas for the pulser) and Labview controlled. • 3 independent Labview VI: Run VI, Calibration VI and GPIB VI.


Data size and bottleneck• Assuming 5000 coincidence signals between two

scintillators and one FPIX Fast-or in 40 seconds beam spill.• Assuming each plane with 5 hits (integrated hits during two coincidences).• Assuming one hit need 3 byte to be stored.• For 10 planes we have

• 3*10*5=150 byte per event.• 150*5000=750kbyte in 40 seconds beam spill.

• The code write the data on a local disk during the 40 seconds no beam spill.

• How much does it take to open, write 750kbyte (binary or ASCII) and close the files? Probably OK.

• There are bottleneck in the system?• What happen if there are 10 times more hits than expected? • A file with 50000 events has a size of 7.5Mbyte and is collected in 13 minutes.• How many events has tracks crossing the planes under test and several traking planes (useful and well reconstructed tracks)?• Save the run files in a CD-rom or FTP to the Fermilab storage system.


What to purchase and test

• Buy a PC and install the appropriate operative system and software. • Choose and buy an appropriate PCI bus extender.• Buy GPIB card to plug in the bus extender.• Choose and buy the appropriate multi channel high voltage and low voltage power supplies (or count the Keithley HV and Tektronix PS we can use in the test beam)• Buy a CD-rom recorder• Designe and prepare new inner boards.• Start to use and test all the components:

• FPIX1 boards• preFPIX2Tb board• FPIX1 Module• PCI bus extender with several PCI+mezzanine card and GPIB card• Play with FPGA’s on the PCI card• Initialization+trigger+readout chain• DAQ speed

• Have a dedicated bench test to do all this.

Documents

First thought on DAQ for the next pixel beam test Chiodini Gabriele Monday pixel meeting - June 25, 2001