Fishbone: A Block-Level Placement and Routing Scheme

Fan Mo and Robert K. Brayton

EECS, UC Berkeley

Outline• The block level placement and routing problem

– Routability, predictability

• Fishbone scheme– Spine net topology– Base/Virtual pin pair– Row/column routing with left-edge algorithm

• Integrated placement and routing• Experimental results• Discussion

Block-Level P&R• In conventional design flow, the block-level

placement and routing are two sequential stages.– During placement, certain net model (fast but

inaccurate) is used to estimate wire length, congestion, etc.

– During routing, blocks are fixed and nets are routed with certain net model (slow but accurate).

• Problem occurs when wrong estimation was made during the placement, or even early steps of the routing.

RST and HP• Rectilinear Steiner Tree (RST)

– Smallest wire length– Slowest computation

• Half-Perimeter Model (HP)– Good estimation of RST– Faster computation– Strictly speaking, HP is not a net topology. It cannot

be used to predict congestion and routability

• A common approach is to use HP in placement and RST in routing.

Block-Level Design in Reality• Pins of the blocks lie on layer mB. Routing takes place on

a couple of higher metal layers, mB+1 and mB+2.

• Layers mB+1 and mB+2 have preferred routing directions (vertical or horizontal) for better manufacturability.

• Routability problem may occur, especially in and around pin regions.– Pins of a block may lie close to each other– Pins of adjacent blocks may lie close to each other.– Such routability problems are quite local, which are hard to

predict even in the global routing step.

The New Routing Scheme• We want a net topology and a routing scheme

that have– Better predictability of routability than HP (or even

RST), especially in and around pin regions.– Faster computation than RST.

Spine Topology• The output pin of a net is on a vertical wire called

"trunk"; and all the input pins connect to the spine by horizontal "branches".– Given pin positions, the net shape is fully determined.– Pin-pin distance is Manhattan.– Routability is easy to detect, given all pin positions.

Grids, Columns and Rows• The routing grids are given cyclic indices labeled

0,1,2,…, GR-1, where GR is the grid radix. • The whole routing space is composed of rows (or

columns), each containing grid 0~GR-1.

Base Pins

0 1 2 3 4 5 0012345

1 2 3 4 5

012345

0 1 2 3 4 5 0 1 2 3 4 5 0

012345012345012

base output pin(mB)

base input pin(mB)

GR=6

obstruction(mB)

Virtual Pins

0 1 2 3 4 5 0012345

1 2 3 4 5

012345

0 1 2 3 4 5 0 1 2 3 4 5 0

012345012345012

GR=6

virtual output pin(mB+2)

trunk

virtual input pin(mB+1)

branch

0 1 2 3 4 5 0

012345

1 2 3 4 5

012345

0 1 2 3 4 5 0 1 2 3 4 5 0

0123450123450

Base/Virtual Pin-Pairs

GR=6

virtual input pin

virtual output pin

The Fishbone Routing• Given a placement of the blocks, we know the base pin

locations (the columns of the base output pins, and the rows of the base input pins).– Only know one coordinate of the virtual pin (Y of virtual output pin

and X of virtual input pin).• The trunks are assigned to the columns, and the

branches are assigned to the rows.• Use "left-edge" algorithm to arrange trunks in columns

and branches in rows.• Then we know the virtual pin positions (points).

• Overflows in the "left-edge" packing are considered as routing violations.– The Fishbone scheme seeks a placement (and thus the routing)

with no violation and some objective function (area and/or delay) minimized.

The Integrated Fishbone P&R• Simulated-annealing framework.

– Sequence-pair – Base/virtual pin and Fishbone routing

• After a random move (swapping of blocks in the sequence pair, or swapping two I/O ports).– Evaluate area (sequence-pair)– Fishbone routing– Evaluate routing violation, wire length or delay

0 1 2 3 4 5 0012345

1 2 3 4 5

012345

0 1 2 3 4 5 0 1 2 3 4 5 0

0123450123456

The I/O Ports

extended region

virtual inputpins

virtualoutput

pin

pseudobranch

Experiment

• Compare the areas, wire lengths and run times of:– Placement and routing with Fishbone.– Placement with RST and Warp Router routing.– Placement with HP and Warp Router routing.– HP placement, post wire length measurement with RST.– Fishbone placement, post wire length measurement with RST.– Fishbone placement, Warp Router routing with base pins.– Fishbone placement, Warp Router routing with virtual pins.

Example #Block #I/O #Net #Pin Grid radix

ami33 33 42 117 522 7

ami49 49 22 407 953 8

playout 62 192 1609 4656 9

ibm100 30 200 3327 9983 7

ibm101 40 300 4340 13021 8

ibm102 50 400 5402 16208 9

ibm103 60 500 6481 19443 9

ibm104 70 600 7621 22864 10

Experimental Results

• On average, the Fishbone scheme resulted in a 14% area overhead and a 5% increase in wire length.

– A price paid for 100% routability and predictability known during placement. • Fishbone placement with virtual pins specified (FB ro-v) is 100% routable

using the Wrouter. Also it runs much faster (because there are no violations to be repaired).

area (mm2) average wire length (mm) #routing violationsFB HP RST FB FB

example FB HP RST pl p-RST ro-b ro-v pl p-RST ro pl ro ro-b ro-v HP RST

ami33 5.09 5.32 5.10 0.70 0.76 0.76 0.78 0.89 0.90 0.89 0.85 0.83 2 0 6 7

ami49 59.4 57.2 58.9 3.22 3.15 3.15 3.18 3.16 3.24 3.24 3.09 3.12 0 0 0 0

playout 349 296 298 9.14 9.42 9.13 9.39 8.92 9.07 9.13 8.91 8.97 4 0 4 2

ibm100 73.6 65.1 67.2 7.51 6.94 6.97 6.94 6.40 6.76 6.74 6.91 6.90 6 0 7 6

ibm101 102 83.9 81.0 8.58 7.92 7.93 7.91 7.28 7.68 7.64 7.90 7.87 5 0 11 7

ibm102 127 104 103 9.21 8.43 8.46 8.43 8.11 8.57 8.55 8.87 8.82 3 0 13 13

ibm103 151 128 131 10.9 9.92 9.93 9.89 9.01 9.50 9.48 9.57 9.53 15 0 16 16

ibm104 187 152 156 11.7 10.5 10.5 10.4 10.6 11.2 11.2 10.2 10.2 23 0 20 23

compare 1.14 1.00 1 1.05 1.00 1.00 1.00 0.98 1.02 1.01 1 1.00 0.77 0 1.06 1

pl: placed.p-RST: post-placement RST estimation. ro: Wrouter.ro-b: Wrouter. Routing with Fishbone placemen but with base pins only.ro-v: Wrouter. Routing with Fishbone placement and virtual pins.

Experimental Results

• The run time of the Fishbone scheme is the time taken only by the simulated annealing phase, which is on average 80% less than for RST placement; the RST and HP placements need extra time for routing.

placement time routing timeFB FB

example FB HP RST ro-b ro-v HP RSTami33 1m36 0m30 19m 1m14 0m02 1m06 1m15ami49 5m07 1m05 54m 0m22 0m02 0m22 0m24

playout 20m 3m15 1h39 1m55 0m13 1m55 2n33ibm100 53m 8m 4h24 2m40 1m32 2m45 2m52ibm101 72m 9m 6h02 3m40 2m26 4m27 4m37ibm102 1h34 10m 7h07 6m58 4m18 6m06 7m15ibm103 1h56 12m 8h09 9m13 6m26 9m07 10mibm104 2h17 13m 9h42 13m 9m13 15m 13m

compare 0.19 0.03 1 0.91 0.39 0.92 1

Discussion• Fishbone cannot handle obstructions in the

routing layers.• No 90o rotations of the blocks are allowed.• Only vertical spine (trunk vertical).• Need a pre-defined grid radix GR.

• Extension to timing-driven version is straightforward.

• Easy for coupling capacitance extraction.