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Speaker & Reporter: 洪聖揚 Adviser ： Prof. An-Weu Wu Date ： 2006/12/11. Fixed-pointed FFT model. Floating point simulation Fixed point model with truncation SQNR with input, output and twiddle factor Optimize the choice of bits Conclusion. Outline. Use MATLAB compile BFI 、 BFII as module - PowerPoint PPT Presentation
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Speaker & Reporter: 洪聖揚Adviser ： Prof. An-Weu Wu
Date ： 2006/12/11
1
Floating point simulation Fixed point model with truncation SQNR with input, output and twiddle
factor Optimize the choice of bits Conclusion
2
Use MATLAB compile BFI 、 BFII as module For loop as counter
BF I
N/2 N/4
BF II
s t
Out of BFIOut of BFII
Input ： (1)data input (2)Out of BFI (3)Register
Output ： (1)Output of BFI (2)Output of BFII (3)Output as Register input
Data input
Register
Function ： BFI BFII
Control by for loop
3
Use fft function in MATLAB for verification
0 10 20 30 40 50 60 70-2
0
2x 10
-15 Output difference
point
Rea
l P
art
0 10 20 30 40 50 60 70-2
0
2x 10
-15 Output difference
point
Ima
g P
art
0 10 20 30 40 50 60 700
1
2x 10
-15 Out difference
point
Abs
Par
t
4
Floating point simulation Fixed point model with
truncation SQNR with input, output and twiddle
factor Optimize the choice of bits Conclusion
5
Separate total bits into two parts : integer part and fraction part Inverse the digits to the
decimation ;construct the truncated data Use the truncated data during the calculation
6
Recovery the fraction data
Recovery the signed data
Truncate data of abs(real(x)) and abs(imag(x))
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Dynamic range for input data:[-4 4] Number of bits for input data:10~14 Number of bits for output data:16~20 Number of bits for twiddle factor:
Designer-defined SQNR>=50dB
8
Defined as Output of previous stage
Defined as Input
9
Floating point simulation Fixed point model with truncation SQNR with input, output and
twiddle factor Optimize the choice of bits Conclusion
10
The input integer part should increasing 1 bit through the adder
The integer part of twiddle factors can be reduced to 1 bits
Input integer bits reduced to 3 bits ,as the final output integer bits reduced to 9 bits
11
Output integer and total bit of input fixed, add input integer
Input integer and total output bit fixed, add output integer
68
1012
3
4
5
6
7
30
40
50
60
twiddle factor fraction
SQNR different with output integer fixed
input integer part
SQ
NR
25
30
35
40
45
50
55
60
65
68
1012
9
10
11
12
13
30
40
50
60
twiddle factor fraction
SQNR different with input integer fixed
output integer part
SQ
NR
25
30
35
40
45
50
55
60
65
Fixed integer output and total bit of input
Fixed integer input and total bit of output
12
There is much room for fraction bits decision
Just compare output bit and twiddle factor to optimize the minimum bits.
The fraction part dominates the precision of output
13
Fixed twiddle factor total ： 13 bit and 14 bit Use 1 bit to store integer data
At total bits=12At total bits=14
78
910
11
7
8
9
10
11
55
60
65
70
output fraction part
SQNR different with twiddle factor fraction fixed
input fraction part
SQNR
52
54
56
58
60
62
64
66
68
70
78
910
11
7
8
9
10
11
52
54
56
58
60
62
64
output fraction part
SQNR different with twiddle factor fraction fixed
input fraction part
SQ
NR
52
54
56
58
60
62
64
14
78
910
11
7
8
9
10
11
55
60
65
70
output fraction part
SQNR different with twiddle factor fraction fixed
input fraction part
SQ
NR
52
54
56
58
60
62
64
66
68
70
Fixed twiddle factor total ： 13 bit and 14 bit Use 1bit to store integer part
At total bits=14 At total bits=13
78
910
11
7
8
9
10
11
55
60
65
70
output fraction part
SQNR different with twiddle factor fraction fixed
input fraction part
SQNR
52
54
56
58
60
62
64
66
68
70
15
810
1214
7
8
9
10
1140
45
50
55
60
65
twiddle factor fraction
SQNR different with output fraction fixed
input fraction part
SQ
NR
40
45
50
55
60
65
810
1214
7
8
9
10
1140
45
50
55
twiddle factor fraction
SQNR different with input fraction fixed
output fraction part
SQ
NR
40
42
44
46
48
50
52
54
56
58
total input bits:12bits ， total output bits:18bits Integer fixed at 3 bit in input,9 bit in output ,1 bit in
twiddle Twiddle factor fraction ： 8~16 bit
At input total bits=12
At output total bits=18
16
When twiddle factor increasing, SQNR is more higher, but saturation at total bit=16
When output fraction bit increasing - bits of twiddle is small, not obviously
change in SQNR - bits of twiddle is large, SQNR is more
higher
17
Floating point simulation Fixed point model with truncation SQNR with input, output and twiddle
factor Optimize the choice of bits Conclusion
18
Requirement SQNR over than 50dB Better reducing bits of output than twiddle Choose fraction bits of output and input be
equal or more Fixed twiddle factor at maximum to choose
output minimum, then reduce twiddle factor.
19
78
910
11
7
8
9
10
11
55
60
65
70
output fraction part
SQNR different with twiddle factor fraction fixed
input fraction part
SQ
NR
52
54
56
58
60
62
64
66
68
70
First, fixed twiddle factor at total bit=13
At total bits=13
Possible output
min
Over than 50dB
20
810
1214
7
8
9
10
1140
45
50
55
twiddle factor fraction
SQNR different with input fraction fixed
output fraction part
SQ
NR
40
42
44
46
48
50
52
54
56
58
Second, fixed output and input at possible minimum region, find out the twiddle factor minimum.
Ex. Fixed output at 8 fraction
At fraction output=8
Input min
twiddle min
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Result ：Input Output Twiddle SQNR
10 16 10 48.3921
10 16 11 50.2602
11 17 10 51.4667
11 17 11 54.6418
11 18 10 51.8127
11 18 11 55.1741
12 17 10 51.8890
12 17 11 55.3209
Best Solutio
n!
22
Conclusion ： 1.Finished floating and fixed point FFT model
2.Analyzed and optimize the bits for truncate input, output, and twiddle factor
In future ： --RTL code before 12/27 --synthesis as soon as possible…
23
