Flash, 2 KB EEPROM, 4 KB SRAM, 10-bit ADC, 10-bit DAC, CAN, UART, 12-bit …ww1.microchip.com/downloads/en/DeviceDoc/ATmegaS64M1... · 2018-03-22 · Flash, 2 KB EEPROM, 4 KB SRAM,

ATmegaS64M1 Rad-Tol 8-bit AVR Microcontroller, 3.3V, 8 MHz with 64 KBFlash, 2 KB EEPROM, 4 KB SRAM, 10-bit ADC, 10-bit DAC,CAN, UART, 12-bit PSC, SPI, 8-bit and 16-bit Timer/Counter

with PWM

Introduction

The ATmegaS64M1 is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISCarchitecture. By executing powerful instructions in a single clock cycle, the ATmegaS64M1 achievesthroughputs close to 1 MIPS per MHz. This empowers system designers to optimize the device for powerconsumption versus processing speed.

Features

• High-performance, Low-Power 8-bit AVR® Microcontroller• Advanced RISC Architecture

– 131 powerful instructions - most single clock cycle execution– 32 × 8 general purpose working registers– Fully static operation– Up to 1 MIPS throughput per MHz– On-chip 2-cycle multiplier

• Data and Nonvolatile Program Memory– 64K Bytes flash of in-system programmable program memory– 2K Bytes of in-system programmable EEPROM– 4K Bytes internal SRAM– Write/erase cycles

• Flash: 10,000 cycles• EEPROM: 20,000 cycles

– Data retention• 15 years @ 70°C• 10 years @ 125°C

– Optional boot code section with independent lock bits• In-system programming by on-chip boot program• True read-while-write operation

– Programming lock for Flash program and EEPROM data security• On-chip DebugIinterface (debugWIRE)• CAN 2.0A/B with Six Message Objects - ISO16845 certified• 8-bit UART (supporting LIN 2.1 and 1.3 controller)

© 2018 Microchip Technology Inc. Datasheet DS60001506B-page 1

• One 12-bit High-speed Power Stage Controller (PSC)– Nonoverlapping inverted PWM output pins with flexible dead-time– Variable PWM duty cycle and frequency– Synchronous update of all PWM registers– Auto stop function for emergency event

• Peripheral Features– One 8-bit general-purpose timer/counter with separate prescaler, compare mode and capture

mode– One 16-bit general-purpose timer/counter with separate prescaler, compare mode and capture

mode– One master/slave SPI serial interface– 10-bit ADC

• Up to 11 single-ended channels and three fully differential ADC channel pairs• Programmable gain (5×, 10×, 20×, 40×) on differential channels• Internal reference voltage• Direct power supply voltage measurement

– 10-bit DAC for variable voltage reference (comparators, ADC)– Four analog comparators with variable threshold detection– 100 μA ±2% current source (LIN node identification)– Interrupt and wake-up on pin change– Programmable watchdog timer with separate on-chip oscillator– On-chip temperature sensor

• Special Microcontroller Features– Low power idle, noise reduction, and power down modes– Power on reset and programmable brown-out detection– In-system programmable via SPI port– High-precision crystal oscillator for CAN operations– 8 MHz internal calibrated RC oscillator– On-chip PLL for fast PWM

• Operating Range– Operating voltage: 3.0 V to 3.6 V– Temperature: -55 °C to +125 °C

• 8 MHz Core Speed Grade• Radiation Tolerance

– No Single Event Latch-up (SEL) below a LET threshold of 62.5 MeV/mg/cm2@125 °C– Tested up to a Total Ionizing Dose (TID) of 30 KRads(Si) according to MIL-STD-883 Method 1019

• ESD Classification– HBM > 4000V (Class 3A)– CDM > 1000V (Class IV)

• Packages– 32-lead Ceramic Quad Flat package (CQFP) with mass equal to 0.847g– 32-lead Plastic Quad Flat package (TQFP) with mass equal to 0.145g

ATmegaS64M1


Table of Contents

Introduction......................................................................................................................1

Features.......................................................................................................................... 1

1. Space Quality Grade................................................................................................. 9

2. Description...............................................................................................................10

3. Block diagram.......................................................................................................... 11

4. Pin configurations.................................................................................................... 124.1. Pin Descriptions......................................................................................................................... 13

5. Ordering Information................................................................................................17

6. Resources............................................................................................................... 18

7. About code examples.............................................................................................. 19

8. AVR CPU Core........................................................................................................ 208.1. Overview.................................................................................................................................... 208.2. Arithmetic Logic Unit (ALU)........................................................................................................218.3. Status Register...........................................................................................................................218.4. General Purpose Register File...................................................................................................248.5. Stack Pointer..............................................................................................................................258.6. Accessing 16-Bit Registers........................................................................................................ 278.7. Instruction Execution Timing...................................................................................................... 288.8. Reset and Interrupt Handling..................................................................................................... 28

9. AVR Memories.........................................................................................................319.1. Overview.................................................................................................................................... 319.2. In-System Reprogrammable Flash Program Memory................................................................319.3. SRAM Data Memory.................................................................................................................. 329.4. EEPROM Data Memory............................................................................................................. 339.5. I/O Memory.................................................................................................................................349.6. Register Description...................................................................................................................35

10. System Clock and Clock Options............................................................................ 4410.1. Clock Systems and Their Distribution........................................................................................ 4410.2. Clock Sources............................................................................................................................ 4510.3. Default Clock Source .................................................................................................................4610.4. Low Power Crystal Oscillator..................................................................................................... 4610.5. Calibrated Internal RC Oscillator................................................................................................4810.6. PLL.............................................................................................................................................4910.7. 128kHz Internal Oscillator.......................................................................................................... 50


10.8. External Clock............................................................................................................................ 5010.9. Clock Output Buffer.................................................................................................................... 5110.10. System Clock Prescaler.............................................................................................................5110.11. Register Description...................................................................................................................52

11. Power Management and Sleep Modes................................................................... 5711.1. Sleep Modes.............................................................................................................................. 5711.2. Idle Mode....................................................................................................................................5711.3. ADC Noise Reduction Mode...................................................................................................... 5811.4. Power-Down Mode.....................................................................................................................5811.5. Standby Mode............................................................................................................................ 5911.6. Power Reduction Register..........................................................................................................5911.7. Minimizing Power Consumption.................................................................................................5911.8. Register Description...................................................................................................................60

12. System Control and Reset.......................................................................................6412.1. Resetting the AVR...................................................................................................................... 6412.2. Reset Sources............................................................................................................................6412.3. Power-on Reset..........................................................................................................................6512.4. External Reset............................................................................................................................6612.5. Brown-out Detection...................................................................................................................6612.6. Watchdog System Reset............................................................................................................6712.7. Internal Voltage Reference.........................................................................................................6712.8. Watchdog Timer......................................................................................................................... 6812.9. Register Description...................................................................................................................70

13. INT - Interrupts........................................................................................................ 7413.1. Interrupt Vectors in ATmegaS64M1........................................................................................... 7413.2. Register Description...................................................................................................................77

14. External Interrupts (EXINT)..................................................................................... 8014.1. Overview.................................................................................................................................... 8014.2. Register Description...................................................................................................................81

15. I/O-Ports.................................................................................................................. 9215.1. Overview.................................................................................................................................... 9215.2. Ports as General Digital I/O........................................................................................................9315.3. Alternate Port Functions.............................................................................................................9615.4. Register Description................................................................................................................. 110

16. 8-bit Timer/Counter0 (TC0) with PWM.................................................................. 12516.1. Features................................................................................................................................... 12516.2. Overview.................................................................................................................................. 12516.3. Timer/Counter Clock Sources.................................................................................................. 12716.4. Counter Unit............................................................................................................................. 12716.5. Output Compare Unit............................................................................................................... 12816.6. Compare Match Output Unit.....................................................................................................13016.7. Modes of Operation..................................................................................................................132

ATmegaS64M1


16.8. Timer/Counter Timing Diagrams.............................................................................................. 13616.9. Register Description.................................................................................................................138

17. 16-bit Timer/Counter1 (TC1) with PWM................................................................ 15017.1. Overview.................................................................................................................................. 15017.2. Features................................................................................................................................... 15017.3. Block Diagram..........................................................................................................................15117.4. Definitions.................................................................................................................................15117.5. Registers.................................................................................................................................. 15217.6. Accessing 16-bit Timer/Counter Registers...............................................................................15217.7. Timer/Counter Clock Sources.................................................................................................. 15517.8. Counter Unit............................................................................................................................. 15517.9. Input Capture Unit.................................................................................................................... 15617.10. Output Compare Units............................................................................................................. 15817.11. Compare Match Output Unit.....................................................................................................16017.12. Modes of Operation..................................................................................................................16117.13. Timer/Counter 0, 1 Prescalers................................................................................................. 16917.14. Timer/Counter Timing Diagrams.............................................................................................. 16917.15. Register Description.................................................................................................................171

18. Timer/Counter 0, 1 Prescalers...............................................................................18418.1. Internal Clock Source...............................................................................................................18418.2. Prescaler Reset........................................................................................................................18418.3. External Clock Source..............................................................................................................18418.4. Register Description.................................................................................................................186

19. PSC – Power Stage Controller..............................................................................18819.1. Features................................................................................................................................... 18819.2. Overview.................................................................................................................................. 18819.3. Accessing 16-bit registers........................................................................................................ 18819.4. PSC description........................................................................................................................18919.5. Functional description.............................................................................................................. 19019.6. Update of values...................................................................................................................... 19419.7. Overlap Protection....................................................................................................................19419.8. Signal Description.................................................................................................................... 19519.9. PSC Input.................................................................................................................................19619.10. PSC input modes 001b to 10xb: Deactivate outputs without changing timing.........................19919.11. PSC Input Mode 11xb: Halt PSC and wait for software action.................................................19919.12. Analog Synchronization........................................................................................................... 19919.13. Interrupt handling..................................................................................................................... 20019.14. PSC clock sources...................................................................................................................20019.15. Interrupts..................................................................................................................................20119.16. Register Description.................................................................................................................201

20. Serial Peripheral Interface (SPI)............................................................................21420.1. Features................................................................................................................................... 21420.2. Overview.................................................................................................................................. 21420.3. SS Pin Functionality................................................................................................................. 218

ATmegaS64M1


20.4. Data Modes..............................................................................................................................21820.5. Register Description.................................................................................................................219

21. CAN – Controller Area Network.............................................................................22621.1. Features................................................................................................................................... 22621.2. Overview.................................................................................................................................. 22621.3. CAN protocol............................................................................................................................22621.4. CAN Controller......................................................................................................................... 23121.5. CAN channel............................................................................................................................ 23221.6. Message objects...................................................................................................................... 23521.7. CAN timer.................................................................................................................................23921.8. Error management................................................................................................................... 23921.9. Interrupts.................................................................................................................................. 24121.10. Examples of CAN Baud Rate Setting.......................................................................................24321.11. Register Description.................................................................................................................245

22. LIN / UART - Local Interconnect Network Controller or UART..............................27622.1. Features................................................................................................................................... 27622.2. Overview.................................................................................................................................. 27622.3. LIN protocol..............................................................................................................................27722.4. LIN / UART controller............................................................................................................... 27822.5. LIN / UART description.............................................................................................................28322.6. Register Description.................................................................................................................292

23. Analog-to-Digital Converter (ADC)........................................................................ 30623.1. Features................................................................................................................................... 30623.2. Overview.................................................................................................................................. 30623.3. Description............................................................................................................................... 30823.4. Starting a Conversion...............................................................................................................30823.5. Prescaling and Conversion Timing...........................................................................................30923.6. Changing Channel or Reference Selection..............................................................................31223.7. ADC Noise Canceler................................................................................................................ 31423.8. ADC Conversion Result........................................................................................................... 31823.9. Temperature Measurement...................................................................................................... 32023.10. Amplifier................................................................................................................................... 32123.11. Register Description.................................................................................................................324

24. ISRC - Current Source.......................................................................................... 33724.1. Features................................................................................................................................... 33724.2. Typical Applications..................................................................................................................33724.3. Register Description.................................................................................................................339

25. AC – analog comparator........................................................................................34225.1. Features................................................................................................................................... 34225.2. Overview.................................................................................................................................. 34225.3. Use of ADC amplifiers..............................................................................................................34425.4. Register Description.................................................................................................................344

ATmegaS64M1


26. DAC – Digital to Analog Converter........................................................................35526.1. Features................................................................................................................................... 35526.2. Overview.................................................................................................................................. 35526.3. Operation..................................................................................................................................35626.4. Starting a conversion................................................................................................................35726.5. Register Description.................................................................................................................357

27. debugWIRE On-chip Debug System.....................................................................36127.1. Features................................................................................................................................... 36127.2. Overview.................................................................................................................................. 36127.3. Physical Interface.....................................................................................................................36127.4. Software Breakpoints............................................................................................................... 36227.5. Limitations of debugWIRE........................................................................................................36227.6. Register Description.................................................................................................................362

28. Boot Loader Support – Read-While-Write Self-programming (BTLDR)................ 36428.1. Features................................................................................................................................... 36428.2. Overview.................................................................................................................................. 36428.3. Application and Boot Loader Flash Sections............................................................................36428.4. Read-While-Write and No Read-While-Write Flash Sections...................................................36528.5. Boot Loader Lock Bits.............................................................................................................. 36728.6. Entering the Boot Loader Program...........................................................................................36828.7. Addressing the Flash During Self-Programming......................................................................36928.8. Self-Programming the Flash.....................................................................................................37028.9. Register Description.................................................................................................................378

29. Memory Programming (MEMPROG).....................................................................38129.1. Program And Data Memory Lock Bits......................................................................................38129.2. Fuse Bits.................................................................................................................................. 38229.3. PSC Output Behavior During Reset.........................................................................................38329.4. Signature Bytes........................................................................................................................38529.5. Calibration Byte........................................................................................................................38529.6. Page Size.................................................................................................................................38629.7. Parallel Programming Parameters, Pin Mapping, and Commands..........................................38629.8. Parallel Programming...............................................................................................................38829.9. Serial Downloading.................................................................................................................. 395

30. Electrical Characteristics....................................................................................... 40230.1. Absolute Maximum Ratings*.................................................................................................... 40230.2. DC Characteristics................................................................................................................... 40230.3. Clock Characteristics................................................................................................................40430.4. External Clock Drive Characteristics........................................................................................40630.5. System and Reset Characteristics........................................................................................... 40730.6. PLL Characteristics.................................................................................................................. 40830.7. SPI Timing Characteristics....................................................................................................... 40830.8. ADC Characteristics.................................................................................................................40930.9. Parallel Programming Characteristics...................................................................................... 411

ATmegaS64M1


30.10. Typical Characteristics............................................................................................................. 413

31. Typical Characteristics...........................................................................................42431.1. Pin Pull-Up............................................................................................................................... 42431.2. Pin Driver Strength...................................................................................................................42531.3. Pin Thresholds and Hysteresis.................................................................................................42631.4. BOD Thresholds and Analog Comparator Hysteresis..............................................................43131.5. Internal Oscillator Speed..........................................................................................................432

32. Register Summary.................................................................................................435

33. Instruction Set Summary....................................................................................... 439

34. Packaging Information...........................................................................................44434.1. CQFP32................................................................................................................................... 44434.2. TQFP32....................................................................................................................................445

35. Revision History.....................................................................................................44635.1. Rev. A - 06/2017.......................................................................................................................44635.2. Rev. B - 03/2018.......................................................................................................................446

The Microchip Web Site.............................................................................................. 447

Customer Change Notification Service........................................................................447

Customer Support....................................................................................................... 447

Microchip Devices Code Protection Feature............................................................... 447

Legal Notice.................................................................................................................448

Trademarks................................................................................................................. 448

Quality Management System Certified by DNV...........................................................449

Worldwide Sales and Service......................................................................................450

ATmegaS64M1


1. Space Quality GradeThe ATmegaS64M1 has been developed and manufactured according to the most stringent requirementsof MIL-PRF-38535 International Standards and Aerospace AEQA0239 specification. This datasheetprovides limit values extracted from the results of extensive characterization (versus temperature andvoltage). The quality and reliability of the ATmegaS64M1 have been verified during regular productqualification in compliance with MIL-PRF-38535 and MIL-STD-883 standards.

ATmegaS64M1Space Quality Grade


2. DescriptionThe AVR core combines a rich instruction set with 32 general-purpose working registers. All 32 registersare directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to beaccessed in one single instruction executed in one clock cycle. The resulting architecture is more code-efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmegaS64M1 provides the following features: 64Kbytes of In-System Programmable Flash withRead-While-Write capabilities(1), 2Kbytes EEPROM, 4Kbytes SRAM, 27 general-purpose I/O lines, 32general-purpose working registers, one Motor Power Stage Controller, two flexible Timer/Counters withcompare modes and PWM, one UART with HW LIN, an 11-channel 10-bit ADC with two differential inputstages with programmable gain, a 10-bit DAC, a programmable Watchdog Timer with internal individualoscillator, an SPI serial port, an On-chip Debug system and four software-selectable power savingmodes.

The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports, CAN, LIN/UART andinterrupt system to continue functioning. The Power-down mode saves the register contents but freezesthe oscillator, disabling all other chip functions until the next interrupt or hardware reset. The ADC NoiseReduction mode stops the CPU and all I/O modules except the ADC, thus minimizing switching noiseduring ADC conversions. In Standby mode, the crystal/resonator oscillator is running while the rest of thedevice is sleeping. This allows very fast start-up combined with low power consumption.

The device is manufactured using our 0.35 µm CMOS and high-density nonvolatile memory technology(AT35K4 process). The on-chip ISP Flash allows the program memory to be reprogrammed in-systemthrough an SPI serial interface, by a conventional nonvolatile memory programmer, or by an on-chip bootprogram running on the AVR core. The boot program can use any interface to download the applicationprogram in the application Flash memory. Software in the boot Flash section continues to run while theapplication Flash section is updated, providing true Read-While-Write operation. By combining an 8-bitRISC CPU with in-system self-programmable Flash on a monolithic chip, the ATmegaS64M1 is apowerful microcontroller that provides a highly flexible and cost-effective solution to many embeddedcontrol applications in a Space environment.

The ATmegaS64M1 is supported by a full suite of program and system development tools including Ccompilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

Note: 1. Refer to the product radiation report and dedicated application notes.

ATmegaS64M1Description


3. Block diagramFigure 3-1. Block diagram.

Flash programmemory

Instructionregister

Instructiondecoder

Programcounter

Control lines

32 x 8generalpurposeregistrers

ALU

Statusand control

I/O lines

EEPROM

Data bus 8-bit

DataSRAM

Dire

ct a

ddre

ssin

g

Indi

rect

add

ress

ing

Interruptunit

SPIunit

Watchdogtimer

Four analogcomparators

DAC

ADC

MPSC

Timer 1

Timer 0

HW LIN/UART

CANCurrent source

ATmegaS64M1Block diagram


4. Pin configurationsFigure 4-1. ATmegaS64M1 Pinout.

12345678

2423222120191817

(PCINT18/PSCIN2/OC1A/MISO_A) PD2(PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A) PD3

(PCINT9/PSCIN1/OC1B/SS_A) PC1VCCGND

(PCINT10/T0/TXCAN) PC2(PCINT11/T1/RXCAN/ICP1B) PC3(PCINT0/MISO/PSCOUT2A) PB0

PB4 (AMP0+/PCINT4) PB3 (AMP0-/PCINT3)PC6 (ADC10/ACMP1/PCINT14)AREF(ISRC)AGNDAVCCPC5 (ADC9/ACMP3/AMP1+/PCINT13)PC4 (ADC8/ACMPN3/AMP1-/PCINT12)

32 31 30 29 28 27 26 25

9 10 11 12 13 14 15 16

(PC

INT1

/MO

SI/P

SCO

UT2

B) P

B1(P

CIN

T25/

OC

0B/X

TAL1

) PE1

(PC

INT2

6/AD

C0/

XTAL

2) P

E2(P

CIN

T20/

ADC

1/R

XD/R

XLIN

/ICP1

A/SC

K_A)

PD

4(A

DC

2/AC

MP2

/PC

INT2

1) P

D5

(AD

C3/

ACM

PN2/

INT0

/PC

INT2

2) P

D6

(AC

MP0

/PC

INT2

3) P

D7

(AD

C5/

INT1

/AC

MPN

0/PC

INT2

) PB2

PD

1(PC

INT1

7/PS

CIN

0/C

LKO

)P

E0

(PC

INT2

4/R

ESET

/OC

D)

PC

0(PC

INT8

/INT3

/PSC

OU

T1A)

P

D0

(PC

INT1

6/PS

CO

UT0

A)PB

7 (A

DC

4/PS

CO

UT0

B/SC

K/PC

INT7

)PB

6 (A

DC

7/PS

CO

UT1

B/PC

INT6

)PB

5 (A

DC

6/IN

T2/A

CM

PN1/

AMP2

-/PC

INT5

)PC

7 (D

2A/A

MP2

+/PC

INT1

5)

ATmegaS64M1Pin configurations


4.1 Pin DescriptionsTable 4-1. Pinout Description

PinNo.

Mnemonic

Type Name, Function

Standard Function Alternate Function

4 VCC Power Digital Power Supply

5 GND Power Ground: 0V reference

19 AVCC Power Analog Power Supply–this pin supplies the voltage for the A/D Converter, D/AConverter, Current source. It should be externally connected to VCC, even if the ADC,DAC are not used. If the ADC is used, it should be connected to VCC through a low-pass filter.

20 AGND Power Analog ground–0V reference for analog part.

21 AREF Power Analog reference–reference for analogconverter. This is the reference voltage ofthe A/D converter.

As output, can be used by external analog.ISRC (Current Source Output)

8 PB0 I/O Port B is an 8-bit bi-directional I/O portwith internal pull-up resistors (selectedfor each bit). The Port B output buffershave symmetrical drive characteristicswith both high sink and source capability.As inputs, Port B pins that are externallypulled low will source current if the pull-up resistors are activated. The Port Bpins are tri-stated when a reset conditionbecomes active, even if the clock is notrunning.

MISO (SPI Master In Slave Out)PSCOUT2A (PSC Module 2 Output A)

PCINT0 (Pin Change Interrupt 0)

9 PB1 I/O MOSI (SPI Master Out Slave In)PSCOUT2B (PSC Module 2 Output B)


16 PB2 I/O ADC5 (Analog Input Channel 5)INT1 (External Interrupt 1 Input)

ACMPN0 (Analog Comparator 0 NegativeInput)


23 PB3 I/O AMP0- (Analog Differential Amplifier 0Negative Input)PCINT3 (Pin Change Interrupt 3)

24 PB4 I/O AMP0+ (Analog Differential Amplifier 0Positive Input)PCINT4 (Pin Change Interrupt 4)

26 PB5 I/O ADC6 (Analog Input Channel 6)INT2 (External Interrupt 2 Input)

ACMPN1 (Analog Comparator 1 NegativeInput)

AMP2- (Analog Differential Amplifier 2Negative Input)



PinNo.

Mnemonic

Type Name, Function



27 PB6 I/O ADC7 (Analog Input Channel 7)PSCOUT1B (PSC Module 1 Output A)


28 PB7 I/O ADC4 (Analog Input Channel 4)PSCOUT0B (PSC Module 0 Output B)

SCK (SPI Clock)


30 PC0 I/O Port C is an 8-bit bi-directional I/O portwith internal pull-up resistors (selectedfor each bit). The Port C output buffershave symmetrical drive characteristicswith both high sink and source capability.As inputs, Port C pins that are externallypulled low will source current if the pull-up resistors are activated. The Port Cpins are tri-stated when a reset conditionbecomes active, even if the clock is notrunning.

PSCOUT1A (PSC Module 1 Output A)INT3 (External Interrupt 3 Input)


3 PC1 I/O PSCIN1 (PSC Digital Input 1)OC1B (Timer 1 Output Compare B)

SS_A (Alternate SPI Slave Select)


6 PC2 I/O T0 (Timer 0 clock input)TXCAN (CAN Transmit Output)


7 PC3 I/O T1 (Timer 1 clock input)RXCAN (CAN Receive Input)

ICP1B (Timer 1 input capture alternate Binput)


17 PC4 I/O ADC8 (Analog Input Channel 8)AMP1- (Analog Differential Amplifier 1Negative Input)

ACMPN3 (Analog Comparator 3 NegativeInput )


18 PC5 I/O ADC9 (Analog Input Channel 9)AMP1+ (Analog Differential Amplifier 1Positive Input)

ACMP3 (Analog Comparator 3 PositiveInput)



PinNo.

Mnemonic

Type Name, Function



22 PC6 I/O ADC10 (Analog Input Channel 10)ACMP1 (Analog Comparator 1 PositiveInput)


25 PC7 I/O D2A (DAC output)AMP2+ (Analog Differential Amplifier 2Positive Input)


29 PD0 I/O Port D is an 8-bit bi-directional I/O portwith internal pull-up resistors (selectedfor each bit). The Port D output buffershave symmetrical drive characteristicswith both high sink and source capability.As inputs, Port D pins that are externallypulled low will source current if the pull-up resistors are activated. The Port Dpins are tri-stated when a reset conditionbecomes active, even if the clock is notrunning.

PSCOUT0A (PSC Module 0 Output A)PCINT16 (Pin Change Interrupt 16)

32 PD1 I/O PSCIN0 (PSC Digital Input 0)CLKO (System Clock Output)


1 PD2 I/O OC1A (Timer 1 Output Compare A)PSCIN2 (PSC Digital Input 2)

MISO_A (Programming & alternate SPIMaster In Slave Out)


2 PD3 I/O TXD (UART Tx data)TXLIN (LIN Transmit Output)

OC0A (Timer 0 Output Compare A)

SS (SPI Slave Select)

MOSI_A (Programming & alternate MasterOut SPI Slave In)


12 PD4 I/O ADC1 (Analog Input Channel 1)RXD (UART Rx data)

RXLIN (LIN Receive Input)

ICP1A (Timer 1 input capture alternate Ainput)

SCK_A (Programming & alternate SPIClock)




PinNo.

Mnemonic

Type Name, Function


13 PD5 I/O ADC2 (Analog Input Channel 2)ACMP2 (Analog Comparator 2 PositiveInput)


14 PD6 I/O ADC3 (Analog Input Channel 3)ACMPN2 (Analog Comparator 2 NegativeInput)

INT0 (External Interrupt 0 Input)


15 PD7 I/O ACMP0 (Analog Comparator 0 PositiveInput)PCINT23 (Pin Change Interrupt 23)

31 PE0 I/O or I Port E is an 3-bit bi-directional I/O portwith internal pull-up resistors (selectedfor each bit). The Port E output buffershave symmetrical drive characteristicswith both high sink and source capability.As inputs, Port E pins that are externallypulled low will source current if the pull-up resistors are activated. The Port Epins are tri-stated when a reset conditionbecomes active, even if the clock is notrunning.If the RSTDISBL Fuse is programmed,PE0 is used as an I/O pin. Note that theelectrical characteristics of PE0 differfrom those of the other pins of Port E.

If the RSTDISBL Fuse is unprogrammed,PE0 is used as a reset input. A low levelon this pin for longer than the minimumpulse length will generate a reset, even ifthe clock is not running.

Depending on the clock selection fusesettings, PE1 can be used as input to theinverting Oscillator amplifier and input tothe internal clock operating circuit.

Depending on the clock selection fusesettings, PE2 can be used as output fromthe inverting Oscillator amplifier.

RESET (Reset Input)OCD (On Chip Debug I/O)


10 PE1 I/O XTAL1 (XTAL Input)OC0B (Timer 0 Output Compare B)


11 PE2 I/O XTAL2 (XTAL Output)ADC0 (Analog Input Channel 0)




5. Ordering InformationOrdering Code Speed (MHz) Power Supply Package Flow

ATmegaS64M1-KH-E

8 MHz 3.0–3.6VCQFP32

Engineering Samples

ATmegaS64M1-KH-MQ QML-Q equivalent

ATmegaS64M1-KH-SV QML-V equivalent

ATmegaS64M1-MA-HP TQFP32 Hirel Plastic

ATmegaS64M1Ordering Information


6. ResourcesA comprehensive set of development tools, application notes, and datasheets are available for downloadon http://www.microchip.com/design-centers/8-bit/microchip-avr-mcus.

ATmegaS64M1Resources


http://www.microchip.com/design-centers/8-bit/microchip-avr-mcus

7. About code examplesThis documentation contains simple code examples that briefly show how to use various parts of thedevice. Be aware that not all C compiler vendors include bit definitions in the header files and interrupthandling in C is compiler dependent. Please confirm with the C compiler documentation for more details.

These code examples assume that the part specific header file is included before compilation. For I/Oregisters located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must bereplaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with"SBRS", "SBRC", "SBR", and "CBR".

ATmegaS64M1About code examples


8. AVR CPU Core

8.1 OverviewThis section discusses the AVR core architecture in general. The main function of the CPU core is toensure correct program execution. The CPU must, therefore, be able to access memories, performcalculations, control peripherals, and handle interrupts.

Figure 8-1. Block Diagram of the AVR Architecture

Register file

Flash program memory

Program counter

Instruction register

Instruction decode

Data memory

ALUStatus register

R0R1R2R3R4R5R6R7R8R9

R10R11R12R13R14R15R16R17R18R19R20R21R22R23R24R25

R26 (XL)R27 (XH)R28 (YL)R29 (YH)R30 (ZL)R31 (ZH)

Stack pointer

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separatememories and buses for program and data. Instructions in the program memory are executed with asingle level pipelining. While one instruction is being executed, the next instruction is pre-fetched from theprogram memory. This concept enables instructions to be executed in every clock cycle. The programmemory is In-System Reprogrammable Flash memory.

The fast-access register file contains 32 x 8-bit general purpose working registers with a single clockcycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALUoperation, two operands are output from the register file, the operation is executed, and the result isstored back in the register file – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for data spaceaddressing – enabling efficient address calculations. One of these address pointers can be used as an

ATmegaS64M1AVR CPU Core


address pointer for lookup tables in Flash program memory. These added function registers are the 16-bitX-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and aregister. Single register operations can also be executed in the ALU. After an arithmetic operation, theStatus register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directlyaddress the whole address space. Most AVR instructions have a single 16-bit word format. Everyprogram memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided into two sections, the Boot Program section and the ApplicationProgram section. Both sections have dedicated Lock bits for write and read/write protection. The SPMinstruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.The Stack is effectively allocated in the general data SRAM, and consequently, the Stack size is onlylimited by the total SRAM size and the usage of the SRAM. All user programs must initialize the StackPointer (SP) in the Reset routine (before subroutines or interrupts are executed). The SP is read/writeaccessible in the I/O space. The data SRAM can easily be accessed through the five different addressingmodes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional global interruptenable bit in the Status register. All interrupts have a separate interrupt vector in the interrupt vector table.The interrupts have priority in accordance with their interrupt vector position. The lower the interruptvector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control registers, SPI, andother I/O functions. The I/O memory can be accessed directly, or as the data space locations followingthose of the register file, 0x20 - 0x5F. In addition, this device has extended I/O space from 0x60 - 0xFF inSRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

8.2 Arithmetic Logic Unit (ALU)The high-performance AVR ALU operates in direct connection with all the 32 general purpose workingregisters. Within a single clock cycle, arithmetic operations between general purpose registers orbetween a register and an immediate are executed. The ALU operations are divided into three maincategories: arithmetic, logical, and bit-functions. Some implementations of the architecture provide apowerful multiplier supporting both signed/unsigned multiplication and fractional format. See InstructionSet Summary section for a detailed description.

Related LinksInstruction Set Summary

8.3 Status RegisterThe Status register contains information about the result of the most recently executed arithmeticinstruction. This information can be used for altering program flow in order to perform conditionaloperations. The Status register is updated after all ALU operations, as specified in the instruction setreference. This will in many cases remove the need for using the dedicated compare instructions,resulting in faster and more compact code.



The Status register is not automatically stored when entering an interrupt routine and restored whenreturning from an interrupt. This must be handled by software.



8.3.1 Status Register

Name: SREGOffset: 0x5FReset: 0x00Property: When addressing as I/O register: address offset is 0x3F

When addressing I/O registers as data space using LD and ST instructions, the provided offset must beused. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in anI/O address offset within 0x00 - 0x3F.

Bit 7 6 5 4 3 2 1 0 I T H S V N Z C

Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0

Bit 7 – I Global Interrupt EnableThe Global Interrupt Enable bit must be set for interrupts to be enabled. The individual interrupt enablecontrol is then performed in separate control registers. If the Global Interrupt Enable Register is cleared,none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit iscleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enablesubsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLIinstructions, as described in the instruction set reference.

Bit 6 – T Copy StorageThe Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination forthe operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and abit in T can be copied into a bit in a register in the register file by the BLD instruction.

Bit 5 – H Half Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. Half carry flag is useful in BCDarithmetic. See the Instruction Set Description for detailed information.

Bit 4 – S Sign Flag, S = N ㊉ V

The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flagV. See the Instruction Set Description for detailed information.

Bit 3 – V Two’s Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetic. See the Instruction SetDescription for detailed information.

Bit 2 – N Negative FlagThe negative flag N indicates a negative result in an arithmetic or logic operation. See the Instruction SetDescription for detailed information.

Bit 1 – Z Zero FlagThe zero flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction SetDescription for detailed information.



Bit 0 – C Carry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Descriptionfor detailed information.

8.4 General Purpose Register FileThe register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the requiredperformance and flexibility, the following input/output schemes are supported by the register file:

• One 8-bit output operand and one 8-bit result input• Two 8-bit output operands and one 8-bit result input• Two 8-bit output operands and one 16-bit result input• One 16-bit output operand and one 16-bit result input

Figure 8-2. AVR CPU General Purpose Working Registers7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

Most of the instructions operating on the register file have direct access to all registers, and most of themare single cycle instructions. As shown in the figure, each register is also assigned a data memoryaddress, mapping them directly into the first 32 locations of the user data space. Although not beingphysically implemented as SRAM locations, this memory organization provides great flexibility in accessof the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.

8.4.1 The X-register, Y-register, and Z-registerThe registers R26...R31 have some added functions to their general purpose usage. These registers are16-bit address pointers for indirect addressing of the data space. The three indirect address registers X,Y, and Z are defined as described in the figure.



Figure 8-3. The X-, Y-, and Z-registers15 XH XL 0

X-register 7 0 7 0

R27 R26

15 YH YL 0

Y-register 7 0 7 0

R29 R28

15 ZH ZL 0

Z-register 7 0 7 0

R31 R30

In the different addressing modes, these address registers have functions as fixed displacement,automatic increment, and automatic decrement (see the instruction set reference for details).

Related LinksInstruction Set Summary

8.5 Stack PointerThe stack is mainly used for storing temporary data, local variables, and return addresses after interruptsand subroutine calls. The stack is implemented as growing from higher to lower memory locations. TheStack Pointer register always points to the top of the stack.

The stack pointer points to the data SRAM stack area where the subroutine and interrupt stacks arelocated. A stack PUSH command will decrease the stack pointer. The stack in the data SRAM must bedefined by the program before any subroutine calls are executed or interrupts are enabled. Initial stackpointer value equals the last address of the internal SRAM and the stack pointer must be set to pointabove start of the SRAM. See the table for stack pointer details.

Table 8-1. Stack Pointer Instructions

Instruction Stack Pointer Description

PUSH Decremented by 1 Data is pushed onto the stack

CALL

ICALL

RCALL

Decremented by 2 Return address is pushed onto the stack with a subroutine call orinterrupt

POP Incremented by 1 Data is popped from the stack

RET

RETI

Incremented by 2 Return address is popped from the stack with return from subroutine orreturn from interrupt



The AVR stack pointer is implemented as two 8-bit registers in the I/O space. The number of bits actuallyused is implementation dependent. Note that the data space in some implementations of the AVRarchitecture is so small that only SPL is needed. In this case, the SPH register will not be present.



8.5.1 Stack Pointer Register Low and High byte

Name: SPL and SPHOffset: 0x5DReset: 0x10FFProperty: When addressing I/O Registers as data space the offset address is 0x3D

The SPL and SPH register pair represents the 16-bit value, SP.The low byte [7:0] (suffix L) is accessibleat the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.

When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. Whenaddressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these offsetaddresses.

Bit 15 14 13 12 11 10 9 8 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8

Access RW RW RW RW RW RW RW RW Reset 0 0 0 1 0 0 0 0

Bit 7 6 5 4 3 2 1 0 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – SP Stack Pointer RegisterSPL and SPH are combined into SP.

8.6 Accessing 16-Bit RegistersThe AVR data bus has a width of 8 bit, and so accessing 16-bit registers requires atomic operations.These registers must be byte accessed using two read or write operations. 16-bit registers are connectedto the 8-bit bus and a temporary register using a 16-bit bus.

For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byteis then written into the temporary register. When the high byte of the 16-bit register is written, thetemporary register is copied into the low byte of the 16-bit register in the same clock cycle.

For a read operation, the low byte of the 16-bit register must be read before the high byte. When the lowbyte register is read by the CPU, the high byte of the 16-bit register is copied into the temporary registerin the same clock cycle as the low byte is read. When the high byte is read, it is then read from thetemporary register.

This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously whenreading or writing the register.

Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bitregister during an atomic 16-bit read/write operation. To prevent this, interrupts can be disabled whenwriting or reading 16-bit registers.

The temporary registers can be read and written directly from user software.



8.7 Instruction Execution TimingThis section describes the general access timing concepts for instruction execution. The AVR CPU isdriven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internalclock division is used. The figure below shows the parallel instruction fetches and instruction executionsenabled by the Harvard architecture and the fast-access register file concept. This is the basic pipeliningconcept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,functions per clocks, and functions per power unit.

Figure 8-4. The Parallel Instruction Fetches and Instruction Executions

clk

1st Instruction Fetch1st Instruction Execute

2nd Instruction Fetch2nd Instruction Execute

3rd Instruction Fetch3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

The following figure shows the internal timing concept for the register file. In a single clock cycle, an ALUoperation using two register operands is executed and the result is stored back to the destination register.

Figure 8-5. Single Cycle ALU Operation

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clkCPU

8.8 Reset and Interrupt HandlingThe AVR provides several different interrupt sources. These interrupts and the separate Reset vectoreach have a separate program vector in the program memory space. All interrupts are assignedindividual enable bits, which must be written logic one together with the global interrupt enable bit in theStatus register in order to enable the interrupt. Depending on the program counter value, interrupts maybe automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improvessoftware security.

The lowest addresses in the program memory space are by default defined as the Reset and interruptvectors. They have determined priority levels: The lower the address the higher is the priority level.RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The interrupt vectorscan be moved to the start of the boot Flash section by setting the IVSEL bit in the MCU Control Register(MCUCR). The Reset vector can be moved to the start of the boot Flash section by programming theBOOTRST Fuse.



When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. Theuser software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can theninterrupt the current interrupt routine. The I-bit is automatically set when a return from interrupt instruction– RETI – is executed.

There are basically two types of interrupts:

The first type is triggered by an event that sets the interrupt flag. For these interrupts, the programcounter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, andhardware clears the corresponding interrupt flag. Interrupt flags can be cleared by writing a logic one tothe flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interruptenable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or theflag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interruptenable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the globalinterrupt enable bit is set and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts donot necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled,the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the mainprogram and execute one more instruction before any pending interrupt is served.

The Status register is not automatically stored when entering an interrupt routine, nor restored whenreturning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. Nointerrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLIinstruction. The following example shows how this can be used to avoid interrupts during the timedEEPROM write sequence.

Assembly Code Example(1)

in r16, SREG ; store SREG valuecli ; disable interrupts during timed sequencesbi EECR, EEMPE ; start EEPROM writesbi EECR, EEPEout SREG, r16 ; restore SREG value (I-bit)

C Code Example(1)

char cSREG;cSREG = SREG; /* store SREG value *//* disable interrupts during timed sequence */_CLI();EECR |= (1

C Code Example(1)

__enable_interrupt(); /* set Global Interrupt Enable */__sleep(); /* enter sleep, waiting for interrupt *//* note: will enter sleep before any pending interrupt(s) */

1. Refer to About Code Examples.

Related LinksMemory ProgrammingBoot Loader Support – Read-While-Write Self-Programming

8.8.1 Interrupt Response TimeThe interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. Afterfour clock cycles, the program vector address for the actual interrupt handling routine is executed. Duringthis four clock cycle period, the program counter is pushed onto the stack. The vector is normally a jumpto the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of amulti-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurswhen the microcontroller (MCU) is in Sleep mode, the interrupt execution response time is increased byfour clock cycles. This increase comes in addition to the start-up time from the selected Sleep mode. Areturn from an interrupt handling routine takes four clock cycles. During these four clock cycles, theprogram counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, andthe I-bit in SREG is set.



9. AVR Memories

9.1 OverviewThis section describes the different memory types in the device. The AVR architecture has two mainmemory spaces, the Data Memory and the Program Memory space. In addition, the device features anEEPROM Memory for data storage. All memory spaces are linear and regular.

9.2 In-System Reprogrammable Flash Program MemoryThe ATmegaS64M1 contains 64Kbytes on-chip in-system reprogrammable Flash memory for programstorage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 32K x 16.

The ATmegaS64M1 Program Counter (PC) is 15 bits wide, thus addressing the 32K program memorylocations. The operation of the Boot Program section and associated Boot Lock bits for softwareprotection are described in detail in Boot Loader Support – Read-While-Write Self-Programming. Refer toMemory Programming for the description of Flash data serial downloading using the SPI pins.

Constant tables can be allocated within the entire program memory address space, using the LoadProgram Memory (LPM) instruction.

Timing diagrams for instruction fetch and execution are presented in Instruction Execution Timing.

Figure 9-1. Program Memory Map ATmegaS64M1

0x0000

0x7FFF

Program Memory

Application Flash Section

Boot Flash Section

Related LinksBoot Loader Support – Read-While-Write Self-programming (BTLDR)Memory Programming (MEMPROG)Instruction Execution Timing

ATmegaS64M1AVR Memories


9.3 SRAM Data MemoryThe following figure shows how the device SRAM memory is organized.

The device is a complex microcontroller with more peripheral units than can be supported within the 64locations reserved in the Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 -0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The lower 4352 data memory locations address both the register file, the I/O memory, extended I/Omemory, and the internal data SRAM. The first 32 locations address the register file, the next 64 locationthe standard I/O memory, then 160 locations of extended I/O memory, and the next 4K locations addressthe internal data SRAM.

The five different addressing modes for the data memory cover:• Direct

– The direct addressing reaches the entire data space.• Indirect with Displacement

– The indirect with displacement mode reaches 63 address locations from the base addressgiven by the Y- or Z-register.

• Indirect– In the register file, registers R26 to R31 feature the indirect addressing pointer registers.

• Indirect with Pre-decrement– The address registers X, Y, and Z are decremented.

• Indirect with Post-increment– The address registers X, Y, and Z are incremented.

The 32 general purpose working registers, 64 I/O registers, 160 extended I/O registers, and the 4K bytesof internal data SRAM in the device are all accessible through all these addressing modes.

Figure 9-2. Data Memory Map with 4096 Byte Internal Data SRAM

(4096x8)

0x10FF

9.3.1 Data Memory Access TimesThe internal data SRAM access is performed in two clkCPU cycles as described in the following Figure.



Figure 9-3. On-chip Data SRAM Access Cycles

clk

WR

RD

Data

Data

Address Address valid

T1 T2 T3

Compute Address

Rea

dW

rite

CPU

Memory Access Instruction Next Instruction

9.4 EEPROM Data MemoryThe ATmegaS64M1 contains 2KB of data EEPROM memory. It is organized as a separate data space, inwhich single bytes can be read and written. The access between the EEPROM and the CPU is describedin the following, specifying the EEPROM Address registers, the EEPROM Data register, and theEEPROM Control register.

See the related links for a detailed description on EEPROM Programming in SPI or Parallel Programmingmode.

Related LinksMemory Programming (MEMPROG)

9.4.1 EEPROM Read/Write AccessThe EEPROM access registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 9-2. A self-timing function, however, lets the usersoftware detect when the next byte can be written. If the user code contains instructions that write theEEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fallslowly on power-up/down. This causes the device for some period of time to run at a voltage lower thanspecified as a minimum for the clock frequency used. Refer to Preventing EEPROM Corruption for detailson how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer tothe description of the EEPROM Control register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction isexecuted. When the EEPROM is written, the CPU is halted for two clock cycles before the next instructionis executed.



9.4.2 Preventing EEPROM CorruptionDuring periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low forthe CPU and the EEPROM to operate properly. These issues are the same as for board level systemsusing EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regularwrite sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itselfcan execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be doneby enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does notmatch the needed detection level, an external low VCC Reset protection circuit can be used. If a Resetoccurs while a write operation is in progress, the write operation will be completed provided that thepower supply voltage is sufficient.

9.5 I/O MemoryThe I/O space definition of the device is shown in the Register Summary.

All device I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by theLD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose workingregisters and the I/O space. I/O registers within the address range 0x00-0x1F are directly bit-accessibleusing the SBI and CBI instructions. In these registers, the value of single bits can be checked by usingthe SBIS and SBIC instructions.

When using the I/O specific commands IN and OUT, the I/O addresses 0x00-0x3F must be used. Whenaddressing I/O registers as data space using LD and ST instructions, 0x20 must be added to theseaddresses. The device is a complex microcontroller with more peripheral units than can be supportedwithin the 64 locations reserved in Opcode for the IN and OUT instructions. For the extended I/O spacefrom 0x60..0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/Omemory addresses should never be written.

Some of the status flags are cleared by writing a '1' to them; this is described in the flag descriptions.Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, andcan, therefore, be used on registers containing such status flags. The CBI and SBI instructions work withregisters 0x00-0x1F only.

The I/O and peripherals control registers are explained in later sections.

Related LinksMemory Programming (MEMPROG)Instruction Set Summary

9.5.1 General Purpose I/O RegistersThe device contains three general purpose I/O registers; General purpose I/O register 0/1/2 (GPIOR0/1/2). These registers can be used for storing any information, and they are particularly useful for storingglobal variables and status flags. General purpose I/O registers within the address range 0x00 - 0x1F aredirectly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.



9.6 Register Description

9.6.1 Accessing 16-Bit RegistersThe AVR data bus has a width of 8 bit, and so accessing 16-bit registers requires atomic operations.These registers must be byte accessed using two read or write operations. 16-bit registers are connectedto the 8-bit bus and a temporary register using a 16-bit bus.

For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byteis then written into the temporary register. When the high byte of the 16-bit register is written, thetemporary register is copied into the low byte of the 16-bit register in the same clock cycle.

For a read operation, the low byte of the 16-bit register must be read before the high byte. When the lowbyte register is read by the CPU, the high byte of the 16-bit register is copied into the temporary registerin the same clock cycle as the low byte is read. When the high byte is read, it is then read from thetemporary register.

This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously whenreading or writing the register.

Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bitregister during an atomic 16-bit read/write operation. To prevent this, interrupts can be disabled whenwriting or reading 16-bit registers.

The temporary registers can be read and written directly from user software.



9.6.2 EEPROM Address Register Low and High Byte

Name: EEARL and EEARHOffset: 0x41Reset: 0xXXProperty: When addressing as I/O Register: address offset is 0x21

The EEARL and EEARH register pair represents the 16-bit value, EEAR. The low byte [7:0] (suffix L) isaccessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. Formore details on reading and writing 16-bit registers, refer to accessing 16-bit registers in the sectionabove.


Bit 15 14 13 12 11 10 9 8 EEAR[10:8]

Access R/W R/W R/W Reset x x x

Bit 7 6 5 4 3 2 1 0 EEAR[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x

Bits 10:0 – EEAR[10:0] EEPROM AddressThe EEPROM Address Registers, EEARH and EEARL, specify the EEPROM address in the 2KBEEPROM space. The EEPROM data bytes are addressed linearly between 0 and 1023. The initial valueof EEAR is undefined. A proper value must be written before the EEPROM may be accessed.



9.6.3 EEPROM Data Register

Name: EEDROffset: 0x40Reset: 0x00Property: When addressing as I/O Register: address offset is 0x20


Bit 7 6 5 4 3 2 1 0 EEDR[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0

Bits 7:0 – EEDR[7:0] EEPROM DataFor the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM inthe address given by the EEAR register. For the EEPROM read operation, the EEDR contains the dataread out from the EEPROM at the address given by EEAR.



9.6.4 EEPROM Control Register

Name: EECROffset: 0x3FReset: 0x00Property: When addressing as I/O register: address offset is 0x1F

Bit 7 6 5 4 3 2 1 0 EEPM[1:0] EERIE EEMPE EEPE EERE

Access R/W R/W R/W R/W R/W R/W Reset x x 0 0 x 0

Bits 5:4 – EEPM[1:0] EEPROM Programming Mode BitsThe EEPROM Programming mode bit setting defines which programming action will be triggered whenwriting EEPE. It is possible to program data in one atomic operation (erase the old value and program thenew value) or to split the erase and write operations into two different operations. The programming timesfor the different modes are shown in the table below. While EEPE is set, any write to EEPMn will beignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

Table 9-1. EEPROM Mode Bits

EEPM[1:0] Typ. Programming Time Operation

00 3.4 ms Erase and Write in one operation (Atomic Operation)

01 1.8 ms Erase Only

10 1.8 ms Write Only

11 - Reserved for future use

Bit 3 – EERIE EEPROM Ready Interrupt EnableWriting EERIE to '1' enables the EEPROM ready interrupt if the I bit in SREG is set. Writing EERIE tozero disables the interrupt. The EEPROM ready interrupt generates a constant interrupt when EEPE iscleared. The interrupt will not be generated during EEPROM write or SPM.

Bit 2 – EEMPE EEPROM Master Write EnableThe EEMPE bit determines whether writing EEPE to '1' causes the EEPROM to be written.When EEMPE is '1', setting EEPE within four clock cycles will write data to the EEPROM at the selectedaddress.

If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to '1' by software,hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for anEEPROM write procedure.

Bit 1 – EEPE EEPROM Write EnableThe EEPROM write enable signal EEPE is the write strobe to the EEPROM. When address and data arecorrectly set up, the EEPE bit must be written to '1' to write the value into the EEPROM. The EEMPE bitmust be written to '1' before EEPE is written to '1', otherwise, no EEPROM write takes place. Thefollowing procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is notessential):



1. Wait until EEPE becomes zero.2. Wait until SPMEN in SPMCSR becomes zero.3. Write new EEPROM address to EEAR (optional).4. Write new EEPROM data to EEDR (optional).5. Write a '1' to the EEMPE bit while writing a zero to EEPE in EECR.6. Within four clock cycles after setting EEMPE, write a '1' to EEPE.

The EEPROM cannot be programmed during a CPU write to the Flash memory. The software must checkthat the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant ifthe software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never beingupdated by the CPU, step 2 can be omitted.

CAUTIONAn interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM masterwrite enable will time-out. If an interrupt routine accessing the EEPROM is interrupting anotherEEPROM access, the EEAR or EEDR register will be modified, causing the interruptedEEPROM access to fail. It is recommended to have the global interrupt flag cleared during allthe steps to avoid these problems.

When the write access time has elapsed, the EEPE bit is cleared by hardware. The usersoftware can poll this bit and wait for a zero before writing the next byte. When EEPE has beenset, the CPU is halted for two cycles before the next instruction is executed.

Bit 0 – EERE EEPROM Read EnableThe EEPROM read enable signal EERE is the read strobe to the EEPROM. When the correct address isset up in the EEAR register, the EERE bit must be written to a '1' to trigger the EEPROM read. TheEEPROM read access takes one instruction, and the requested data is available immediately. When theEEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, itis neither possible to read the EEPROM, nor to change the EEAR register.

The calibrated oscillator is used to time t

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Flash, 2 KB EEPROM, 4 KB SRAM, 10-bit ADC, 10-bit DAC, CAN, UART, 12-bit …ww1.microchip.com/downloads/en/DeviceDoc/ATmegaS64M1... · 2018-03-22 · Flash, 2 KB EEPROM, 4 KB SRAM,