Floorplanner Introduction Guide Design Flow Getting ...homepages.cae.wisc.edu/~ece554/website/Xilinx/Floorplanner Guide … · Floorplanning Prerequisites ... features and capabilities

FloorplannerGuide

Floorplanner Guide 3.1i

Introduction

Design Flow

Getting Started

Using the Floorplanner

Glossary

Printed in U.S.A.

Floorplanner Guide

R

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Xilinx Development System

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About This Manual

This manual describes the Xilinx Floorplanner, a graphically basedtool that allows you to interactively and automatically place logicsymbols from a hierarchical design into a Xilinx target FPGA.

Before using this manual, you should be familiar with the operationsthat are common to all Xilinx software tools: how to bring up thesystem, select a tool for use, specify operations, and manage designdata. These topics are covered in the Quick Start Guide. Other publica-tions you can consult for related information are the DevelopmentSystem Reference Guide and the HDL Synthesis for FPGAs Design Guide.

Note This Xilinx software release is certified as Year 2000 compliant.

Manual ContentsThis manual covers the following topics.

Chapter 1,Introduction provides an overview of the Floor-planner interface, including basic operations, input and outputfiles, and supported FPGA architectures.

Chapter 2, Design Flow describes five distinct work flows inwhich you can use the Floorplanner.

Chapter 3, Getting Started describes how to invoke the Floor-planner from the Design Manager or as a standalone tool, andprovides more details about the interface.

Chapter 4, Using the Floorplanner describes several importantfloorplanning procedures for implementing high-density designsin Xilinx devices.

Floorplanner Guide 3.1i i

Floorplanner Guide

Glossary defines the terms used in this manual.

Additional Resources

For additional information, go to http://support.xilinx.com .The following table lists some of the resources you can access fromthis Web site. You can also directly access these resources using theprovided URLs.

Resource Description/URL

Tutorials Tutorials covering Xilinx design flows, from design entry to verificationand debugginghttp://support.xilinx.com/support/techsup/tutorials/index.htm

AnswersDatabase

Current listing of solution records for the Xilinx software toolsSearch this database using the search function athttp://support.xilinx.com/support/searchtd.htm

ApplicationNotes

Descriptions of device-specific design techniques and approacheshttp://support.xilinx.com/apps/appsweb.htm

Data Book Pages from The Programmable Logic Data Book, which contains device-specific information on Xilinx device characteristics, including readback,boundary scan, configuration, length count, and debugginghttp://support.xilinx.com/partinfo/databook.htm

Xcell Journals Quarterly journals for Xilinx programmable logic usershttp://support.xilinx.com/xcell/xcell.htm

Technical Tips Latest news, design tips, and patch information for the Xilinx designenvironmenthttp://support.xilinx.com/support/techsup/journals/index.htm

ii Xilinx Development System

Conventions

This manual uses the following conventions. An example illustrateseach convention.

TypographicalThe following conventions are used for all documents.

Courier font indicates messages, prompts, and program filesthat the system displays.

speed grade: - 100

Courier bold indicates literal commands that you enter in asyntactical statement. However, braces { } in Courier bold arenot literal and square brackets [ ] in Courier bold are literalonly in the case of bus specifications, such as bus [7:0].

rpt_del_net=

Courier bold also indicates commands that you select from amenu.

File Open

Italic font denotes the following items.

Variables in a syntax statement for which you must supplyvalues

edif2ngd design_name

References to other manuals

Floorplanner Guide 3.1i iii

Floorplanner Guide

See the Development System Reference Guide for more informa-tion.

Emphasis in text

If a wire is drawn so that it overlaps the pin of a symbol, thetwo nets are not connected.

Square brackets [ ] indicate an optional entry or parameter.However, in bus specifications, such as bus [7:0], they arerequired.

edif2ngd [option_name] design_name

Braces { } enclose a list of items from which you must chooseone or more.

lowpwr = { on | off }

A vertical bar | separates items in a list of choices.

lowpwr = { on | off }

A vertical ellipsis indicates repetitive material that has beenomitted.

IOB #1: Name = QOUT

IOB #2: Name = CLKIN

.

.

.

A horizontal ellipsis . indicates that an item can be repeatedone or more times.

allow block block_name loc1 loc2locn;

Online DocumentThe following conventions are used for online documents.

Red-underlined text indicates an interbook link, which is a cross-reference to another book. Click the red-underlined text to openthe specified cross-reference.

iv Xilinx Development System

Blue-underlined text indicates an intrabook link, which is a cross-reference within a book. Click the blue-underlined text to openthe specified cross-reference.

Floorplanner Guide v

Floorplanner Guide

vi Xilinx Development System

Contents

About This ManualManual Contents ........................................................................... iAdditional Resources .................................................................... ii

ConventionsTypographical................................................................................ iiiOnline Document .......................................................................... iv

Chapter 1 Introduction

What is the Floorplanner? ............................................................. 1-1Floorplanner Icon .......................................................................... 1-3Why Floorplan? ............................................................................. 1-3Floorplanning Prerequisites .......................................................... 1-3Features of the Floorplanner......................................................... 1-4Supported Architectures................................................................ 1-5New Files ...................................................................................... 1-5Input Files...................................................................................... 1-6Output Files................................................................................... 1-6

Chapter 2 Design Flow

Place and Route, then Floorplan................................................... 2-1Floorplanning Prior to Place and Route ........................................ 2-3Iterative Floorplanning................................................................... 2-4Incremental Design Changes........................................................ 2-5Creating UCF Constraints from IOB Placement............................ 2-7

Chapter 3 Getting Started

Running the Floorplanner.............................................................. 3-1Design Manager Interface............................................................. 3-2Command Line Interface............................................................... 3-4

Floorplanner Guide 3.1i vii

Floorplanner Guide

Floorplanner Interface ................................................................... 3-5Toolbar .................................................................................... 3-5Status Bar ................................................................................ 3-5Mouse ...................................................................................... 3-6Keyboard.................................................................................. 3-6Dialog Boxes............................................................................ 3-7

The Floorplanner Windows ........................................................... 3-8Primary Window....................................................................... 3-8Design Hierarchy Window........................................................ 3-10

Hierarchy Display................................................................ 3-11Selecting Logic ................................................................... 3-11Expanding and Collapsing Hierarchical Groups ................. 3-12Hierarchical Group Annotation............................................ 3-13Symbol Annotation.............................................................. 3-14

Design Nets Window................................................................ 3-15Floorplan Window .................................................................... 3-15

Resource Graphics ............................................................. 3-17Placement Window .................................................................. 3-18

Closing the Current Design ........................................................... 3-18Exiting the Floorplanner ................................................................ 3-19

Chapter 4 Using the Floorplanner

Opening a File............................................................................... 4-3Saving a File ................................................................................. 4-3Using Colors.................................................................................. 4-4

In the Design Hierarchy Window.............................................. 4-4In the Floorplan Window .......................................................... 4-4Distinguishing Logic ................................................................. 4-5

Floorplanning Logic....................................................................... 4-6Floorplanning Designs that Contain RPMs ................................... 4-8

RPM Binding ............................................................................ 4-9Creating Groups............................................................................ 4-9

Manual Grouping ..................................................................... 4-10Automatic Grouping ................................................................. 4-13

Using Area Constraints ................................................................. 4-14Using the UCF Flow ...................................................................... 4-14

Creating UCF Constraints for IOB Placement ......................... 4-15Flattening and Building the Hierarchy ........................................... 4-16

How to Flatten the Hierarchy ................................................... 4-16How to Rebuild the Hierarchy .................................................. 4-17

Walking Through the Design......................................................... 4-17Finding Logic............................................................................ 4-17

viii Xilinx Development System

Contents

Finding Nets............................................................................. 4-17Displaying the Ratsnest ........................................................... 4-18Using the Ratsnest................................................................... 4-18Viewing Selected Nets in the Ratsnest .................................... 4-19

Analyzing PAR Placement ............................................................ 4-19Analyzing PAR Placement for Timing Constraints ........................ 4-22

From the Design Manager ....................................................... 4-22Using Find and Ratsnest to Find Critical Nets ......................... 4-24

Finding Logic Connected to Nets .................................................. 4-26Displaying Resources and Logic................................................... 4-26Performing Detailed Manual Placement........................................ 4-28Checking the Floorplan ................................................................. 4-29Aligning Symbols........................................................................... 4-29Working with Patterns ................................................................... 4-33

Creating a Pattern.................................................................... 4-34Using a Pattern ........................................................................ 4-34

How to Interleave Buses ............................................................... 4-35Design Example....................................................................... 4-35

Iterative Floorplanning................................................................... 4-44Floorplanning Incremental Schematic Changes ........................... 4-45

Design Example....................................................................... 4-45Making Small Modifications to Automatic Placement.................... 4-48Lock Down I/Os from Automatically Placed Design ...................... 4-49Getting Started With an Unfamiliar Design ................................... 4-50

Creating Hierarchy at a Higher Level....................................... 4-50Creating Subgroups............................................................ 4-51

Floorplanning the New Hierarchy............................................. 4-51

Floorplanner Guide ix

Floorplanner Guide

x Xilinx Development System

Chapter 1

Introduction

This chapter describes the graphical interface and the importantfeatures and capabilities of the Xilinx Floorplanner. It contains thefollowing sections.

What is the Floorplanner? is a general introduction to theFloorplanner tool.

Floorplanner Icon shows the icon that appears in the DesignManager window.

Why Floorplan? explains how the Floorplanner can help youimprove the performance and density of your design.

Floorplanning Prerequisites explains the necessary require-ments for successful floorplanning.

Features of the Floorplanner lists the features provided by theFloorplanner.

Supported Architectures lists the Xilinx device families thatFloorplanner supports.

New Files describes the two new file types that Floorplanneruses.

Input Files lists the files that Floorplanner uses as input.

Output Files lists the files that Floorplanner generates.

What is the Floorplanner?The Floorplanner is a graphical placement tool that gives you controlover placing a design into a target FPGA using a drag and dropparadigm with the mouse pointer.

Floorplanner Guide 3.1i 1-1

Floorplanner Guide

The Floorplanner displays a hierarchical representation of the designin the Design Hierarchy window using hierarchy structure lines andcolors to distinguish the different hierarchical levels. The Floorplanwindow displays the floorplan of the target device into which youplace logic from the hierarchy. The following figure shows thewindows on the PC version.

Figure 1-1 Floorplanner Window

Logic symbols represent each level of hierarchy in the Design Hier-archy window. You can modify that hierarchy in the Floorplannerwithout changing the original design.

You use the mouse to select the logic from the Design Hierarchywindow and place it in the FPGA represented in the Floorplanwindow.

Alternatively, you can invoke the Floorplanner after running theautomatic place and route tools to view and possibly improve theresults of the automatic implementation.

1-2 Xilinx Development System

Introduction

Floorplanner IconThe Floorplanner can be started by clicking the Floorplanner icon inthe Design Manager screen. The following figure shows the icon.

Why Floorplan?Floorplanning is an optional methodology to help you improveperformance and density of a fully, automatically placed and routeddesign. Floorplanning is particularly useful on structured designsand data path logic. With the Floorplanner, you see where to placelogic in the floorplan for optimal results, placing data paths exactly atthe desired location on the die.

With the Floorplanner, you can floorplan your design prior to or afterrunning PAR. In an iterative design flow, you floorplan and place androute, interactively. You can modify the logic placement in the Floor-plan window as often as necessary to achieve your design goals. Youcan save the iterations of your floorplanned design to use later as aconstraints file for MAP.

The 3.1i version of the Floorplanner allows you to begin floorplan-ning with just an NGD file generated in a previous flow. You canmanually make IOB assignments which you can then write to a UCFfile. The Floorplanner edits the UCF file by adding the newly createdplacement constraints. The placement constraints you create in theFloorplanner take precedence over existing constraints in the UCF.

Floorplanning PrerequisitesThe Floorplanner is specifically intended to assist those users whorequire some degree of handcrafting for their designs. You mustunderstand both the details of the device architectures and how floor-planning can be used to refine a design. Successful floorplanning isvery much an iterative process and it can take time to develop a floor-plan that outperforms an "automatically" processed design.

Floorplanner Guide 1-3

Floorplanner Guide

Because of the nature of the Floorplanners interaction with the auto-matic MAP and PAR tools, several prerequisites are necessary inorder to floorplan your design successfully.

Detailed knowledge of the specifics of the target architecture andpart

Detailed knowledge of the specifics of the design being imple-mented

A design that lends itself to floorplanning

A willingness to iterate a floorplan to achieve the desired results

Realistic performance and density goals

Features of the FloorplannerThe Floorplanner provides an easy-to-use graphical interface thatoffers the following features.

Interacts at a high level of the design hierarchy, as well as withlow-level elements such as I/Os, function generators, tristatebuffers, flip-flops, and RAM/ROM

Captures and imposes complex patterns, which is useful forrepetitive logic structures such as interleaved buses

Automatically distributes logic into columns or rows

Uses dynamic rubberbanding to show the ratsnest connections

Finds logic or nets by name or connectivity

Permits design hierarchy rearrangement to simplify floorplan-ning

Groups logic by connectivity or function

Offers an alternative UCF flow that allows you to write outgraphically created constraints to a UCF

Allows binding and unbinding of RPMs

Identifies placement problems in the Floorplan window

Provides online help


Introduction

Supported ArchitecturesThe Floorplanner supports all Xilinx architectures in the Spartan/-II, Virtex/-E/-II, and XC4000 device families.

New FilesThere are three file types that Floorplanner uses.

FNF

The Floorplanner Netlist File (FNF) is the floorplanners data-base. Its core function is to retain a record of all the (physical)constraints entered in the Floorplan window. If the FNF is gener-ated using a placed NCD file, the placement information is alsorecorded in the FNF for use by the placement window. Addition-ally, the FNF file retains user-created groups from the DesignHierarchy window. When design modifications are made (modi-fied source files (.ngd) or new placement (.ncd)), the existing FNFfile can be updated with the new information using the File Update command. This allows for design iterations without theloss of your previous work. Any design archive should includethe FNF file to allow subsequent design or constraint modifica-tions.

MFP

The Mapper Floorplan (MFP) file links the Floorplanner to theM1 flow by directing MAP behavior. It is the intervention into themap phase of the flow that permits you to floorplan at the BEL(Basic Element) level. The MFP is a subset (physical constraintsonly) of the FNF file. The FNF2MFP utility is automaticallyinvoked when saving a floorplan, which produces an MFP filefrom the relevant information in the FNF file. The MFP file namealways has the same root name as the FNF file, for example,design.fnf and design.mfp.

Note The Floorplanner cannot read MFP files. You must save theFNF file in order to archive floorplan information.

UCF

The UCF is an ASCII file specifying constraints on the logicaldesign. These constraints affect how the logical design is imple-mented in the target device. The Floorplanner allows you to read


Floorplanner Guide

in an existing UCF file, create constraints graphically in the floor-plan, and write the constraints out to the UCF file. You performthese tasks using the UCF flow.

Input FilesThe Floorplanner can read in the following input files.

NCD

This file is generated by either MAP or PAR. It is used by theFloorplanner during the File Newcommand to generate thephysical design for the FNF file.

NGD

This file is generated by NGDBuild. It is used by the Floorplannerduring the File New command to correlate the physicaldesign to the logical design when creating the FNF file.

FNF

A previous version of this file, which was generated by a File Save in the Floorplanner, can optionally be used in thecreation of a new FNF file. If used, it helps retain designconstraints between floorplanning iterations.

NGD

The File New command allows you to open an NGD sourcedesign file.

UCF

The 3.1i version of the Floorplanner allows you to read in a UCFfile with the File Read Constraints command.

Output FilesThe Floorplanner generates the following output files.

FNF

The FNF file is the Floorplanners database. It can be saved byusing the File Save command.

MFP


Introduction

This file is generated when the FNF file is saved in the Floor-planner. It is used as an input to MAP to transfer physicalconstraints from the Floorplanner back to the automatic imple-mentation tools.

UCF

You can write out constraints created in a UCF flow to a UCF fileby using the File Write Constraints command.


Floorplanner Guide


Chapter 2

Design Flow

This chapter describes the four different design flows that you canuse with the Floorplanner to implement your design in a XilinxFPGA. Accompanying each design flow is a comprehensive flowchart that indicates the programs you use, the input files required,and output files that are generated. The four design flows aredescribed in the following sections.

Place and Route, then Floorplan

Floorplanning Prior to Place and Route

Iterative Floorplanning

Incremental Design Changes

Xilinx strongly recommends that you read the HDL Synthesis andSimulation Design Guide before attempting to floorplan your HDLdesigns. This document explains HDL-specific design issues andunderstanding them will make floorplanning your HDL designseasier and more effective.

The design flows in this chapter present a general picture of wherethe Floorplanner fits in the Xilinx design flow; in some instances thedescriptions of the design flows are more relevant to designers usingschematic capture tools than to designers using HDL.

Place and Route, then FloorplanThe first design flow describes how to Floorplan your design afterplacing and routing your design. This is the preferred methodologybecause it allows you to view both the physical constraints for thedesign and the results of the automatic placement.

You enter your design using either a schematic capture tool or HDL.Next, run MAP and PAR to place and route the design in a target


Floorplanner Guide

FPGA device. To view and improve performance of the automaticimplementation, create a new Floorplan Netlist File within the Floor-planner from the placed and routed NCD file. Next, use the Floor-planner to constrain critical paths or adjust the automatic placement.Finally, run MAP and PAR with the newly generated MFP file toobtain the results of the floorplanned design. Refer to the design flowin the following figure.

Figure 2-1 PAR Before Floorplanning Design Flow

Schematic Capture

NGDBuild

Floorplanner

MAP -fp

PAR

HDL

MAP

X8761

netlist

design.ngd

map.ncd

PAR

design.ncd

design.fnf design.mfp

map.ncd design.pcf

design.ncd


Design Flow

Floorplanning Prior to Place and RouteThe second design flow is to floorplan your design before using PARto place and route it. In this flow, you enter your design using either aschematic capture tool or HDL. Run MAP on the design to create aphysical design file (NCD). Use the Floorplanner to define placementconstraints by manually placing selected logic into the resources ofthe target device. Next, run MAP and PAR to fit the design into thetarget FPGA using the Floorplan constraints. Refer to the design flowin the following figure.

Figure 2-2 Floorplan First Design Flow

Schematic Capture

NGDBuild

Floorplanner

MAP -fp

PAR

HDL

MAP

X8762

netlist

design.ngd

map.ncd


map.ncd design.pcf

design.ncd


Floorplanner Guide

Iterative FloorplanningIn the third design flow, iterative floorplanning, you enter the designusing a schematic capture tool or HDL. Next, use the Floorplanner toconstrain portions of the design. Then, run MAP and PAR to map,place, and route the design into the target FPGA.

Based on the results of the automatic place and route tools, you canmodify the currently floorplanned logic or select another portion ofthe design to constrain. Run MAP and PAR again with the new floor-planner constraints.

In addition, you can make small modifications to the placement doneby PAR. After copying the placement over to the Floorplan window,you can make small changes to the Floorplan and save the new fully-constrained FNF file. The Floorplan Constrain All FromPlacement command fully constrains the placement of the designand can be used to fix small performance problems, such as a fewdesign elements that are not optimally placed.

Repeat this Floorplanner-to-MAP and PAR loop until you haveachieved your performance goals for the design. Refer to the designflow in the following figure.

Note that the same NGD file is used throughout the design flow.


Design Flow

Figure 2-3 Iterative Floorplanning Design Flow

Incremental Design ChangesIn the fourth design flow, you make changes to the schematic of adesign that has been previously implemented in an FPGA, with orwithout floorplanning. You must re-implement the design into thetarget device while making only minimal changes to the previousimplementation. These changes could be one or more of thefollowing.

MAP -fp

PAR -w

map.ncd design.pcf

design.ncd

Schematic Capture

NGDBuild

Floorplanner

HDL

MAP

X8763

netlist

design.ngd

design.ngd

New Iteration

map.ncd

PAR

design.ncd


design.fnf

Floorplanner


Floorplanner Guide

Adding logic

Removing logic

Changing existing logic

If you used the Floorplanner to floorplan the original design, use theFloorplanner now to correlate the logic in that design with the newchanges, and adjust the constraints information accordingly. Next,use the Floorplanners output MFP file to constrain the design duringthe mapping and placement phases of the implementation.

For HDL users, incremental design change is more complex withHDL designs because the synthesis tools change symbol nameswhenever the compilation method changes. When applying aprevious revision of your Floorplan to the newly synthesized revi-sion, it may be necessary to constrain some or all of the previouslyfloorplanned elements.


Design Flow

Figure 2-4 Incremental Design Change Design Flow

Creating UCF Constraints from IOB PlacementIn the fifth design flow, you add constraints to the UCF file throughthe Floorplanner and iteratively implement your design to achieveoptimal placement.

Schematic Capture

NGDBuild

Floorplanner

Floorplanner

MAP -fp

PAR

HDL

MAP

X8764

netlist

design.ngd

NGDBuild

design.ngd

New Iteration

map.ncd

MAP

map.ncd

PAR

design.ncd

design.fnf

design.mfp

map.ncd design.pcf

design.ncd

design.fnf


Floorplanner Guide

To begin with, you need only the NGD file generated in a previousflow. In the Floorplanner, you manually make IOB assignmentswhich are automatically written into the UCF file. The Floorplanneredits the UCF file by adding the newly created placement constraints.The placement constraints you create in the Floorplanner take prece-dence over existing constraints in the UCF.

Next, go through the steps of implementing your design by runningNGDBuild, MAP, and PAR. The following flowchart illustrates howyou refine the UCF file through iterative runs.

Figure 2-5 Creating UCF Constraints for IOB Placement Flow

X9245

NGDBuild

design.edf

Floorplanner

design.ngddesign.ucf

NGDBuild (2)

design.ucf

PAR

MAP


Design Flow


Chapter 3

Getting Started

This chapter describes how to start and exit the Floorplanner. It alsoexplains the basic elements and operations of the Floorplannergraphical user interface (GUI).

This chapter contains the following sections.

Running the Floorplanner describes how to start the Floor-planner.

Design Manager Interface explains how to use the DesignManager to run the Floorplanner.

Command Line Interface shows the syntax to use whenrunning NGDBuild, MAP, and PAR in a command window aspart of the floorplanning process.

Floorplanner Interface describes the GUI.

The Floorplanner Windows describes the four sub-windowsinside the Floorplanner primary window.

Closing the Current Design describes how to close the currentdesign without exiting the Floorplanner.

Exiting the Floorplanner explains how to save your currentdesign and exit the Floorplanner.

Running the FloorplannerYou can run the Floorplanner on a PC running Windows NT or onan HP-based or Solaris-based workstation under Design Manager.You can input either an HDL-based design or a schematic-baseddesign.

The following figure shows the Design Manager screen from whichyou can launch the Floorplanner.


Getting Started

Figure 3-1 Design Manager Window

You can invoke the Floorplanner from the Design Manager in eitherof two ways.

Select the Tools Floorplanner command.

Click the Floorplanner toolbox button. In the above figure, this isthe third button from the top in the toolbar on the right.

Refer to the Design Manager/Flow Engine Guide for more detailsabout invoking the Floorplanner from the Design Manager.

Design Manager InterfaceWhen you use the Floorplanner, an MFP file is generated thatcontains mapping information. You can instruct the Design Managerto use this file as a guide for mapping an implementation revision.


Floorplanner Guide

To guide a design with Floorplan files, do the following steps. Formore information, refer to the Design Manager/Flow Engine Guide.

1. Select Design Set Floorplan File(s) from the DesignManager.

The Set Floorplan File(s) dialog box appears, as shown below.

Figure 3-2 Set Floorplan File(s) Dialog Box

2. Select the Copy Floorplan Data From option to copy a floorplanfile into the selected implementation revision. If the Enable Floor-plan option is selected, the software uses this file to implementthe design.

3. Deselect the Enable Floorplan option if you want to keep yourfloorplan intact, but do not want to guide your design in thisrevision. By default, the Enable Floorplan option is selected andthe software uses the specified floorplan file. Note that if youdeselect this option and implement your design, you areprompted to confirm that you want to implement without usinga floorplan file.

4. Select a Floorplan guide design from the Floorplan Design drop-down list.

Select an existing implementation revision.

Select None if you do not want to guide the design.

Select Custom to guide from any mapped file in your filesystem, including designs not generated from within theDesign Manager. This option invokes the Custom dialog box,shown in the following figure. You can specify an FNF file forthe Floorplanning File field and an MFP file for the Floor-planned Guide File field.


Getting Started

Figure 3-3 Custom Dialog Box (Floorplan Files)

5. The Flow Engine uses the selected file to guide the implementa-tion.

Command Line InterfaceAs shown in Figure 2-1 of the Design Flow chapter, the Floor-planner interacts with the core flow by first reading in an NCD filegenerated by MAP or PAR and an NGD file generated by NGDBuild.Next, it writes out a design.fnf file, which stores all the Floorplanninginformation, and a design.mfp file, which is used during MAP toapply the floorplanning constraints. Following is a sample of thecommand lines that would be used in a typical floorplanning session.

ngdbuild -p part_name design_name

map -p part_name -o map.ncd design_name .ngddesign_name .pcf

par map.ncd part_name .ncd part_name .pcf

Use File Newin the Floorplanner to create a floorplan and File Save to create design_name.fnf and design_name.mfp.

map fp design_name .mfp p part_name -o map.ncddesign_name .ngd design_name .pcf

Note The fp option above tells MAP to use the Floorplannerconstraints in the MFP file.

par map.ncd design_name .ncd design_name.pcf


Floorplanner Guide

Floorplanner InterfaceThe Floorplanner GUI consists of the primary Floorplanner windowand four sub-windows labelled Floorplan, Placement, Design Hier-archy, and Design Nets. The primary window also contains pull-down menus, dialog boxes, a toolbar, and a status bar.

The Floorplanner GUI uses pull-down menus that contain all of thenecessary commands to floorplan your design. The menus containmany commands that open dialog boxes, from which you can selectvarious options and parameters for that command. Other commandsact immediately on the selected logic.

Window operations, such as opening, closing, sizing, and moving areconsistent with the window environment of your particular platform.

ToolbarThe toolbar is a feature on the Floorplanner that gives you push-button access to many tasks. You can zoom in and out of the Floor-plan window and enable the display of resource graphics, labels, andratsnest lines. It also gives you pushbutton access to changing thedistribution direction for placing logic symbols.

You can use the toolbar buttons shown in the following figure insteadof the pull-down menus to perform some of the basic operations inthe Floorplan window. For a complete description of the toolbarbuttons, refer to the Floorplanner online help.

Note The toolbar also contains buttons for a number of standardsystem functions, such as opening a file and printing. These buttonsare not shown below.

Figure 3-4 Floorplanner Toolbar

Status BarThe status bar is at the bottom of the primary window. In this area,the Floorplanner displays various resource information. To the farright it displays current row and column coordinates when themouse pointer is in the Floorplan window.


Getting Started

The status bar also provides information about the toolbar buttons.When the toolbar is enabled and you move the mouse pointer over atoolbar button, the Floorplanner displays the name of that button andits function.

MouseThe mouse is integral to many operations. Use it to select and placelogic, access commands from the menus, and perform variouswindow operations. Selecting logic in the Floorplanner windows is adrag-and-drop operation using the mouse pointer. You select logicfrom the hierarchical design in the Design Hierarchy window byplacing the pointer over the symbol icon or hierarchical group nameand clicking the left mouse button. Then you drag the pointer to theFloorplan window (a ghost image of the selected logic moves withthe pointer) and release the mouse button to drop the logic at thepointers location in the window.

To make multiple logic selections in the Floorplanner, use the stan-dard windows procedures.

To make multiple consecutive selections, click the left mousebutton when the pointer is over the first selection. Then move thepointer to the last item, press and hold down the Shift key, andclick the left mouse button.

To make multiple nonconsecutive selections, click the left mousebutton when the pointer is over the first selection. Then holddown the Control (Ctrl) key and click the left mouse button overeach additional selection. Clicking on a selection that is alreadyhighlighted deselects that choice.

KeyboardThe Floorplanner uses the keyboard function keys that are mapped tospecific menu commands and Floorplanner functions for ease of use.The following table lists the keyboard shortcuts for the Floorplanner


Floorplanner Guide

and shows the related toolbar button, if any. You should exercise carewhen using the keyboard shortcuts.

Dialog BoxesThe Floorplanner has many commands that, when invoked, opendialog boxes that contain default settings for command execution.These types of commands have an ellipsis (...) after the commandname in the menu.

Table 3-1 Floorplanner Keyboard Shortcuts

Function Key Menu Command/Function Toolbar Button

F1 Help Help Topics NoneF2 View Options NoneF3 Hierarchy Group NoneF4 Edit Colors NoneF5 View Refresh NoneF6 View Zoom to Selected

F7 View Zoom In

F8 View Zoom Out

F9 View Zoom to Box

F10 Change focus to the menu bar None

F11 View Zoom Full View

Del Floorplan Remove NoneEsc Cancel current operation None


Getting Started

The dialog boxes are composed of the following elements.

Edit boxes, in which you can type information such as a differentpath name

List boxes, which list design information such as net names

Buttons, which allow you browse information and easily changethe way a command functions

The Using the Floorplanner chapter provides a detailed descriptionof the Floorplanner dialog boxes in the command descriptions.

The Floorplanner WindowsThe primary Floorplanner window contains four sub-windows:Design Hierarchy, Design Nets, Floorplan, and Placement. Descrip-tions of these windows follow.

Primary WindowWhen you invoke the Floorplanner, the primary window, shown inthe following figure, is the first window to display on your monitor.


Floorplanner Guide

Figure 3-5 Floorplanner Primary Window

To begin floorplanning, select File Newto create a Floorplan file.

When you load a Floorplan file using the File Newor File Open command, the Design Hierarchy, Design Nets, Floorplan, andPlacement windows are opened, as shown in the following figure.

Note The Placement window only appears if PAR was run on theNCD file used to create the Floorplan file (FNF).


Getting Started

Figure 3-6 Floorplanner Windows

Design Hierarchy WindowThe Floorplanner generates a hierarchical representation from theNGD and NCD input files. The Design Hierarchy window, shown inthe following figure, displays a fully expandable and annotated hier-archy. The header line indicates the name of the design that iscurrently loaded.


Floorplanner Guide

Figure 3-7 Design Hierarchy Window

Hierarchy Display

The Floorplanner uses colors in the hierarchy display to distinguishthe levels in the hierarchy, which are annotated with the instancename from the design file. Hierarchy structure lines are black linesthat traverse the colored areas and show the hierarchy of each hierar-chical group. Each hierarchical group has a gray box with a minussign, , or a plus sign, +. The indicates that the hierarchicalgroup is expanded to show the next lower level of hierarchy. The +indicates that the hierarchical group is collapsed, and that lowerlevels of hierarchy exist for that hierarchical group.

Selecting Logic

When you place the mouse pointer over a hierarchical group instancename or its logic symbol icon (in the Design Hierarchy window) andclick the left mouse button, you select that logic. The Floorplannerdisplays selected logic in the Design Hierarchy window in reversevideo. (If Flashing is enabled, the selected logic in the Floorplanwindow flashes.) When you select a hierarchical group, you alsoselect all the sub-hierarchy in that hierarchical group. When youselect logic at some lower level, the Floorplanner draws a rectangular


Getting Started

box around all associated higher levels of hierarchy. The followingfigure shows an example. The $7I586/REG hierarchical group is theselected logic, as indicated by the reverse video. The hierarchicalgroups hpmvsel and $7I586/REG are the higher-level associatedlogic, as indicated by the box around those hierarchical group names.

Figure 3-8 Selected Logic in the Design Hierarchy Window

Expanding and Collapsing Hierarchical Groups

Click the left mouse button on the Expand/Collapse button when itdisplays the + sign to expand a hierarchical group and display thenext level of hierarchy. The logic elements that comprise each hierar-chical group appear as an icon between the Expand/Collapse buttonand the instance name. The following figure shows a sample hier-archy.


Floorplanner Guide

Figure 3-9 Hierarchical Group Display in the Design HierarchyWindow

Hierarchical Group Annotation

Each hierarchical group in the design hierarchy contains the instancename and symbol counts and, optionally, the group or source name.The symbol count is the number of FPGA resources required toaccommodate that hierarchical group in the floorplan. Groups thatyou create with either the Group or Group By commands contain anon-hierarchical name and symbol count.

In the case of the XC4000 family, the FPGA resources are categorizedby type, such as FG (function generator), BUFTs (tristate buffers),DFFs (registers), IOBs (input/output pads), RAM/ROM, and relatedlogic. The following figure shows the important parts of a hierar-chical group.


Getting Started

Figure 3-10 Hierarchical Group Annotation

Symbol Annotation

The symbol line represents the lowest hierarchy of any hierarchicalgroup. It represents a single resource requirement of the design. Thesymbol line contains a logic icon, the symbol name, symbol type, andthe list of pin:net pairs. The following figure shows one of the symbolinstances of the expanded hierarchical group, XBL/AC4/SUM(shown in the above figure). It labels the important parts of thesymbol line.

Figure 3-11 Symbol Annotation

In this figure, the logic icon that is shown represents a single 4-inputfunction generator (FG) named $FG_XBL/AC4/S3; its outputconnects to net XBL/AC4/S3; its inputs connect to the nets IA3,XBL/AC4/SUM/C2, and XBL/Q43.

The symbol instance name is the corresponding symbol in the sourcenetlist. For function generators or CLBs, it is a name that the mapping


Floorplanner Guide

software (MAP) provides. For other symbols, it is the name in theschematic that either you or the schematic entry tool chooses.

The symbol type refers to the type of resource that the symbolrequires. Examples of symbol types are DFF (D-type flip-flop), IOB(Input/Output buffer), CLB (configurable logic block), FG (functiongenerator), and BUFT (tristate buffer).

Design Nets WindowThe Design Nets window lists the nets that connect the logic in thedesign. This window is shown in the following figure.

Figure 3-12 Design Nets Window

You can list either all nets in the design or just the nets that arecurrently displayed in the Floorplan window. To switch from one listto the other, click the right mouse button to bring up a menu and thenclick the List Visible Nets or List All Nets command inthat menu.

When only the visible nets are listed in the window, the heading ofthe window changes to Visible Nets.

Floorplan WindowThe Floorplan window displays the die for a selected part type, suchas XC4005EPC84. This window, shown in the following figure, is a


Getting Started

scrollable, scalable view of a resource map of the device that is speci-fied in the design.

Figure 3-13 Floorplan Window

You floorplan by dragging selected logic from the Design Hierarchywindow and dropping it into this window.

When a new Floorplan file (FNF) is created for a design and aprevious FNF does not exist, the Floorplan window displays anyphysical design constraints that are in the initial design netlist, theUCF file, or the NCF file. If a previous Floorplan file does exist and isspecified in the creation of the FNF file, the initial Floorplanconstraints are generated from the previous FNF file. All netlist, UCF,and NCF constraints are ignored, unless they exist in the previousFNF.


Floorplanner Guide

Resource Graphics

Each device family architecture has specific resources on the die. Youcan display these resources using the Resources panel of the View Options command. For example the resource graphics for theXC4000 family include I/O pads, function generators, registers,RAM/ROM, and BUFTs in the CLBs. With this feature, you controlthe view of the logic and available device resources. The fewerresources you display in the window, the faster the screen refreshes.

In the XC4000 family devices, flip-flops display as rectangles, func-tion generators as trapezoids, and BUFTs as triangles. The followingfigure shows an example of the resource graphics available in a quad-rant of the Floorplan window.

Note The global buffers have a pair of dedicated I/O pads that canalso connect to other logic. The lines in the floorplan die show whichI/O pad is dedicated to that buffer.

Figure 3-14 Resource Graphics for an XC4000 Device


Getting Started

Placement WindowThe Placement window displays the design after it has been placedand routed. This window is shown in the following figure. This is avery useful function to help evaluate the properties of an automati-cally generated placement.

Figure 3-15 Placement Window

The elements in the Placement Window cannot be moved or modifiedwithout loading in new placement information from a placed NCDfile using the File New or File Update commands. Totranslate placement information into Floorplan constraints, use theFloorplan Constrain From Placement or Floorplan Replace All With Placement commands.

Closing the Current DesignTo close the current design without exiting the Floorplanner, selectthe File Close command. If you have not made any changes tothe current design, the windows that contain the design close whilethe Floorplanner window remains open.


Floorplanner Guide

If you have made any changes to the design in the Floorplanner, adialog box prompts you to save those changes. Click the appropriatebutton.

If you click Yes , the Floorplanner writes out an FNF file that is asnapshot of the floorplanned logic and the Floorplanner environ-ment. In addition, the Floorplanner runs a utility to create anMFP file containing all physically constrained elements in theFNF file. The current design then closes.

If you click No, the current design closes without saving thechanges to the design.

If you click Cancel , the dialog box closes and you can continuewith the current floorplanning session.

Exiting the FloorplannerTo exit from the current floorplanning session, select File Exit .If you have not made any changes to the design, the Floorplannerwindow closes.

If you have floorplanned any logic, a dialog box displays andprompts you to save the changes to the current floorplan. Click theappropriate button.

If you click Yes , the Floorplanner writes out an FNF file that is asnapshot of the floorplanned logic and the Floorplanner environ-ment. In addition, the Floorplanner runs a utility to create anMFP file containing all physically constrained elements in theFNF file. The Floorplanner window closes.

If you click No, the Floorplanner window closes without savingthe changes to the current design.

If you click Cancel , the dialog box closes and you can continuewith the current floorplanning session.


Getting Started


Floorplanner Guide


Chapter 4


This chapter provides step-by-step instructions for performing theimportant floorplanning tasks.

These procedures are presented in sequential order; however, notevery task that can be performed is documented in this chapter.Floorplanning a design may require you to repeat some proceduresseveral times. Consult the design flows in the Design Flow chapterto aid your floorplanning efforts.

For information on starting and exiting the Floorplanner, see theGetting Started chapter.

This chapter contains the following sections.

Opening a File describes how to load a design file into theFloorplanner.

Saving a File explains how to save your floorplanned design.

Using Colors explains how to assign different colors to thehierarchical groups display.

Floorplanning Logic describes how to move logic symbolsfrom the Design Hierarchy window to the Floorplan window.

Floorplanning Designs that Contain RPMs explains how tofloorplan designs that contain Relationally Placed Macros(RPMs).

Creating Groups explains how to rearrange and regroup thedesign hierarchy.

Using Area Constraints describes how to create areaconstraints.

Using the UCF Flowdescribes how to use the UCF flow towrite constraints to a UCF.


Floorplanner Guide

Flattening and Building the Hierarchy describes how to flattenand rebuild the design hierarchy.

Walking Through the Design describes how to select successivelogic by connectivity rather than by name.

Analyzing PAR Placement describes how to analyze the place-ment results that PAR generates.

Analyzing PAR Placement for Timing Constraints describeshow to analyze the placement of floorplanned logic by PAR withrespect to Timing Constraints.

Finding Logic Connected to Nets explains how to find logicthat is connected to nets in the floorplanned design.

Displaying Resources and Logic describes how to display thelogic resources that are available on the FPGA.

Performing Detailed Manual Placement explains how tomanually place logic into the Floorplanner window.

Checking the Floorplan describes how to check the floor-planned logic for placement problems.

Aligning Symbols describes how to align symbols in the Floor-plan window to reduce unnecessary routing.

Working with Patterns describes how to work with patternswhen you place selected logic in the Floorplan window.

How to Interleave Buses describes how to interleave buses inthe Floorplan design.

Iterative Floorplanning explains how to floorplan your designiteratively.

Floorplanning Incremental Schematic Changes describes howto make incremental changes to a design that has been previouslyimplemented in an FPGA.

Making Small Modifications to Automatic Placement describeshow to make small changes to an automatically placed design inorder to fix packing or placement problems.

Lock Down I/Os from Automatically Placed Design describeshow to select the I/Os from an automatically placed and routeddesign and lock them down in the Floorplan window.



Getting Started With an Unfamiliar Design describes how tofamiliarize yourself with the connectivity of someone elsesdesign.

Opening a FileTo load a design file in the Floorplanner, follow these steps.

1. Select File New or File Open .

The File New command opens the New Floorplan dialogbox. You can choose either a standard or UCF flow. You enter thefilename of an appropriate NCD, NGD or FNF file.

The File Open command opens the Open File dialog boxwhere you specify which FNF or NGD file to load. In this dialogbox, you can also change directories if the desired file is in adirectory other than the current directory.

2. Browse until you find the desired design file in the list.

3. Double-click on the design file name, or enter the filename youwant. Click Okay or Open to load the file and open the floorplanwindow.

The Floorplanner reads the file, loads the correct device (parttype), opens the Design Hierarchy window with a hierarchicaldesign, and opens the Floorplan window with the correct FPGAdie.

Saving a FileTo save your floorplanned design, select File Save .

The Save command creates a file with the same name as the currentdesign and the extension .fnf. The information stored in this fileincludes the designs hierarchy organization, floorplanned logic, andnet, logic, and color assignments.

This file represents a snapshot of the current state of the floorplanthat you can use later.

In addition, whenever the FNF file is saved, the floorplanner auto-matically creates an MFP file. The MFP file contains all the physicalconstraints for the design that appear in the Floorplan window, and isused as an input to MAP.


Floorplanner Guide

Using ColorsThe Floorplanner automatically assigns unique colors to hierarchicalgroups when it reads a new design. Hierarchical nodes that have onelower level of hierarchy are set to the color of that lower level node.Hierarchical groups with more than one lower level of hierarchy, aswell as individual symbols, are not assigned colors. Individualsymbols without assigned colors inherit the color of the lowest levelof associated hierarchy.

You can change the colors of any hierarchical group using the Edit Colors command. If you assign a color to a symbol, that symbolis always shown in that color in both windows. If you assign a colorto a hierarchical group, the colorless symbols under that node willappear in that groups color.

Note You can remove color assignments using the Auto Assignbutton in the Colors dialog box.

The following sections describe using colors in the Design Hierarchywindow and in the Floorplan window. The last section describes howto use colors to distinguish between floorplanned logic and place androuted logic.

In the Design Hierarchy Window1. Select the hierarchical groups and symbols for which you want to

change colors.

2. Select Edit Colors .

This command opens the Edit Colors dialog box.

3. Click the button that displays the color you want to use.

4. Click Apply to change to the new color.

In the Floorplan Window1. Select the logic by dragging out an area around the desired logic

for which you want to change colors, or click the left mousebutton on an individual symbol.


This command opens the Edit Colors dialog box.



3. Click the button that displays the color you want to use.

4. Make sure the Apply to Symbols radio button is selected.

5. Click Apply to change to the new color.

Distinguishing LogicYou can use the Edit Colors command to distinguish placedand routed logic and floorplanned logic. You can change the color ofthe floorplanned logic to a color not used in the hierarchy. Then,when you view the placement window, the unique color distin-guishes the placed and routed logic from floorplanned logic in thedesign.

1. Select all the logic in the design.


3. Choose a new color for the selected logic from the palette in theEdit Colors dialog box.

Note When colors are automatically assigned, the first two andthe last two colors are not included. You can use one of thosecolors to make the logic distinguishable from the rest of thedesign.

4. Click Apply .

5. Select the floorplanned logic by dragging the mouse pointer overthe entire Floorplan window.

6. Choose a different color from the palette in the Edit Colors dialogbox for the selected floorplanned logic.

7. Click Apply .

8. If the NCD file that was used to create the Floorplanner filecontained placement information, selecting View Placementwill show the entire placed design, with the Floorplanned logic ina different color than the non-floorplanned logic.

Note You can use the Auto Assign button in the Edit Colors dialogbox to return to a normal display.


Floorplanner Guide

Floorplanning LogicThis procedure explains how to select, move, and manipulate logicsymbols from the Design Hierarchy window to the Floorplanwindow.

1. Select the desired logic from the Design Hierarchy window.There are two ways to do this.

Using the mouse, place the pointer on the logic group icon ofthe desired hierarchical group and click the left mousebutton.

Figure 4-1 Select an Icon Stack from the Design HierarchyWindow

Select Edit Find to find and select the desired logic. Inthe Find dialog box, you can type in the instance name,choose a specific type of logic, such as I/O Pads for IOBs,Flip-Flops for DFF, or type of connection.

Click Find .

If the search criteria that you applied is correct, an arrow willpoint to the applicable instance or hierarchical group in theDesign Hierarchy window.

2. Use the mouse and click on the found logic or hierarchical groupicon.

3. If you want to move an individual piece of logic, expand the hier-archical group and click on the desired logic icon.

The logic icons change to a ghost image as you move the mousepointer.

When moving more than one icon at a time, you must use one ofthe four directional arrow toolbar buttons to determine the distri-bution direction. The default direction is from top to bottom.



4. Move the mouse pointer from the Design Hierarchy window tothe desired location on the FPGA in the Floorplan window.

A ghost image of the selected logic icons showing the allocationdirection moves with the pointer.

Figure 4-2 Icons in Transit from the Design Hierarchy Window tothe Floorplan Window

5. At the desired location in the Floorplanner window, click the leftmouse button to place the logic. The Floorplanner places the logicaccording to the distribution direction you have chosen.

If you have Ratsnest turned on, you will see black lines indicatinglogic connectivity to the group you have just selected and placed.


Floorplanner Guide

Figure 4-3 Logic Icons Placed Using Distribute Mode; RatsnestTurned On

Floorplanning Designs that Contain RPMsThis procedure explains how to floorplan designs that contain Rela-tionally Placed Macros (RPMs). RPMs are optimized macros thathave the relative positions of the logic locked down. For this reason,you can only place RPMs as a whole unit into the Floorplan window.

You must have enough resources in the Floorplan window to accom-modate the entire RPM, because it must be placed in its entirety. Forexample, if an RPM is four CLBs in height and the largest vacancy inthe die is 3 CLBs high, the RPM will not fit.

Perform the following steps to place an RPM in the Floorplanwindow.

1. Select the desired RPM from the Design Hierarchy window.

2. Place the selected RPM into the Floorplan window in an area thatcan accommodate the entire RPM.

Note A good floorplanning practice is to floorplan both the RPM andthe logic it is driving in a specific set of locations.



RPM BindingThe Floorplanner now allows you to create an RPM graphically. Youcan select logic symbols and bind them into an RPM. You use thePattern Bind and Pattern Unbind commands to createand undo RPMs.

Note You cannot bind and unbind RPMs in a UCF flow.

Select the desired logic symbols from the Design Hierarchywindow.

Select Hierarchy Group to group the logic symbols.

Place the group by dragging the group elements to the Floorplanwindow. The logic remains stacked after you lay it out.

Select the Pattern Bind command to create the new RPM.

Note At this point, you can drag the newly created RPM from theFloorplan window to the Design Hierarchy window. When you runPAR, the RPM gets placed. If you leave the RPM in the Floorplanwindow, it is locked in place as seen in the Floorplan window. TheRPM remains bound unless you choose to unbind it.

To unbind an existing or new RPM, follow these steps.

Select the RPM you wish to unbind in the FloorPlan window.

Select the Pattern Unbind command to unbind the RPMinto individual logic symbols.

CautionUnbinding RPMs that contain carry logic is risky. You may deleteconstraints that MAP and PAR will later require to implementyour design.

Creating GroupsThe hierarchical representation of your design is a result of mappingyour original design; it might not be optimized for your floorplan-ning preferences. To make floorplanning easier, you can rearrangeand regroup the design hierarchy.

Note The function or connectivity of logic elements may be a reasonfor you to place them together as a group.


Floorplanner Guide

Manual GroupingTo create a group manually, follow these steps.

1. In the Design Hierarchy window, select the logic that you want togroup.

2. Select the first piece of logic with the left mouse button andsubsequent logic with the middle mouse button. Or, select subse-quent logic by holding down the control key and pressing the leftmouse button.

3. Select Hierarchy Group , or press the F3 key.

The Floorplanner creates a new group and assigns an arbitraryname to the group GRP0. The text line looks as follows.

GRP0 Grouped by: User [symbol count]

[symbol count] is the number of logic elements

The Floorplanner labels subsequent new user-created groupsGRP1, GRP2, and so on.

4. Use the Edit Properties command to give the new groupa better name.

The newly created group occupies a position in the lowest levelof hierarchy that is common to all logic that comprises the group.

The following figures illustrate how to create a new group in thedesign hierarchy.

The first figure shows the four D-type flip-flops that appear in reversevideo. These are the logic symbols that have been selected to form anew group.



Figure 4-4 Select Logic for Grouping

The next figure shows the new group. The new group is named GRP0(highlighted in reverse video). It is the first new group to be createdin the design. Note that the four flip-flops are no longer part of XBLand AC4, respectively, as indicated by the new symbol counts.


Floorplanner Guide

Figure 4-5 The Floorplanner Creates New Group

The Floorplanner places the new group in the hierarchy near thegroup XBL, the lowest level of hierarchy that is common to the fourflip-flops chosen for the group. When you expand the new group,you see that the four flip-flops are now in the new group.

The following figure shows the new group expanded. You can placethis new group as a unit on the floorplan die.



Figure 4-6 GRP0 Expanded to Show Logic Elements

Automatic GroupingIt is often more convenient to group logic by common type or signalnames. Creating such groups can make it easier to floorplan.

For example, you might want to make a group of all the BUFTs thathave a common output enable. In this case, do the following steps.

1. Select Edit Find .

This command opens the Find dialog box.

2. Select a BUFT in the Design Hierarchy window that contains theenable signal of interest by clicking the mouse on the appropriateline (on the BUFTs instance name).

3. In the Connections list box, select Common Enable (BUFTs, DFFs,IO).

4. Click Find .

5. Click Select Found .

The Floorplanner searches throughout the design hierarchy andhighlights each BUFT that meets the criteria you selected.

Note The Floorplanner automatically expands groups that havesubhierarchy that meet the find criteria.

6. Select Hierarchy Group , or press the F3 key.

The Floorplanner creates a new group and assigns an arbitraryname to the group GRP0 (if this is the first user-created group).The text line looks as follows.


Floorplanner Guide

GRP0 Grouped by: User [symbol count]

[symbol count] is the number of logic elements.

Note You can also use the Hierarchy Group By command tocreate these types of groups.

Using Area ConstraintsArea constraints are a way of restricting where PAR can place aparticular piece of logic. By reducing PARs search area for placinglogic, PARs performance may be improved.

To create an area constraint, do the following steps.

1. Select a hierarchical group in the Design Hierarchy window.

2. Select Floorplan Assign Area Constraint or click onthe toolbar button.

3. In the Floorplan window, use the mouse to drag out a rectangularbox where you want the area constraint to be located. The areaconstraint will cover all the tiles that are inside the drag box.

Area constraints may overlap each other. Select Floorplan Bring Area To Front or Floorplan Push Area To Backto move a selected area constraint in front of or behind another.

Using the UCF FlowYou can use the Floorplanner to create a User Constraints File (UCF).This feature allows you to floorplan at an earlier stage of the designprocess, before or just after design entry. The UCF flow causes theFloorplanner to write constraints to the UCF instead of producing anMFP file as output.

When using the UCF flow, remember the following points.

Avoid constraining your design in the source design schematic orHDL. The Floorplanner can add, remove, and edit constraints toan existing UCF, but cannot modify constraints elsewhere in thedesign source (including those in the NCF).

Do not attempt RPM binding. The UCF does not support RPMunbinding. Therefore, the Bind and Unbind commands in thePattern menu are disabled.



Remove any previously generated MFP files before imple-menting your design. If the design directory includes an MFP filefrom previous floorplanning (using the standard flow), theDesign Manger may detect it and invoke MAP to use the previ-ously generated MFP file. This causes any UCF constraints to beignored.

To start a UCF flow, follow these steps.

Select the File Newcommand to display the New Floorplandialog box.

Select UCF Flow instead of the default Standard Flow. The tworadio buttons, UCF Flow and Standard Flow are at the top of thedialog box.

Type an FNF or NGD filename. If you type an NCD filename,make sure you enter the filenames for either an FNF or NGD fileas well.

The Floorplan window opens with the label UCF Flow. Somemenu commands, such as Bind and Unbind are disabled for theUCF flow; others such as Change Device and Add Block inthe Edit menu apply specifically to the UCF flow.

To save a UCF Floorplan, follow these steps.

Select File Save or File Save As . The SaveConstraints As dialog box displays.

Click Okay to save the newly created or edited UCF in thecurrent directory.

Creating UCF Constraints for IOB PlacementThe Floorplanner now offers a graphical way to make and edit IO pinassignments in the UCF. When you write these constraints to a UCF,the Floorplanner applies them to the design along with any existingconstraints in the design source files.

To graphically create new UCF constraints for IOB placement, followthese steps.

Start a UCF Flow by selecting File New to display the NewFloorplan dialog box.

Note Alternatively, you can select File Use UCF Flow .


Floorplanner Guide

Select UCF Flow instead of the default Standard Flow. The tworadio buttons, UCF Flow and Standard Flow, are at the top of thedialog box.

Type an FNF or NGD filename. If you type and NCD filename,make sure you enter the filename for either an FNF or an NGDfile as well.

Note You can also type an NCD filename, but it is not required.

Select the desired IOB logic symbols in the Design Hierarchywindow and drag them to the Floorplan window.

Place the symbols along the periphery of the Floorplan window,thus creating IOB constraints.

Note The Floorplanner performs only minimal rule checkingwhile placing IOB symbols. It does not check to ensure that IOpins driving the global clock buffers are in the right locations.Refer to the device datasheets while deciding on pin locations.

Select File Write Constraints to write the newlycreated IOB constraints to the UCF.

Flattening and Building the HierarchyYou may have floorplanned the design and saved it. Then you realizethat you must make a change to the design at the schematic level thatdeletes some logic. When you read in the FNF file, the Floorplannerreads in the old hierarchy. Due to the changes made at the schematiclevel, the old hierarchy may represent divisions that are no longervalid.

How to Flatten the HierarchyYou must select a hierarchical node to enable the Flatten Groupscommand.

This procedure explains how to flatten the hierarchy in the DesignHierarchy window.

1. Select the part of the design hierarchy that you want to flatten.You can select just the level of hierarchy that contains the logicthat was changed in the schematic.

To flatten the entire hierarchy, select the top-level hierarchy.



2. Select Hierarchy Flatten Groups .

The Floorplanner removes all lower level hierarchy from theselected hierarchical node and moves all of the associatedsymbols up in the hierarchy.

How to Rebuild the HierarchyTo rebuild the hierarchy using symbol instance names, select Hier-archy Rebuild . The Floorplanner builds a hierarchy tree andplaces the selected logic symbols in their proper positions in that tree.

Note The Rebuild command works on all logic, not just selectedlogic.

Walking Through the DesignThis procedure explains how to select successive logic by connec-tivity rather than by name. This process helps you see which floor-planned logic elements drive other logic in the design.

Finding Logic1. Determine the logic that is of interest.



3. In the Connections list box, select either Loading Selected Logicor Driving Selected Logic.

4. Click Find .


The Floorplanner searches the design for the appropriatesymbols. The Floorplanner highlights the first found symbol inthe Design Hierarchy window with an arrowhead at the left ofthe symbol line text. Matching symbols in the Floorplan windowflash (blink) if you have enabled Flashing.

Finding Nets1. Determine the nets that you want to find.



Floorplanner Guide


3. In the Type list box, select Nets.

4. Use the Name dialog box, or Connections list box to find thedesired net(s).

5. Click Find .


For logic that is placed in the Floorplan or Placement windows,the Floorplanner searches the design and highlights the appro-priate nets by drawing them as red lines. Note that only currentlyselected nets appear in red; previously found nets, which weredeselected, are drawn with black lines.

Displaying the RatsnestThe Floorplanner shows connectivity between logic symbols in theFloorplan window with the aid of the ratsnest display. A ratsnest is adisplay of lines between logic blocks that indicate connectionsbetween the inputs and the outputs of floorplanned logic.

By default, the Floorplanner automatically displays ratsnest forselected floorplanned logic and selected nets. Whenever you placeselected logic in the Floorplan window, the ratsnest displays theconnectivity between the logic symbols.

Using the RatsnestBy default, the ratsnest is on. As you place selected logic in the Floor-plan window, the ratsnest lines show connectivity. You can see whichlogic is connected to a given net by selecting nets in the Ratsnestdialog box and choosing the appropriate connection.

1. Select some floorplanned logic. Use the mouse to draw an areaaround the desired logic or click on an individual piece of logic.

The Floorplanner draws the ratsnest to the associated logic.

2. In the Design Nets window, use the right mouse button to clickList Visible Nets . The names of the nets connected to theselected logic appear in the window.

3. Select a net in the Design Nets window and look at the Floorplanwindow.



The Floorplanner draws a ratsnest of the selected net in red.

Viewing Selected Nets in the RatsnestUse the Design Nets window to display specific nets in the Floorplanwindow. Click on a net in the Design Nets window. The Floorplannerwindow displays the net in red lines. To display consecutive nets inthe Design Nets window, hold down the Shift key while selecting thedesired nets. To display non-consecutive nets, hold down the Controlkey while making your selections.

Analyzing PAR PlacementThis procedure describes how to analyze the placement results thatPAR generates. You must first run PAR to generate an NCD file withplacement information.

1. Select File Update and read in the NCD and NGD files.

2. Select View Placement in order to display the Placementwindow.

Note If the Placement window is empty, this indicates that theNCD file used to generate the Floorplanner netlist did notcontain placement information. Make sure that you have runPAR and selected File Update , specifying the placed NCDfile.

3. Examine the Placement window for the following potential prob-lems.

BUFTs with common output enables that are not verticallyaligned or cross over longlines midpoints

RAM that is misaligned so as to prevent control signals frombeing routed on longlines

RPMs, BUFTs, and other groups source and load nets areclose together

Structured logic elements that cross longline splitters intoanother quadrant

Refer to the following figure. Note the positions of the darkcolored BUFTs on the left. The placement is inefficient becausetwo different longlines are required for the output enable signal.


Floorplanner Guide

These BUFTs are misaligned because they are in two columns,which require different longlines, and are split between twodifferent quadrants, crossing longline midpoints. Now, look atthe lightcolored BUFTs on the right. These BUFTs representproper alignment in the FPGA because the common outputenable signals connect to the same vertical longline.

Figure 4-7 BUFT Placement

The following figure illustrates flip-flop to BUFT alignment in theFPGA. The left half of the example shows ineffective placement;see how the ratsnest lines intersect. The right half of the exampleshows the proper alignment of the flip-flops and their associatedBUFTs as indicated by the parallel ratsnest.



Figure 4-8 Flip-flop/BUFT Alignment Example

Note For clarity, the flip-flops and BUFTs occupy two differenttiles. Normally, you would place this logic in the same tile tominimize the length of the ratsnest.

The following figure shows an example of groups placed so thatthe source and load nets are in proximity. In many cases, wherethere is sufficient routing resources, you want to place source andload nets close together.

Figure 4-9 Viewing Placed Logic Symbols Using the Ratsnest


Floorplanner Guide

Note In the example, the middle group is the selected logic fromwhich the ratsnest shows its source nets and load nets.

4. To see that PAR placed group symbols efficiently, select themfrom the Placement window or the Design Hierarchy window.

5. Step through the design, selecting critical groups, and using theRatsnest to view the distance between selected groups and theirsources and loads.

The Floorplanner highlights the selected symbols in the Place-ment window.

Analyzing PAR Placement for Timing ConstraintsThis procedure explains how to analyze the placement of floor-planned logic by PAR with respect to Timing Constraints. If you areusing the Design Manager, follow the instructions in that section.

You should analyze the logic placement in the following sequence.

1. Examine the PAR report for Timing Constraints that were notmet.

2. Use Timing Analyzer to find those Timing Constraints that werenot met.

3. Use the Floorplanner ratsnest to view the path.

4. If sub-optimal placement is causing the timing constraints to fail,floorplanning constraints can be used to improve the placementof logic to shorten time delays.

5. Rerun MAP and PAR with the new floorplanning constraints.

From the Design ManagerIf you are running the Floorplanner from the Design Manager, followthese steps to analyze the placement with regard to your TimingConstraints.

1. Select a routed implementation revision from the Project View.

2. Open up the Report Browser in one of two ways.

Select Utilities Report Browser .

Click the Report Browser toolbar button.



3. From the Report Browser, double-click on the Post Layout TimingReport icon.

4. Examine the report for any missed Timing Constraints.

5. If you find that there are missed Timing Constraints in yourdesign, click the Timing Analyzer toolbox button in theDesign Manager.

This step opens the Timing Analyzer window that displays thereport file.

6. Select Analyze Timing Constraints in the TimingAnalyzer window.

7. Select File Save in the Timing Analyzer window to savethe timing report.

Following is a portion of a sample TRCE report.

Data path myaddr21 to syn294866 contains 4 levels of logic:

Path starting from Comp: IOB.PADTo Delay type Delay(ns) Physical Resource

Logical Resource(s)-------------------------------------------- -------------------IOB.I1 Tpid 1.089R myaddr21

myaddr21my_addr21

CLB.G3 net (fanout=3) 2.984R my_addr21CLB.Y Tilo 1.190R N279

syn295958CLB.G4 net (fanout=4) 2.984R syn295958CLB.X Tiho 1.959R syn294869

syn323918syn294869

CLB.G1 net (fanout=2) 2.984R syn294869CLB.K Tihck 1.640R syn294866

syn323905my_next_statemy_current_state

-------------------------------------------------Total (5.878ns logic, 8.952ns route)14.830ns


Floorplanner Guide

Using Find and Ratsnest to Find Critical NetsWith the edited TRCE report, you can use the Floorplanner Findcommand to display the paths that need fixing.

1. Select Edit Find in the Floorplanner window.

2. In the Find dialog box, set the Type field to Nets. Turn Auto Gotoon and Auto Select off.

3. In the Find dialog box, type the name of the first net in the TRCEreport into the Name field. In the above example, the first net(identified by the first occurrence of the word net in the Delaytype column) is my_addr21.

4. Click Find in the Find dialog box.

5. In the Design Nets window an arrow appears next to the netspecified in the Find dialog box. Select this net. The net isdisp

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Floorplanner Introduction Guide Design Flow Getting ...homepages.cae.wisc.edu/~ece554/website/Xilinx/Floorplanner Guide … · Floorplanning Prerequisites ... features and capabilities