The Performance Degradation of Folded-Cascode CMOS Op-Amp due to Hot-Carrier Effects

Chong-Gun Yu, Hyun-Joong Kim, Woon-Dal Jeong and Jong-Tae Park Department of Electronics Engineering

University of Inchon 177, Tohwa-dong, Namgu, Inchon, Korea

Abstract - This study presents the first experimental data for the impact of CMOS hot- carrier degradation on the performance of folded- cascode op-amps. Two types of folded-cascode op-amps have been designed and fabricated using a 0.8pm double-metal CMOS process. After high voltage stress, the degradation of performance parameters such as open-loop voltage gain, offset voltage, unity-gain frequency and phase margin has been analyzed and physically explained in terms of hot-carrier degradation.

I. INTRODUCTION

Recently, the use of the submicrometer-level CMOS transistors for analog circuits requires the intensive study on the hot-carrier induced circuit performance degradation. It is known that the hot-carrier induced device degradation impacts on the performance of digital circuits and memory circuits such as CMOS logic circuits [ll, DRAM [21 and SRAM circuits [31. However, there have been a few efforts to study how much hot-carrier induced damage affects on analog circuit performance [41,[51. They have studied the performance degradation of CMOS subcircuits such as differential input stages [61 and current mirrors [71, and the drain output conductance degradation for analog circuit applications [SI. It has also been recognized that the performance degradation of analog circuits due to hot-carrier effects is sensitive to the circuit topology and operating conditions [61. Thus, the criteria for hot-carrier reliability should base on circuit and system performance requirements.

This study presents the first experimental data for the impact of hot-carrier induced device degradation on the performance of folded-cascode CMOS operational amplifiers. The hot-carrier degradation of the op-amp performance parameters such as open-loop voltage gain, offset voltage, unity-gain frequency and phase margin was measured and analyzed.

This work has been supported in part by Electronics and Telecommunications Research Institute.

11. DESIGN AND J~~EASUREMENT

Two types of folded-cascode op-amps have been designed and fabricated using a 0.8pm LOCOS -isolated, double-metal CMOS process with LDD stsuctures. As shown in Fig.1, the first type has an NMOS input stage which will be denoted as an N-type op-amp, and the second type has a PMOS input stage which will be denoted as a P-type op-amp. To reduce the systematic offset, the device sizes of output transistors were appropriately adjusted at the simulation stage, and the common centroid technique was used in doing layout of the input transistors to reduce the random offset. The device size of input transistors M1 and M2 is (W/L)i,2=226.4/0.8, and the sizes of output transistors M7 and M9 are (W/L)7=84/1.6 and (W/L)g=177.5/1.6 for the N-type op-amp, and (W/L)7=80/1.6 and (W/L)s=193/1.6 for the P-type op-amp.

Performance parameters such as open-loop voltage gain, offset voltage, unity-gain frequency and phase margin were measured before and after stress. The open-loop voltage gain (Av) was measured using the configuration shown in Fig2 and calculated using the following equation.

vout Ro 1 R 1 + R R1 z ) [ ( l + $ ) ~ - ~ '

where FL is the open-loop output resistance. The output resistance Ro is about 3.R\/IS for P-type op-amp and 2OMQ for the N-type op-amp before stress.

The input offset voltage (Voff) was measured using a resistor divider in the negative feedback path. The unity-gain frequency (UGF) was determined as a frequency at which the input voltage swing equals to the output voltage swing. Finally, the phase margin (PM) was determined by subtracting the phase difference between the input signal and the output signal from 180" at the unity-gain frequency. The measurement results for two types of folded-cascode op-amps before stress are shown in Table 1.

0-7803-3694-1 /97/$10.00 @ 1997 IEEE 164

To easily evaluate the impact of the hot carrier degradation on the circuit performance, high supply voltages were applied. Stress voltages for VDD and Vss were in the range of 5.6V-6.6V and -5.6V- -6.6V, respectively. The stress time was up to 210 minutes. For an open-loop stress condition, the positive input terminal was grounded, and a sinusoidal signal (f =lkHz, Vp-p=2V) was applied at the negative input terminal.

III. ANALYSIS OF PERFORMANCE DEGRADATION

For the open-loop stress condition, input transistor M1 and output transistors M7 and M9 for both cases are degraded more significantly compared to other transistors. Due to large voltage stress received by M7 of Fig.l(a) (M9 of Fig.l(b)) during the positive input swing and by M9 of Fig.l(a) (M7 of Fig.l(b)) during the negative input swing, the circuit performance will be degraded.

During the negative input swing, M9 of Fig.l(a) (M7 of F@.l(b)) is in the saturation region with low gate to source voltages, and M7 of Fig.l(a) (M9 of Fig.l(b)) is also in the saturation region during the positive input swing. When an NMOS is biased in the saturation region, as for most analog circuit purpose, acceptor-type interface states are mostly unoccupied because of the lowered electron quasi-fermi level near the drain [91. As a result, trapped hole charges lead to the increase of the transconductance (gm) and the drain output conductance (gd) [41. When a PMOS is biased in the saturation region, trapped electron charges lead to the increase of the transconductance and the decrease of drain output conductance 141.

Fig.3 shows the measured frequency responses of the open-loop voltage gain versus stress time. The gain of the N-type op-amp increases after stress, but the gain of the P-type op-amp decreases. The open-loop voltage gain of a single-stage folded- cascode op-amp is defined as the product of the transconductance o€ input transistors ( g d and the resistance at the output node ( R d .

&=gfmi Rout

In casc of the IY-type op-amp, the voltage gain shift is dominated by the degradation of the output PMOS transistor ld7. The hot-carrier variation of g d is usually much significant than that of gm. Since gd7 decreases dominantly after stress, the output resistance %,t and thus, the voltage gain Av increases as the stress time increases. The decrease of the voltage gain of the P-type op-amp can be explained by the dominant degradation of the output NMOS transistor M7. Because of the dominant increase of $37, the output resistance &,t

~

165

decreases, and thus, the open-loop gain decreases. There is a power law relation between the open-loop voltage gain variation and the stress time as shown in Fig.4. It can also be found that the voltage gain variation increases with stress voltage.

The hot-carrier induced offset voltage variation which is caused primarily by the degradation of the input transistor M1 is shown in Fig.5. It has been observed that the offset voltage of the P-type op-amp shifts in the positive direction with stress time while the offset voltage of the N-type op-amp shifts in the negative direction with stress time. Therefore, the magnitude of the offset voltages for both cases increases after all regardless of the polarity of the initial offset voltage. The significant degradation of the offset voltages could become the criteria for the determination of the circuit lifetime. From Fig.5, it is also found that the offset voltage variation increases with stress voltage.

The unity-gain frequency variation is shown Fig.6. In case of the N-type op-amp, the unity-gain frequency increases at the early sQge of stress but becomes almost saturated as the stress time is increased further. In case of the P-type op-amp, the unity-gain frequency decreases at the early stage of stress such that its variation increases as shown in Fig.6(b) but also becomes saturated as the stress time increases.

It has also been observed that the phase margin of the N-type op-amp decreases, but the phase margin of the P-type op-amp increases with stress time. Their variations versus stress time are shown in Fig.7. In case of the N-type op-amp, the open-loop voltage gain increases, while the dominant pole (-l/R,tCd decreases. However, the increase rate of Av IS greater than the decrease rate of R,t by the factor of g,,-,i. Therefore, the unity-gain frequency, which is approximately same as the product of the open-loop gain and the dominant pole, increases and thus, the phase margin decreases. In case of the P-type op-amp, the same comment as above can be made to explain the variation of the performance parameters.

IV. CONCLUSION

In this paper the performance variation of two types of CMOS folded-cascode op-amps due to hot-carrier effects has been measured and analyzed. It can be concluded from the reliability point of view that the degradation of the open-loop voltage gain and offset voltage determines the circuit lifetime in case of the folded-cascode op-amp with a PMOS input stage, and the offset voltage and phase margin can be the major factors determining the lifetime in case of the folded-cascode op-amp with an NMOS input stage.

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TABLE I hlEASuRED PERFORMANCE PARAMETERS OF THE OP-AMPS

Parameter N-type op-amp P-type op-amp Av(dB) 67.3 71.6

UGF(MHz) 3.1 2.5 PM(deg) 74 94 Voff(mV) 3.8 4.9

(b) Fig. 1. Circuit schematic of folded-cascode op-amps with (a) an

NMOS input stage (b) a PMOS input stage

R3 (520k) V, R, (520k)

&

voltage gain Fig. 2. Configuration for measuring the low-frequency open-loop

1 0" e IO- Stress Voltage

V &V = t 6 W A 30- T 60-

DD SS

Stress Voltage V &V =+6 .W DD SS

103 101 102 103 1[)1 105

(b) Frequency W )

Fig. 3. Open-loop response characteristics before and after stress (a) N-type op-amp (b) P-type op-amp

166

1 02

I"-

h . c E 10':

E . 4 .

100

."

8 E 101.

E i . .

a .

1001

v 4 v DD

+ 6.W

v &V

e----+-

. . . . ? . . . , . ....... . . . . . . -

. . I

103 lo"

1W 103 101 10s (b) :Stress time (sec.)

Fig. 4. Open-loop voltage gain variation measured at lkHz versus stress time (a) N-type op-amp (b) P-type op-amp

' I

100 102 103 101 105

(a) Stress time (sec.)

102,

h 8

G P 8 101

4

Fig. 5. Offset voltage vwiation versus stress time (a) N-type op-amp (b) P-type op-amp

roo4 103 104 105

(b) Stress time (sec.)

Fig. 6. Unity-gain frequency variation versus stress time (a) N-type op-amp (b) P-type op-amp

-------

6

Fig. 7. Phase margin variation (a) N-type op-amp (b) P-type OP-amP

167