References

[1] C. C. Hsu, F. C. Huang et al., “An 11b 800MS/s time-interleaved ADC with digital background calibration,” in 2007 IEEE ISSCC. Digest of Technical Papers, Feb 2007, pp. 464–615.

[2] B. Razavi, “Design considerations for interleaved ADCs,” IEEE Journal of Solid-State Circuits, vol. 48, no. 8, pp. 1806–1817, Aug 2013.

[3] H.Wei, P. Zhang et al., “An 8 bit 4 GS/s 120mW CMOS ADC,” IEEE Journal of Solid-State Circuits, vol. 49, no. 8, pp. 1751–1761, Aug 2014.

DESIGN OF A BACKGROUND MISMATCH CALIBRATION SCHEME FOR A 10-BIT 12 GS/s 16-CHANNEL TIME-INTERLEAVED ADC IN 28 nm FD-SOI PROCESS

Arda Uran, Mustafa Kılıç, Yusuf LeblebiciMicroelectronic Systems Laboratory (LSM)arda.uran@epfl.ch

More about this study

This study was completed by EPFL Master students as part of aSocial and Human Science course called How People Learn II. Wewould like to thank the EPFL survey platform inForm for theirsupport.

For further details, please contact roland.tormey@epfl.ch

ConclusionDigital processing capabilities of scaled technologies can beleveraged to compensate for the imperfections in the analogpart. It is possible to mitigate the causes and/or effects ofmismatch after fabrication using digital post-processing.

Linearity mismatch detection based on averaging is straight-forward, and correction is simple arithmetic in digital domain.Blind background timing mismatch detection is possiblewithout an extra channel, as long as the input signal satisfiescertain conditions. For higher number of channels, correctdetection gets more difficult as mismatch information getsweaker. Correction can be done via programmable delay lines.

Designing multi-phase clocked digital circuits creates timingproblems. A systematic approach eases the design procedure ofsuch circuits.

MotivationTime-interleaving is a widely used technique in high-speed ADCdesign. An important side effect of time-interleaving is inter-channel mismatch, which affects the output quality regardless ofthe quality of sub-ADCs. This work presents an implementationof a mismatch calibration scheme applied on a 10-bit 12 GS/s16-channel time-interleaved SAR ADC. The proposed scheme isdeveloped using and expanding the existing architectures. Itconsists of a digital calibration processor and a programmabledelay line.

ResultsThe designed calibration scheme is able to restore effectivenumber of bits (ENOB) from as low as 5 bits to 9 bits. Thefrequency response of the timing mismatch calibration hasnotches at 1/(kTs.). The processor dissipates 84 mW, and thedelay line draws 105 µW from a 1 V supply.

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MethodOffset mismatch calibrationMean of the output directly contains offset information.Choosing one channel as reference, mean difference givesoffset mismatch, which can be subtracted from channel outputs.

Gain mismatch calibrationAbsolute mean of the output indirectly contains gaininformation. Choosing one channel as reference, gain can becorrected iteratively until absolute means are equalized [1].

Timing mismatch calibrationCalibrating timing mismatch without interrupting the operation(background) and without explicit knowledge of the input (blind)has been demonstrated for 2 and 4 channels [2,3]. This workgeneralizes the architecture to N-channel TI-ADCs.The architecture depends on the cross-correlation of channeloutputs, which translates to the auto-correlation of the inputwith a lag of kTs. Difference of cross-correlations yields a valuedirectly proportional to the timing mismatch, provided that theinput and clock signals are asynchronous. The sampling clock istuned via a programmable delay line until the mismatch is zero.

ImplementationThe designed calibration scheme is integrated into a 16-channelSAR ADC and sent to be fabricated in Samsung 28 nm FD-SOIprocess. The calibration processor occupies an area of 250 µmby 550 µm. The programmable delay line occupies an area of 50µm by 100 µm.

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