Forced Frequency Resonant Flyback controller

Data Sheet Please read the Important Notice and Warnings at the end of this document Revision 2.0

www.infineon.com 2019-10-30

XDPS21071

Forced Frequency Resonant Flyback controller Based on FW: REV 1.0

Product Highlights • Integrated 600 V startup cell for fast startup and direct bus voltage sensing

• Multi-mode operation with forced frequency resonant mode (FFR)

• DCM operation guaranteed

• Adaptive current limitation for variable Vout

• Supports low no load input power to meet stringent regulatory standard

• One pin UART interface for configuration

Features • Multi-mode operation with BM, DCM

• Configurable ZVS enabled line voltage

• ZVS gate drive signal for forced resonant mode

• Built-in soft-start

• Built-in protection modes

• Brown-in and brownout detection via integrated HV

startup cell

• Pb-free lead plating; RoHS compliant

• Halogen-free according to IEC61249-2-21

Applications • High density adapter/charger

Product Validation • Qualified for industrial applications according to the

relevant tests of JEDEC47/20/22

Description

The XDPS21071 is a digital PWM controller for high density

adapter applications based on DCM flyback topology. A wide

feature set is provided in a DSO-12 package and requires

only a minimum of external components. An integrated

ASSP digital engine provides advanced algorithms for multi-

mode operation and protection features. A forced frequency

resonant operation support optimized high density adapter

system dimensioning. In addition a one-time-

programmable (OTP) unit is integrated to provide a

selective set of configurable parameters, which can be

matched to a dedicated system design.

Figure 1 Typical application

Marking Package FW Revision SP Ordering Code

XDPS21071 PG-DSO-12-20 REV 1.0 SP005355100

85 ... 264 VAC

GD0

MFIO

HV

GND

XDPS21071

VCC

GD1

ZCD

CS

GPIO

Data Sheet 2 Revision 2.0

2019-10-30

Forced Frequency Resonant Flyback controller

Table of contents

Description

Description Description

Description

Description

Table of contents

Based on FW: REV 1.0 ...................................................................................................................... 1

Product Highlights .......................................................................................................................... 1

Features 1

Applications ................................................................................................................................... 1

Product Validation .......................................................................................................................... 1

Description 1

Table of contents ............................................................................................................................ 2

1 Pin Configuration and Functionality ................................................................................ 4

2 Representative Block Diagram ........................................................................................ 5

3 Introduction .................................................................................................................. 6

4 Functional Description ................................................................................................... 7 4.1 Power supply management .................................................................................................................... 7 4.1.1 VCC capacitor charge-up and startup sequence ............................................................................... 7

4.1.2 Brown-in monitoring .......................................................................................................................... 8 4.1.3 Brown-out protection response ........................................................................................................ 9

4.1.4 During burst mode operation ........................................................................................................... 9 4.1.5 Bang-bang mode during latched and auto-restart operation ....................................................... 10

4.1.5.1 During latched operation............................................................................................................ 11

4.1.5.2 During auto-restart operation .................................................................................................... 11

4.2 Control features ..................................................................................................................................... 12 4.2.1 Reflected voltage sensing and Vcs offset calculation based on output voltage............................ 14

4.2.1.1 Output voltage sensing via ZCD pin ........................................................................................... 15

4.2.1.2 Ringing suppression time ........................................................................................................... 17

4.2.1.3 Vcs offset calculation based on output voltage sensed at ZCD pin .......................................... 17 4.2.2 Vbulk voltage measurement via HV startup cell ............................................................................. 18

4.2.3 Propagation delay compensation (PDC) ......................................................................................... 18 4.2.4 Soft-start ........................................................................................................................................... 20

4.2.5 Leading edge blanking (LEB) at CS pin ............................................................................................ 20 4.2.6 Spike blanking at CS pin for 2nd level over-current detection (OCP2) .......................................... 21

4.2.7 Gate driver output GD0 and GD1 ..................................................................................................... 21 4.2.8 Multi-mode operation ...................................................................................................................... 22

4.2.8.1 Frequency law setting for XDPS21071 ........................................................................................ 24 4.2.9 Frequency jittering ........................................................................................................................... 25 4.2.10 Burst mode operation ...................................................................................................................... 26

4.2.10.1 Burst mode entry ........................................................................................................................ 27 4.2.10.2 Burst operation ........................................................................................................................... 27

4.2.11 Burst mode exit ................................................................................................................................ 28 4.2.12 Forced frequency resonant (FFR) mode operation ......................................................................... 28 4.2.13 UART function at GPIO pin ............................................................................................................... 30 4.3 Protection features ............................................................................................................................... 30

4.3.1 Auto-Restart Mode (ARM) ................................................................................................................. 31

4.3.2 Latch Mode (LM) ............................................................................................................................... 31 4.3.3 VCC Under-Voltage lockout (UVOFF) ............................................................................................... 31 4.3.4 Brown-In Protection (BIP) ................................................................................................................ 31 4.3.5 Brown-Out Protection (BOP) ........................................................................................................... 32

4.3.6 Over-Current Protection level 1 (OCP1) .......................................................................................... 32


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Table of contents

4.3.7 Over-Current Protection level 2 (OCP2) .......................................................................................... 32

4.3.8 High input at CS pin (CShigh) .......................................................................................................... 32 4.3.9 MFIO pin high (MFIOH) ..................................................................................................................... 32 4.3.10 Internal over-temperature detection (IntOTP) ............................................................................... 32 4.3.11 Primary side output Over-Voltage Protection (VoutOVP) ............................................................... 33 4.3.12 Over load power protection ............................................................................................................. 33

4.3.13 CS pin short protection .................................................................................................................... 33

5 Configuration ............................................................................................................... 34 5.1 Overview of configurable parameters using .dp Vision ....................................................................... 34 5.2 Overview of configurable parameters and functions .......................................................................... 34

5.2.1 Configurable parameters and functions ......................................................................................... 34

6 Electrical Characteristics ............................................................................................... 36

6.1 Definitions ............................................................................................................................................. 36 6.2 Absolute Maximum Ratings .................................................................................................................. 36 6.3 Package Characteristics ........................................................................................................................ 37

6.4 Operating Range .................................................................................................................................... 38 6.5 Characteristics ....................................................................................................................................... 39

7 Package Information ..................................................................................................... 48

7.1 Outline dimensions ............................................................................................................................... 48

7.2 Footprint and packing ........................................................................................................................... 49

8 Marking ....................................................................................................................... 50

9 Appendix ..................................................................................................................... 51 9.1 Minimum required capacitive load at GD0 and GD1 pin ...................................................................... 51

10 References ................................................................................................................... 52

Revision history............................................................................................................................. 53


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Pin Configuration and Functionality

1 Pin Configuration and Functionality

The pin configuration is shown in Figure 2 and the functions are described in Table 1.

Figure 2 Pin Configuration of XDPS21071

Table 1 Pin Definitions and Functions

Symbol Pin Type Function

ZCD 1 I Zero Crossing Detection

ZCD pin is connected to an auxiliary winding for zero crossing detection and positive

pin voltage measurement.

MFIO 2 I Multi-Functional Input Output

MFIO pin is connected to an optocoupler that provides an amplified error signal for

the PWM mode operation.

GPIO 3 IO Digital General Purpose Input Output

GPIO pin provides an UART interface until brown-in. It is switched to weak pull down mode and disabled UART function during normal operation.

CS 4 I Current Sense

CS pin is connected via a resistor in series to an external shunt resistor and the source of the power MOSFET.

HV 5, 6, 7, 8 I High Voltage Input

HV pin is connected to the rectified bulk voltage. An internally connected 600 V HV startup-cell is used for initial VCC charge. Furthermore brown-in and

brownout detection is provided.

GD1 9 I FFR Signal Gate Driver Output

GD1 pin provides a gate driver pulse signal to initiate the forced frequency resonant mode operation.

GD0 10 O Gate Driver Output

Output for directly driving the main power MOSFET.

VCC 11 I Positive Voltage Supply IC power supply.

GND 12 O Power and Signal Ground

1

2

3

4

10

11

12

GD0

ZCD

VCC

GPIO

GND

PG-DSO-12-20

CS 9 GD1

MFIO

5

6

8 HVHV

HV 7 HV

XD

PS

210

71


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Representative Block Diagram

2 Representative Block Diagram Figure 3 shows a simplified top level block diagram of the IC functionality.

Figure 3 Representative Block Diagram of XDPS21071

Auto Restart

Mode

Latch

Mode

Protection

Modes

Frequency clamp

MFIO

RMFIOPU

VVDDP = 3.3 V

Vout OV

Protection

VZCDOVP = 2.75 V

Gate Driver

GD0PWM

Logic

GPIO

Overtemperature

DetectionTJOTP = 130 °C

GD1

BM Ctrl

Frequency Law

VMFIO

fSW

VMFIO

VCSPK

HV

HV Startup-cell

Closed/Open

VCC

D1

RM

QM

Vbulk Brown-in

Protection

VCC Brown-in

ProtectionVVCCBI = 9.1 V

UVLO

VVCCon = 20.5 V

Startup-Cell

Driver

HW Reset

Power

Management

Vbulk Brown-out

Protection

&

Soft-Start

ZCD1 k

Vout reflected Voltage

Measurement

UART

Communication

CS

OCP2

OCP1

Cycle by Cycle Peak Current Ctrl

2nd Level Overcurrent Detection

tCSLEB

tCSOCP2BL

1 k 10k 1 pF

VCSPK

VCSOCP2 = 0.8 V

C7VMFIOBMEN

C3VMFIOBMEX1

C5VMFIOBMWK

C6VMFIOBMPA

BM 2-point

Regulation

BM Exit

BM Entry

on-phase

off-phase

Auto Restart

Input Detection

FFR Mode

With ZVS Pulse

Generation

PDC

Burst Mode Function

XDPS21071

Bang-Bang Ctrl

VVCCBBoff = 20.5 V

VVCCBBonAR/LM = 9 V

C2VMFIOH = 2.41 V

Open Loop Timer

IGPIOLPU

VVDDP = 3.3 V

Vbulk

measurement

Parameter

Configuration

Gate Driver

tMFIOH = 31.3 ms

VVCCoffx = 7.2 V / 9.6 V

IHVBO = 0.443 mA

IHVBI = 1.15 mA

Vcs_offset


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Introduction

3 Introduction The XDPS21071 is a digital AC/DC current-mode controller for high density adapter applications. The IC provides a

configurable multi-mode operation controlled by the feedback signal from the secondary side control loop. The multi-mode

operation supports different operation modes like forced frequency resonant control (see chapter 4.2.12) or burst mode,

frequency reduction mode depending on line and load conditions. With supporting those modes high power density designs

can be dressed in a very flexible manner.

An embedded application specific digital core provides advanced algorithms for the multi-mode operation and a variety of

protection features. Special analog and mixed-signal peripherals are integrated to support the requirements for low stand-

by power.

The IC supports highest design flexibility in the application by means of an advanced set of configurable parameters and

state machines, which supports very dedicated system dimensioning. The configuration can be done via a single pin UART

interface at GPIO pin that supports in-circuit configuration. Chapter 5 contains the parameter default configuration setting

for XDPS21071 and the correlated specific firmware version. Furthermore, it provides a mapping table for the defined FW

symbols and the correlated data sheet parameters. Each listed parameter is specified in the electrical characteristics

Chapter 6.

The following functional description in Chapter 4 is based on the default parameter setting in the configuration Chapter 5.

Chapter 7.1 provides information about the package outline and dimensions.

An appendix Chapter 9 provides additional information about specific electrical characteristics or test conditions.

The reference Chapter 10 provides an overview about correlated documents.


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Functional Description

4 Functional Description The functional description gives an overview about the integrated functions and features and their relationship. The

mentioned parameters and equations are based on typical values at TA = 25 °C. The correlated minimal and maximal values

are shown in the electrical characteristics in Chapter 6.

The functional description is grouped in following sections:

Power supply management (Chapter 4.1)

Control features (Chapter 4.2)

Protection features (Chapter 4.3)

4.1 Power supply management

The power supply management ensures a reliable and robust IC operation. Depending on the operation mode of the control

IC, the power supply management unit runs in different ways for VCC supply and for brown-in monitoring, which are

described in the sequel:

• VCC capacitor charge-up and startup sequence (see Chapter 4.1.1)

• Brown-in monitoring (Chapter 4.1.2)

• Brown-out protection response (Chapter 4.1.3)

• During burst mode (QBM) operation (Chapter 4.1.4)

• Bang-bang mode during latch mode (LM) operation (Chapter 4.1.5.1 )

• Bang-bang mode during auto-restart mode (ARM) operation (Chapter 4.1.5.2)

4.1.1 VCC capacitor charge-up and startup sequence

There are two main functions supported at HV pin by a resistor RHV connected to the bulk capacitor (see Figure 5). They are

the VCC capacitor charge-up, and the bulk voltage monitoring (see Chapter 4.1.2).

At beginning of a cold startup, the depletion startup cell is on. Once the AC line voltage is applied and charging the bulk

capacitor, a current flows through the external resistor RHV into HV pin. Via the integrated diode D1, that current may charge

up the external VCC capacitor (see Figure 5). Once VCC voltage exceeds the threshold VVCCon = 20.5 V, the startup cell is turned

off, the control IC is enabled and the firmware boot sequence follows which takes about 1.2 ms. Both bulk voltage brown-in

and VCC brown-in condition (see Chapter 4.3.4) are checked continuously. Once they both are above the brown-in level,

respectively, the first GD0 pulse according to the soft-start control will be generated earliest after the 1.2 ms boot sequence

time. The voltage VVCC drops until the supply via the auxiliary winding (VVCCSS) takes over the VCC supply (see Figure 4). For a

proper system startup and operation, the supply voltage VVCC must be always above the VCC off-threshold VVCCoff=7.2 V (see

Chapter 4.3.3).


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Figure 4 Typical startup sequence

4.1.2 Brown-in monitoring

Once the IC is activated, brown-in monitoring is enabled for input brown-in protection (see Chapter 4.3.4) by measuring

the current at HV pin through the internal shunt resistor RM (see Chapter 4.2.2). If the input brown-in is not detected before

VCC falls below VVCCBI, the startup cell measurement unit remains enabled until VCC falls down to VVCCoff.

VVCC(t)

t

VVCCon = 20.5 V

VVCCoffOP = 7.2 VVVCCBI = 9.1 V

VHV(t)

VVCCSS

IVCC(t)

t

t

VVACpeak

Initial startup and normal operation

IVCCop1 = 7.5 mA

IVCCUVOFF = 30 µA

IVCCop

ca. 1.2ms internal boot sequence

VCC brown-in window

VCC self supply takes over

Start of GD0 switching

VAC brown-in condition fulfilled

TYPICAL STARTUP SEQUENCE


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Figure 5 High voltage brown-in sensing and VCC startup at HV pin

4.1.3 Brown-out protection response

In case of brown-out (see Chapter 4.3.5), the IC stops gate driver switching and stays active. At the same time, the VCC turn-

off threshold is switched over from VVCCoff to the threshold VVCCoffBO = 9.6 V. The threshold VVCCoffBO is higher than the threshold

VVCCoff, which supports an earlier system restart than using the threshold VVCCoff.

4.1.4 During burst mode operation

After the control IC enters quiet burst mode, the IC enters repeatedly a sleep mode, in which the IC current consumption is

reduced to IVCCquBM2 = 460 µA. Waking up from and entering this sleep mode (pause) is controlled by the feedback voltage at

MFIO pin VMFIO via the internal comparators C5 and C6 (see Figure 6 and Chapter 4.2.910).

RHV = 100kW

VAC = 85 ... 264

Vrms CBulk

VBULK

HV

RM

VCC

D1

QM

CVCC

Startup-Cell

DriverClosed/Open

HV Startup-

cell

Brown-in &

Brown-out

Protection

IHVBI = 1.15 mA

VCC Brown-in

ProtectionVVCCBI = 9.1 V

& PWM

Logic

UVLO

VVCCon = 20.5 V

VVCCoffx = 7.2 V / 9.6 VHW Reset

Power Supply

Management

IHVBO = 0.442mA


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Figure 6 Burst mode control

For the system dimensioning, it should be ensured that the voltage VVCC should be always well above the threshold VVCCoff, including the burst-off phase. Figure 7 shows a typical burst mode operation signal for VCC and

correlated current consumption.

Figure 7 Burst operation

4.1.5 Bang-bang mode during latched and auto-restart operation

The bang-bang mode supports an IC operation without external VCC supply during the latched and auto-restart operation.

It directly controls the HV startup cell depending on the set bang-bang mode turn-on threshold VVCCBBon of the corresponding

auto-restart and latch mode (see Figure 8). In latch mode, the HV startup cell switch-on threshold is set to VVCCBBon = 9 V (see

Chapter 4.1.5.1 and Chapter 4.1.5.2). In auto-restart mode, there is also an additional stand-by timer active that switches on

the HV startup cell in a fixed time period of 500ms scheme to keep the VCC all the time at a high level above the brown-in

threshold VVCCBI = 9.1 V. Then a restart can take place without going through an additional VCC brown-in cycle. Due to the low

current consumption during the auto-restart break time, the startup cell is always turned on by the 500 ms timer.

Figure 8 Bang-bang mode control of HV startup-cell

Power

ManagementBM Ctrl

C5VMFIOBMWK

C6VMFIOBMPA

BM 2-point

Regulation

burst-on

burst-off

MFIO

VVCC(t)

t

VVCCoff = 7.2 V

VMFIO(t)

VVCCSS

IVCC(t)

t

t

VMFIOBMWK = 1.6 V

VMFIOBMPA

IVCCop

IVCCquBM2 = 460 µA

burst-off phase

VGD0(t)

t

burst-on phase

Auto Restart

Mode

Latch

Mode

Protection ModesHV

HV Startup-cell

Closed/Open

VCC

D1

Bang-Bang CtrlVVCCBBoff = 20.5 V

VVCCBBonAR/LM = 9 V

Startup-Cell

Driver

Power

Management


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4.1.5.1 During latched operation

If latch mode is entered (see Chapter 4.3.2), the IC stops gate switching and the VCC current consumption is reduced to

IVCCquLM = 150 µA. The enabled bang-bang mode ensures that the IC is kept alive by keeping the voltage at VCC pin above the

threshold VVCCoff = 7.2 V (see Figure 9). A reset of the latch mode takes place only after the VCC drops below the VVCCoff threshold.

Figure 9 Latch mode operation

4.1.5.2 During auto-restart operation

Once auto-restart mode is entered (see Chapter 4.3.1), the IC stops GD0 switching, the VCC current consumption is reduced

to IVCCquAR = 160 µA, and a stand-by timer with 500 ms (tBBoffAR) period is activated which turns on the HV startup cell

periodically, to charge up the VCC capacitor. Once the voltage at VCC pin exceeds the switch-off threshold VVCCBBoff = 20.5 V,

the startup cell is turned off (see Figure 10). This is bang-bang mode operation for the VCC management during the auto-

restart break time. In this way, the VCC voltage is kept at a level well above the VCC brown-in threshold to ensure enough

energy stored in the VCC capacitor for the coming restart of the system, that is initiated after the auto-restart break time

tAR = 3 s. Then after an additional time ∆t = ε, the gate driver switching is activated with a soft-start sequence. Here the

additional time ε depends on the VCC capacitor charge-up time which is related to the VCC capacitance and the voltage at

HV pin.

VVCC(t)

t

VVCCBBoff = 20.5 V

VVCCoff = 7.2 V

VHV(t)

VVCCSS

IVCC(t)t

t

VVACpeak

VVCCBBonLM = 9 V

Latch mode operation

IVCCUVOFF = 30 µA

IVCCop

IVCCquLM = 150 µA

Reset of latch mode due to low VAC


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Figure 10 Auto-restart mode operation

4.2 Control features

The XDPS21071 provides peak current control assisted by the features listed in Table 2. A simplified block diagram

representing the controller features is shown in Figure 11.

Auto-restart mode operationVVCC(t)

t

VVCCBBoff = 20.5 V

VVCCBBonAR = 9 VVVCCBI = 9.1 V

VHV(t)

VVCCSS

t

VVACpeak

IVCC(t)

t

IVCCop1 = 7.5 mAIVCCop

IVCCquAR = 160 µA

VVCCoff = 7.2 V

tBBoffAR = 500 ms

tAR = 3sVGD0(t)

t

VGD0H = 10.5 V

Dt = e


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Figure 11 Block Diagram of PWM Control

Table 2 gives an overview about the controller features that are described in the mentioned chapters.

Table 2 Controller Features

Reflected voltage sensing and zero crossing detection at auxiliary winding Chapter 4.2.1

Vbulk voltage measurement via HV startup cell Chapter 4.2.2

Propagation delay compensation (PDC) Chapter 4.2.3

Soft-start Chapter 4.2.4

Leading edge blanking (LEB) time at CS pin Chapter 4.2.5

Spike blanking at CS pin for 2nd level over-current detection Chapter 4.2.6

Gate driver output GD0 and GD1 Chapter 4.2.7

Multi-mode operation Chapter 4.2.8

Burst mode (QBM) operation Chapter 4.2.9

Forced frequency resonant (FFR) mode operation Chapter 4.2.12

UART function at GPIO pin Chapter 4.2.13

Multi-Mode

Controlfrequency law,

burst mode controlVMFIO

fSW

MFIO

ZCD

VVDDP

IHV

Vout

Measurement

+

CSVCS

Soft-Start

ControlVCSSS

Start Request

Generator

+

VCSOCP2

tCSOCP2BL

FF

CLEAR

&

SET

GD0

M

I

N

Propagation

Delay

Compensation

start GD0

MULTIMODE_OVERVIEW_DIGITAL

VCSOCP1

&

tZCDRS

Cold Start,

BM Wake-Up,

Autorestart

VBulk

Measurment

HV

ZCD

FFR ZVS

PWM

Generator

GD1

Vcs_offset

&

FF

SET

CLEAR

stop GD0

tCSLEB


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4.2.1 Reflected voltage sensing and Vcs offset calculation based on

output voltage

The IC provides output voltage detection by means of measuring the reflected voltage at the auxiliary winding VAux at the

primary side of the transformer via ZCD pin and an external resistive voltage divider. The voltage signal VAux contains the

information of the flyback output voltage, VOut, at the secondary side.

The ZCD pin related circuit is shown in Figure 12. Figure 13 shows a typical voltage waveform of the drain voltage VDrain and

the related auxiliary winding voltage VAux. The sensed output voltage is used for over-voltage protection (see Chapter 4.3.11).

Following topics are described in the sequel:

• Output voltage sensing via ZCD pin (Chapter 4.2.1.1)

• Vcs offset with sensed Vo at ZCD pin (Chapter 4.2.1.3)

Figure 12 Functionality at ZCD pin

ZCD

GND

iZCD

RZCDH

RZCDL vZCD

vAux

vPri vSec

VOLTAGE_SENSING_OVERVIEW

VBulk

VOut

vZVS

vDrain


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Figure 13 Auxiliary voltage and magnetization current waveforms for standard discontinuous

conduction mode operation

4.2.1.1 Output voltage sensing via ZCD pin

Output voltage is sensed at a fixed point of time during the free-wheeling phase. The free-wheeling phase begins when the

gate driver is switched off and ends when the secondary side demagnetization current becomes zero. During free-wheeling

phase the VCC capacitor of the IC, the output stage and the additional ZVS capacitor at ZVS winding for introducing a forced

resonant cycle (see Chapter 4.2.12) are supplied. As soon as VCC capacitor is charged, the auxiliary voltage is a function of

secondary side voltage.

𝑽𝑨𝑼𝑿 =𝑵𝑨𝑼𝑿

𝑵𝑺𝒆𝒄∙ 𝑽𝑺𝒆𝒄 ( 1 )

Figure 14 shows the schematic related to secondary side voltage sensing and the equivalent network.

vDrain(t)

vAux(t)

0

VBulk

NPri / NSec × vSec

NAux / NSec × vSec

NAux / NPri × VBulk

tOn tf tOsc

14

14

14

14

VOLTAGE_SENSING_SIGNALS

t

t

Free-wheeling phase Oscillation phase

0

tOffiMag(t)

t


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Figure 14 Secondary Side Voltage Sensing

No current clamping applies during the free-wheeling time and the voltage at ZCD pin is given by

𝑽𝒁𝑪𝑫𝑺𝑬𝑪(𝑽𝑺𝒆𝒄) = 𝑹𝒁𝑪𝑫∙(𝑽𝑨𝑼𝑿

𝑹𝒁𝑪𝑫𝑯) ( 2 )

RZCD is the internal resistance of VZCDSEC (VSec) and is the equivalent parallel resistance of RZCDH and RZCDL. The related waveforms

are presented in Figure 15. After the primary side gate driver is turned off, the auxiliary voltage goes from its negative level

to positive. After a ringing phase, the positive level is given by the output voltage plus the secondary side diode voltage drop.

During the free-wheeling phase the secondary side diode operates in the linear region until the demagnetization current

becomes very small. This linear relationship can be described as a resistor RDSonSec, resulting in a falling slope according to

RDSonSec·iLSec(t). The secondary side current iLSec(t) decreases with a slope given by the output voltage and the transformer

secondary side inductance. Hence the resulting auxiliary winding voltage is more or less constant until the secondary side

current becomes zero. The reflected voltage at auxiliary winding is sampled at the end of the ringing suppression time (see

Chapter 4.2.1.2). The measured voltage VZCDSEC includes the output voltage level and a superimposed offset ∆VZCDOFFSET that is

depending on the secondary side chosen rectification approach and the associated component dimensioning.

To ensure an accurate measurement of the reflected output voltage, the system dimensioning must provide a free-wheeling

phase that only finishes after the ringing suppression time tZCDRS.

Furthermore following effects can influence the output voltage sensing if not properly considered in system dimensioning:

• VCC and ZVS capacitor charging

• Voltage drop on secondary side at the free-wheeling diode or the secondary side switch

The VCC and ZVS capacitors need to be charged up before the ringing suppression time tZCDRS ends. The superimposed

voltage offset ∆VZCDOFFSET at sample time point due to secondary side rectification approach needs to be considered either by

the dimensioning of the ZCD resistor divider or the internal overvoltage threshold setting VZCDOVP (see Chapter 4.3.11).

ZCD

GND

iZCD=0

vZCD>0

vSec(t)

NSec:NAux

RZCDH

RZCDL

ZCD

GND

vZCDSEC(vSec)+

VOLTAGE_SENSING_ZCDSH

vAux(t)


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Figure 15 Output Voltage Sensing Signals

4.2.1.2 Ringing suppression time

To prevent erroneous ZCD events due to primary side gate driver turn off ringing, a ringing suppression time tZCDRS = 1.9µs

applies for the zero-crossing events. During this time no zero-crossing is considered.

4.2.1.3 Vcs offset calculation based on output voltage sensed at ZCD pin

To limit the output current at different output voltage, a linear scaled Vcs offset is inserted to the peak current command.

This offset will be minused from the current command mapping from the frequency law curve.

It is an inverse of the output voltage based on positive ZCD winding voltage. Figure 16 shows when the Vzcd is at

Vzcd_zero_point, the Vcs offset is zero. While Vzcd voltage is at minimum level, the Vcs offset is maximum. The Vcs offset level

depends on the slew rate of Kvcs_offset and the starting point of Vzcd. The equation is as below:

𝑽𝒄𝒔𝒐𝒇𝒇𝒔𝒆𝒕 = 𝑲𝒗𝒄𝒔𝒐𝒇𝒇𝒔𝒆𝒕 ∗ (𝑽𝒛𝒄𝒅 − 𝑽𝒛𝒄𝒅_𝒛𝒆𝒓𝒐_𝒑𝒐𝒊𝒏𝒕)/𝟔𝟓𝟓𝟑𝟔 ( 3 )

All the number in above equation is decimal digital value.

At ZCD pin, the sensed voltage will minus 1.2V offset first, then feed into an ADC channel to get the sense the voltage. Also

due to the ADC input voltage range is 1.2-2.8V, so any ZCD voltage out of this range is ignored by the IC and ADC converter

value will be saturated at its min(0) and max value(255).

Below is the example on how to set the value,

Vzcd_zero_point is the voltage level without compensation, here we choose Vzcd=1.41V, the digital value of Vzcd_zero_point_dig=(1.41-

1.2)*1.5/2.4*255=148, Kvcsoffset=28000, for Vzcd=1.2V, the digital value of it will be

Vzcd_dig=(1.2-1.2)*1.5/2.4*256=0, so Vcsoffset_dig=28000*(0-79)/65536=34, its analog value will be 34/255*0.6=80mV.

If system parameters like transformer turns ratio, ZCD pin voltage divider is known, then the corresponding output voltage

can be calculated. E.g. Naux=2, Nsec=2, RzcdH is 39kohm, RzcdL is 5.6kohm.

𝑽𝒐 = 𝑽𝒛𝒄𝒅 ∗𝑵𝒔𝒆𝒄

𝑵𝒂𝒖𝒙∗ (𝑹𝒛𝒄𝒅𝑳 + 𝑹𝒛𝒄𝒅𝑯)/𝑹𝒛𝒄𝒅𝑳 ( 4 )

vZCD(t)

VZCDSEC(VSec)

tf tOsc/4

VOLTAGE_SENSING_SIGNALS_ZCDSH

t

vGD0(t)

t

VZCDclp

VZCDTHR

tZCDRS

Ringing suppression

tGD0offZC

DVZCDOFFSET

VZCDVO(VOut)

Voltage sampling


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So for Vzcd=1.41V, Vo will be 1.41*2/2*(39+5.6)/5.6=11.23V assuming transformer coupling is 1.

For Vzcd=1.2V, Vo will be 1.2*2/2*(39+5.6)/5.6=9.56V.

This means that when output voltage is above 11.23V, there is no Vcs offset compensation, below 9.56V the compensation

is clamped at 80mV as calculated above.

Figure 16 Vcs_offset calculation

4.2.2 Vbulk voltage measurement via HV startup cell

The VBulk voltage is measured via the HV pin that is connected at the bulk capacitor node. The current IHV is sampled in the IC

and processed for the following functions:

• Brown-in protection ( Chapter 4.3.4)

• Brown-out protection (Chapter 4.3.5),

• Propagation delay compensation (Chapter 4.2.3),

In all these functions, the current IHV represents the bulk voltage.

4.2.3 Propagation delay compensation (PDC)

Due to the gate driver turn-off propagation delay tPD, the level VCSOCP1 set by the OCP1 comparator will not directly control

the inductor peak current, ILPk.

Without propagation delay, the peak current would be given by ILPk = RCS-1·VCSOCP1. However, due to the propagation delay,

the OCP1 level is exceeded by

𝑹𝑪𝑺 ∙ 𝑰𝑳𝒑𝒌 = 𝑽𝑪𝑺𝑶𝑪𝑷𝟏 + 𝑽𝑪𝑺𝑷𝑫(𝑽𝑩𝒖𝒍𝒌) ( 5 )

where the propagation delay overshoot VCSPD(VBulk) is

𝑽𝑪𝑺𝑷𝑫(𝑽𝑩𝒖𝒍𝒌) =𝑹𝑪𝑺

𝑳𝑷𝒓𝒊∙ 𝒕𝑷𝑫 ∙ 𝑽𝑩𝒖𝒍𝒌 ( 6 )

In Figure 17 related example waveforms are presented.

VCSOF F SET

Vzcd

Vcs offsetVcs_offset

Vzcd_LowV

Vzcd_zero_point

Kvcs_offset


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Figure 17 Propagation Delay and Propagation Delay Compensation

On the left side, the bulk voltage is low, the slope of inductor current and of the CS voltage are low, too. When the CS voltage

reaches the OCP1 level, the gate driver turns off and the inductor current reaches its peak after the turn off propagation

delay tPD. The turn off propagation delay tPD includes the delay tCS of the filter capacitor connected to CS pin and the resistor

connected between shunt resistor and CS pin (see Typical Application Figure). The overshoot of the inductor current due to

propagation delay is small due to the small slope 𝒅𝑽𝑪𝑺

𝒅𝒕=

𝑹𝑪𝑺∙𝑽𝑩𝒖𝒍𝒌

𝑳𝒑 ( 7 )

The right side of Figure 17 shows the same operating waveforms for a higher bulk voltage. In this case, the OCP1 comparator

limit needs to be less than on the left side to reach the same inductor peak current. Although the propagation delay remains

the same, the slope as well as the overshoot due to propagation delay is larger.

The XDPS21071 controller is defined to measure the HV current IHV representing the bulk voltage VBulk. The OCP1 comparator

limit is adjusted depending on the measured bulk voltage so that the real peak current due to the propagation delay is

compensated. For this HV pin needs to be connected to VBulk.

Consequently, any CS peak parameter VCSx is specified in the electrical characteristics (Chapter 6.5) for a low-line use case

(VCSxLL) and for a high-line use case (VCSxHL).

Low-Line Use Case (LL)

• IHVLL = 70 µA as for VBulk = 72 V, RHV = 100 kΩ

• (dvCS /dt)LL = 96 mV/µs as for VBulk = 72 V, LPri = 220 µH, RCS = 0.294 Ω

High-Line Use Case (HL)

• IHVHL = 370 µA as for VBulk = 372 V, RHV = 100 kΩ

• (dvCS /dt)HL = 497 mV/µs as for VBulk = 372 V, LPri = 220 µH, RCS = 0.294 Ω

These use cases set the corners of the propagation delay compensation which operates in a linear manner so that the typical

OCP1 threshold for any IHV is given by

𝑽𝑪𝑺𝒙(𝑰𝑯𝑽)−𝑽𝑪𝑺𝒙𝑳𝑳

𝑰𝑯𝑽−𝑰𝑯𝑽𝑳𝑳=

𝑽𝑪𝑺𝒙𝑯𝑳−𝑽𝑪𝑺𝒙𝑳𝑳

𝑰𝑯𝑽𝑯𝑳−𝑰𝑯𝑽𝑳𝑳 ( 8 )

MULTIMODE_PDC

vGD0(t)

vDrain(t)

vCS(t)

t

t

t

RC

SILp

k

VC

SOC

P1

dvCS/dt

VBulkLL

RCSILpk(t)

vGD0(t)

vDrain(t)

vCS(t)

t

t

t

VC

SOC

P1

dvCS/dt

VBulkHL

RCSILpk(t)

tPD tPD

tCS

tCS


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4.2.4 Soft-start

The IC control provides a soft-start during initial startup and auto-restart cycles. The soft-start slew rate is defined by the

step ∆VCSS = 2.5 mV taking place every time step of tBase1 = 52.14 µs. Furthermore, the peak current start level is determined

by the parameter VCSSS.

The soft-start phase is latest finished after VCS has ramped up to the maximum level of VCSmax (see Figure 18).

The total soft-start time tSSmax is therefore based on the following equation:

𝒕𝑺𝑺𝒎𝒂𝒙 = 𝒕𝑩𝒂𝒔𝒆𝟏 ∙𝑽𝑪𝑺𝒎𝒂𝒙−𝑽𝑪𝑺𝑺𝑺

∆𝑽𝑪𝑺𝑺 ( 9 )

The associated ramped up peak current limitation is determined by internal digital numbers, which are not depending on

the propagation delay during peak current limitation process.

Figure 18 Soft-start timing

The internal soft-start phase is finished once the voltage level at MFIO pin is getting lower than 2.42 V. Then the setting for

CS limitation is determined by the feedback signal at MFIO pin via the frequency law (see Chapter 4.2.8.1).

4.2.5 Leading edge blanking (LEB) at CS pin

A digital leading edge blanking filter with tCSLEB = 269 ns (see Chapter 5) is integrated in the OCP1 peak current control path

to prevent the current limitation process from distortions, caused by the leading edge spike at the switch-on of the power

MOSFET (see Figure 19). The LEB applies only for the OCP1 comparator (see Figure 3) that is used for cycle-by-cycle peak

current limitation. The LEB needs also to ensure a monotonous peak current control without being impacted by ringing

taking place directly after the leading edge spike.

Figure 19 Leading edge blanking

t

VCS(t)

VCSmax

tSSmax

VCSSS

tBase1

DVCSS

t

VCS(t)

VCSOCP1

VGD0(t)

tCSLEB

t


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4.2.6 Spike blanking at CS pin for 2nd level over-current detection

(OCP2)

A further comparator OCP2 is implemented at CS pin (see Figure 3) to detect dangerous current levels (see Chapter 5), which

could occur if one or more transformer windings are shorted or if the secondary side diode is shorted. To avoid an accidental

trigger by exceeding this 2nd level over-current protection threshold VCSOCP2 = 0.8 V, a spike blanking time tCSOCP2BL = 616.2 ns

(see Chapter 5) is implemented in the output path of the OCP2 comparator.

4.2.7 Gate driver output GD0 and GD1

The gate driver GD0 and GD1 are of the same type. The GD0 is used for controlling the main MOSFET connected to the primary

main inductance of the flyback transformer. The GD1 is used for controlling the FFR mode (see Chapter 4.2.8) by driving the

dedicated MOSFET that is connected to the ZVS winding at the flyback transformer.

The gate driver output stages consist of a regulated current source connected to VCC pin and a MOSFET switch connected

to GND (see Figure 20 and Figure 21). The peak source current at GDx is set to IGDxHPKSRC = -118 mA. The MOSFET switch

provides a discharge path for the main power MOSFET with a sink capability of RGDxLSNK ≤ 6.5 Ω.

The controlled source current determines together with the gate-source capacitance CGS and the gate-drain capacitance CGD

of the external power MOSFET the rising slope during turn-on phase (see Figure 22). The gate driver state control ensures

that the charged gate driver output voltage is clamped at the level VGDxH = 10.5 V.

The external gate resistor RGDx is therefore only meant for adjusting the peak sink current and the corresponding gate voltage

falling slope during the turn-off phase. Here the turn-on behavior is mainly dominated by the controlled limited current

source IGDxHPKSRC as the size of the external gate resistor is mainly limiting the higher peak sink current at GDx pin. When

dimensioning the serial gate resistor RGDx, also a minimum load capacitance needs to be considered after RGDx (see Chapter

9.1), which needs to be provided by the corresponding gate-source capacitance CGS of the external power MOSFET. This

ensures a smooth and stable settling of the voltage level VGDxH at the end of the turn-on phase.

Figure 20 GD0 output stage structure

RGD0LSNK

IGD0HPKSRC

GD0

VCC

GND

Q1

RCS

CS

Source current control

Gate driver state control

VGD0H

RGD0Flyback ctrl

VCC

CGS

Power

MOSFET

CGD

VD

Primary main inductance


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Figure 21 GD1 output stage structure

Figure 22 Gate drive output

4.2.8 Multi-mode operation

The multi-mode operation consists of two different operation modes that are controlled by the feedback voltage signal at

MFIO pin (see Table 3).

Table 3 Overview multi-modes

Symbol Operation Mode Description

BM Burst mode Chapter 4.2.9

FFR Forced frequency resonant mode during BM and DCMx operation Chapter 4.2.12

The configurable multi-mode operation depends on the inductance design, switching frequency, load condition and the

bulk voltage VBulk. It is characterized by the frequency scheme and peak current correlation shown in Figure 23. The peak

current limit VCSPK (y-axis) and the frequency limits are set according to the input signal at MFIO pin. The peak current limits

for VCSPK are shown for the low and high-line use case (see Chapter 4.2.3), which consider the propagation delay

compensation (PDC). The border for entering the burst mode (BM) is determined by the setpoint D. The actual peak current

and the actual switching frequency areas follow:

RGD1LSNK

IGD1HPKSRC

GD1

VCC

GND

Q2

Source current control

Gate driver state control

VGD1H

RGD1FFR modepulse control

VCC

CGS

Power

MOSFET

CGD

VD

ZVS-winding

t

VGDx(t)

VGDxH = 10.5 V

tGDxon

turn-on phase

Miller plateau is determined by

IGDxHPKSRC, CGD and VD

The turn-off phase is determined by

RGDx, RGDxLSNK, CGS, CGD and VD

dVGDx/dt is determined

by IGDxHPKSRC and CGS


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• in DCM1, DCM2 and DCM3 operation, the peak current and the switching frequency are directly given by the curve A-B-

C-D.

• in DCM1 the peak current changes with the voltage VMFIO and the switching frequency is fixed.

• in DCM2 the peak current is fixed, and the switching frequency changes with VMFIO.

• in DCM3 the peak current changes with the voltage VMFIO and the switching frequency is fixed until CRM operation is

taking place. The start of CRM cycles is depending on VBulk. The frequency in DCM3 is configurable. The highest

frequency is 139.4 kHz.

• the multi-mode controller selects the operating mode (BM, DCM1, DCM2, DCM3 with FFRZVS or CRM)

CRM switching cycles occur in DCM3 when the Vbulk voltage exceeds a lower Vbulk voltage level and the remaining off-time

is not sufficient to fully demagnetize the flyback transformer. In this mode no zero crossing is detected before the end of the

switching period determined, however IC gate is only allowed when zero crossing is detected. In such condition, IC will wait

the demagnetization finshes until the first zero crossing comes, once zero crossing is detected, IC will allow gate on. The fix

frequency operation will be bypassed here and frequency will be reduced and IC will switch at valley.

The following Figure 23 shows an example of using all possible multi-mode operation phases that are determined by the

corresponding setpoints A, B, C and D. The specific frequency law setting for XDPS21071 based on the FW: REV 1.0 is shown

in Chapter 4.2.8.1. Setpoints A and B can change from lowest switching frequency (burst frequency) e.g. 30 kHz to maximum

switching frequency 139.4 kHz. Setpoint B and C are also configurable, i.e VmfioC, VmfioB, VcsC are also configurable, so the

middle to light load efficiency can be optimized for different combination of frequency and peak current.

There is a special condition to limit the maximum frequency, when the bulk voltage is higher than Vbulk_high=200V and ZCD pin

voltage is lower than Vzcd_low=1.30V, the frequency will be clamped to fclamp which is a configurable based on different system

design, the default value is 105 kHz. When the bulk voltage is less than 200V and zcd pin voltage is higher than 1.47V, the

fclamp will be removed. By lower the frequency and work in DCM, switching loss can be reduced at high line and thus

increase efficiency.


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Figure 23 Configurable frequency law and peak current schemes depending on signal at MFIO pin

4.2.8.1 Frequency law setting for XDPS21071

The frequency law setting for XDPS21071 based on the is defined by the set point A, B, C and D as shown in Table 4.

Table 4 Corner points for frequency limitation curve and peak current setting for XDPS21071

Setpoint

A Corner point for maximum current at fixed frequency

VMFIOmax = 2.42 V

fSWmax = 139.4 kHz

VCSmaxLL = 594 mV

VCSmaxHL =392 mV

ABM

MULTIMODE_FREQLAW

VMFIO

fSW(VMFIO)

VMFIOC VMFIOB VMFIOmax

fSWmin

fSWmax

C

B A

VMFIO

VCSPK(VMFIO)

VCSmax

VMFIOBMEN

D

DCM2DCM1

VCSC

VCSmin

DCM3

A

BC

D

CRM

Start of CRM

operation

depending on

VBulk

fsw_clampFreq clamp at

special condition


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B Corner point for border between DCM3 and DCM2 for frequency reduction

VMFIOB = 1.82 V

fSWB = 140 kHz

VCSBLL = 443 mV

VCSBHL = 366 mV

C Corner point for border between DCM2 and DCM1 for fixed frequency and peak current reduction

VMFIOC = 1.01 V

fSWC = 24.9 kHz

VCSCLL = 443 mV

VCSCHL = 366 mV

D Corner point at minimum frequency setting

VMFIOD = 0.408 V

fSWmin = 24.9 kHz

VCSminLL = 92mV

VCSminHL =15 mV

4.2.9 Frequency jittering

In order to improve the EMI performance, the XDPS21071 enables frequency jittering at heavy load where the switching frequency is the maximum (fSWmax). The frequency jittering can improve the EMI signature.

Both the frequency amplitude and frequency period will jitter over time as shown in Figure 24 and Figure 25. The

default jittering magnitude is ± 3.125% of the maximum switching frequency fSWmax and the jittering period is

3.2ms.

Figure 24 Frequency jitter range

fSWmin

fSWmax

fSW

VMFIOVMFIOC VMFIOB

No. of sampled

points = 2N

No. of sampled points = 256

Jitter magnitude

= +/- (fSW * X%)


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Figure 25 Jittering magnitude and period

Table 5 Frequency jitter parameters

4.2.10 Burst mode operation

The burst mode (BM) is entered at light load to optimize efficiency and correlated total power consumption. The BM consists

of three main phases:

• Burst mode entry (see 4.2.10.1)

• Burst operation (see 4.2.10.2)

• Burst mode exit (see 4.2.11)

The burst mode control is described in the following chapters based on the block diagram in Figure 27 and the signal

overview in 4.2.10.1.

Figure 26 Block diagram burst mode control

fSW

Ajitter_Max / 8 points

fSW - AjitterMax

fSW + Ajitter_Max

100µs

Jitter Period = 32 points * 100µs = 3200µs

t

BM Ctrl

C7VMFIOBMEN

C3VMFIOBMEX1

C5VMFIOBMWK

C6VMFIOBMPA

BM 2-point

Regulation

BM Exit

BM Entry

burst-on

burst-off

MFIO

RMFIOPU

VVDDP = 3.3 V

Power

Management

Frequency

Law

Parameter Name Physical value Digital value

A_Jitter_percent_val 3.125% 5

A_Jitter_period_val 3.2ms 3


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Figure 27 Burst mode signals

4.2.10.1 Burst mode entry

Figure 27 is showing a typical signal scheme for entering quiet burst mode. The frequency law limits the minimum possible

power transfer defined at the setpoint D (see Chapter 4.2.8.1). With decreasing load, the voltage at MFIO pin sinks. Once the

voltage at MFIO pin falls below the burst mode entry threshold VMFIOBMEN, BM is then entered, the IC initiates a burst-off phase,

where the IC current consumption is reduced to IVCCquBM2. Afterwards, the voltage at MFIO pin controls the output voltage

control via the two-point regulator (see Chapter 4.2.10.2).

As the MFIO voltage determines the frequency and current command value, i.e the power. The efficiency at different output

voltage is also different. A look up table (LUT) based burst mode entry is implemented to cover very small burst enter/leave

hysteresis. Based on the sensed ZCD voltage signal which is output voltage related, a different VMFIO is used to determine the

entering energy for burst mode operation. The small the output voltage, the bigger the entering energy, i.e larger Vmfio

4.2.10.2 Burst operation

The two-point regulator, that is activated during burst mode operation, is implemented with the comparators C5 and C6

(see Figure 26) with the two thresholds VMFIOBMWK and VMFIOBMPA to determine the burst-on and burst-off phase depending on

the feedback signal at the MFIO pin. During this phase, the error signal is now used for the two-point regulator scheme,

whereas it correlates with the inverse output voltage AC ripple signal shape (see Figure 27). The wake-up threshold VMFIOBMWK

determines the output voltage bottom peak ripple point and the pause threshold VMFIOBMPA determines the output voltage

upper peak ripple point. Once the voltage at the MFIO pin exceeds the threshold VMFIOBMWK, IC will be waked-up, it takes

tMFIOBMWK = 26.6 µs till the first gate pulse of the burst sequence starts. The switching cycles during burst-on phase are

predefined and not depending on the voltage at the MFIO pin. All burst sequence pulses have the same switching frequency

fSWBSPx, but progressive changed voltage VCSBSPx as shown in Table 17. All following pulses have then the same peak value for

VCS as the fourth pulse VCSBSP4. The peak value of the Vcs determines, together with the set frequency fSWBSP4, the deliverable

limited maximum power during the quiet burst operation. If the output load is exceeding the deliverable limited power for

the burst operation, the voltage at MFIO pin will increase. After it exceeds the burst mode exit threshold VMFIOBMEX, the control

IC may exit burst mode (see Chapter 4.2.11).

t

VOUT(t)

t

IOUT(t)

t

VMFIO(t)

VMFIOBMEN

VMFIOBMPA

VMFIOBMWK

VMFIOBMEX

VOUTnom

t

VCS(t)

VCSmin,

VCSBSP4,

VCSBMEX

tMFIOBMWK

burst-on phase burst-off (pause) phase

entering burst mode

exit burst mode

wake-up

entering pause

Wake-up when wake-up threshold met


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4.2.11 Burst mode exit

At load jumps above the burst mode exit power level, a fast burst mode exit is supported to limit the drop in output voltage.

A sudden load demand causes a rising slope at MFIO pin. Once the voltage VMFIO exceeds the threshold VMFIOBMEX, the IC exits

the burst mode immediately.

Once burst mode is exit, the two-point regulation is terminated and the next pulse is determined by the fixed peak current

setting VCSBMEX. The further consecutive pulses are determined by the frequency law (see Chapter 4.2.8) with the voltage VMFIO

controlling the switching cycles.

4.2.12 Forced frequency resonant (FFR) mode operation

XDPS21071 provides a special forced frequency resonant (FFR) mode to reduce significantly switching losses during

operation in discontinuous conduction mode (DCM). Furthermore conducted EMI in the high frequency spectrum > 10MHz

and especially radiated EMI can be greatly reduced, which supports the usage of high speed optimized super junction

MOSFETs. The idea is to turn on the main power MOSFET only at a controlled lowest drain voltage level in a self-generated

oscillation period after demagnetization phase of the flyback transformer has been finished. This self-generated oscillation

period is derived from an additional gate driver pulse that introduces to the flyback transformer at a self-determined time a

defined negative magnetization. The level of negative magnetization current can be configured (see Chapter 5)

Compared to the so called quasi-resonant (QR) operation, which is focusing on turning on the main power MOSFET only in

the valleys after transformer demagnetization, the FFR provides full control on the switching frequency and the drain

voltage swing down level for turning on the MOSFET. Higher frequency design approaches can now be exploited for low line

without compromising on efficiency and EMI for the high line operation. When reducing the load, frequency foldback to

lowest frequency levels can be supported with avoiding any hard switching cycle (see Chapter 4.2.8.1).

Figure 28 shows the required signals in the application for FFR mode operation. The second gate driver GD1 drives Q1 for

initiating the self-controlled zero voltage switching (ZVS) cycle. The HV pin provides the VBulk voltage measurement to adapt

the timings for the ZVS pulse.

Figure 28 Required signals for forced frequency resonant (FFR) mode operation

GD1

GND

vPri vSec

FFR MODE

VBulk

VOut

vDrain

vZVS

GD0

Q1

Q0

HV

RZCDH

RZCDL

vAux ZCD


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The ZCD pin provides the zero crossing detection to enable main gate generation. The ZVS gate can be enabled based on

configurable line voltage with 20Vdc hysteresis.

Figure 29 shows the FFR mode signal wave forms and associated timings. The FFR mode is caused by introducing a ZVS pulse

via the gate driver GD1 during the time frame t1-t2 and subsequent dead-time tZVSdead from t2-t3 until gate driver GD0 turns

on the main power MOSFET. The dead-time tZVSdead should be dimensioned in such a manner that the turn-on of GD0 takes

place at the minimum drain voltage oscillation magnitude, which correlates to a transformer magnetization close to zero.

The forced frequency operation of GD0 is achieved by directly controlling the switching period tSWperiod of GD0. GD1 is

prematurely turned on after the delay time tZVSdelay, when a zero crossing has been detected.

Figure 29 Signal overview for forced frequency resonant mode operation

The length of the ZVS pulse and the charged voltage of the ZVS capacitor determine the amount of introduced negative

transformer magnetization. A higher level of introduced negative magnetization leads to a lower drain voltage swing down,

which could further optimize the switching losses and high frequency EMI behavior of the main power MOSFET. However,

as this comes along with the expense of increased power losses associated with the additional ZVS pulse generation, a trade

off needs to be found to maximize the potential increase in efficiency and reduction in EMI. Depending on the chosen main

power MOSFET different drain voltage levels might be adapted for turning on the main power MOSFET. This is mainly

depending on the output capacitor characteristic of the power MOSFET, which is highly nonlinear increasing, when going

for low drain voltages. The amount of necessary negative magnetization current increases with the size of the output

capacitor of the power MOSFET and parastics coupling capacitor of transformer. Therefore the dimensioning for the ZVS

pulse generation is significantly depending on the system dimensioning. The default parameter set is optimized for a 45 W

USB PD adapter.

vDrain(t)

vZVS(t)

0

VBulk

NPri / NSec × vSec

NZVS / NSec × vSec

NZVS / NPri × VBulk

tf

FFR_MODE_SIGNALS

t

t

tGD0Off

iMag(t)

t

vGD0(t)

vGD1(t)

t

t

tGD1Off

tGD1on

tZVSdead

Forced frequency resonant mode

tSWperiod

t1 t2 t3 t4t1 t2 t3 t4 t5

tZVSdelay

0


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The required ZVS pulse length tGD1on is depending on VBulk. The GD1 on-time tGD1on needs to increase with increasing VBulk to

ensure the same low drain voltage level for turning on the main power MOSFET for the whole VAC input range. Whereas the

ZVS dead-time is fixed at tZVSdead = 220 ns (see Chapter 5.2 ).

The default configured relationship between tGD1on and VBulk and determined by following implemented equation:

𝒕𝑮𝑫𝟏𝒐𝒏 = (𝑩𝑼𝑳𝑲_𝑽𝑶𝑳𝑻𝑨𝑮𝑬(𝑽) ∙𝑲𝒛𝒗𝒔𝒐𝒏𝒇𝒂𝒄𝒕𝒐𝒓

𝟔𝟓𝟓𝟑𝟔 𝒏𝒔

𝑽) ∗ 𝟏𝟓. 𝟏𝟓𝒏𝒔 + 𝟑𝟏. 𝟔 𝒏𝒔 ( 10 )

The parameter BULK_VOLTAGE(V) is calculated based on the measured current at HV pin IHV via the external resistor RHV =

102kΩ. Figure 30 shows the default configured relationship between the controlled ZVS pulse length tGD1on and VBulk based on

default Kzvsonfactor=3200.

Figure 30 VBulk depended adaptive ZVS pulse length tGD1on

4.2.13 UART function at GPIO pin

GPIO pin provides a digital IO interface for UART communication. Configuration of defined parameters and HW setups are

supported (see Chapter 5.2). The UART function at GPIO pin is normally enabled till the VCC brown-in is reached (see Chapter

4.1.2). After VCC brown-in, the UART function is disabled.

On the other hand, the UART function can be kept enabled during normal operation by sending a corresponding soft

command before VCC brown-in. Then configuration “on the fly” is supported and change of parameters during normal

operation is possible.

4.3 Protection features

Table 6 shows the protection features and their corresponding reaction on malfunction. Two protection modes (auto-restart

mode and latch mode) as well as a HW reset (IC reset by VCC under-voltage lockout) are implemented.

Note: All protection features w/o UVOFF only apply during normal operation. During sleep phase (in burst or protection

mode), neither pin measurement of pin voltage nor temperature sensor is active.

Table 6 Protection Features

Protection Feature Symbol Reaction Description

VCC Under-Voltage lockout UVOFF Deactivate IC Chapter 4.3.3

0

50

100

150

200

250

300

350

70 120 170 220 270 320 370

tGd

1o

n(n

s)

Vbulk(V)

ZVS ontime Vs Bulk voltage


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Brown-In Protection (when Brown-in conditions not met) BIP Block switching Chapter 4.3.4

Brown-Out Protection BOP Stop switching Chapter 4.3.5

Over-Current Protection level 1 OCP1 CbC limit Chapter 4.3.6

Over-current protection level 2 OCP2 Auto-restart Chapter 4.3.7

High input at CS pin (> 200 µs) CShigh Auto-restart Chapter 4.3.8

MFIO pin High MFIOH Auto-restart Chapter 4.3.9

Internal Over-Temperature Protection IntOTP Auto-restart Chapter 4.3.10

Primary side output Over-Voltage Protection VoutOVP Auto-restart /

Latch mode Chapter 4.3.11

Over load protection OLP Auto-restart Chapter 4.3.12

CS pin short protection CSP Auto-restart Chapter 4.3.13

4.3.1 Auto-Restart Mode (ARM)

Once the auto-restart mode is entered, the IC stops the gate driver switching at GD0 pin and enters stand-by mode with

reduced current consumption of IVCCquAR = 160 µA. After the auto-restart off-time tAR = 3 s, the control IC resumes its operation

with soft-start after the VCC capacitor is charged up and the VCC voltage reaches its turn-on threshold. During the auto-

restart off-phase, the HV startup-cell is operating in the bang-bang mode (see Chapter 4.1.5.2) to keep the VCC voltage at a

high level to have enough energy stored in the VCC capacitor for the system startup.

4.3.2 Latch Mode (LM)

When latch mode is entered, the gate driver switching at GD0 pin is stopped and the control IC enters stand-by mode where

the current consumption is reduced to IVCCquLM = 150 µA. During the latch mode the HV startup-cell is operating in the bang-

bang mode to keep the IC alive and staying in latch mode. Here the voltage VVCC is varying in a wider range compared to the

bang-bang mode operation in auto-restart mode (see Chapter 4.1.5.1).

4.3.3 VCC Under-Voltage lockout (UVOFF)

The implemented VCC under-voltage lockout (UVLO) ensures a defined activation and deactivation of the IC operation

depending on the supply voltage VVCC. The UVLO contains a hysteresis with the voltage thresholds VVCCon = 20.5 V for

activating the IC. For deactivating the IC, two thresholds are defined. They are:

• VVCCoff = 7.2 V during normal operation / during auto-restart break time

• VVCCoffBO = 9.6 V after brown-out detected

The higher VVCCoffBO threshold leads to earlier deactivation of the IC and earlier charge-up of the VCC capacitor and supports

a new system startup earlier.

Both VCC on- and off-thresholds contain a spike blanking tVCCon and tVCCoff.

4.3.4 Brown-In Protection (BIP)

At initial power-up or auto-restart, the brown-in condition at the HV pin and at the VCC pin must be fulfilled for starting the

soft-start procedure. The controller measures the current at HV pin through the internal shunt resistor RM (see Figure 3). The

input brown-in is fulfilled if the current IHV exceeds the threshold IHVBI = 1.15 mA. The VCC brown-in is fulfilled if the voltage

VVCC is above the threshold VVCCBI = 15 V. No blanking time applies for brown-in detection. If one of the brown-in conditions is

not fulfilled, the IC stays active, but without gate switching. The voltage at VCC pin drops then. Once it falls below the


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threshold VVCCoff = 7.2 V, the control IC is deactivated, and the startup cell is turned on automatically to charge up the VCC

capacitor.

4.3.5 Brown-Out Protection (BOP)

The brown-out protection for bulk voltage prevents the IC from operating with a too low line voltage, which could lead to

high RMS current stress in the application. Brown-out detection is also performed via the HV pin as for brown-in detection.

Here an under-voltage detection of the bulk voltage VBulk is provided to support brown-out protection. The measured current

IHV is compared with the bulk under-voltage detection threshold IHVBO = 0.443 mA. The brown-out protection applies if bulk

under-voltage is detected for certain blanking time. This blanking time is set to tHVBO = 1.09 ms during normal operation and

to tHVBOSS = 5.27 ms during soft-start phase. Once brown-out protection is entered, the IC stops switching, but it is still active

and the VCC turn-off threshold is increased to VVCCoffBO = 9.6V. Once VCC falls below VVCCoffBO, the HV startup cell turns on to

charge up the VCC capacitor (see Chapter 4.1.3).

4.3.6 Over-Current Protection level 1 (OCP1)

The over-current protection level 1 (OCP1) is performed by means of the cycle-by-cycle peak current control via the

comparator OCP1 (see Figure 3). A leading edge blanking (see Chapter 4.2.5) prevents the IC from false switching-off the

power MOSFET due to the leading edge spike. The maximum peak setting for VCS is compensated by the propagation delay

compensation (see Chapter 4.2.3), to provide an input voltage level independent current limitation. The highest peak setting

for VCS of VCSmaxLL(max) = 594 mV occurs at low-line and defines the maximal saturation current of the flyback transformer.

4.3.7 Over-Current Protection level 2 (OCP2)

The over-current protection level 2 (OCP2) protects the flyback converter under critical fault conditions such as shorted

transformer windings or shorted secondary side rectifier diode. In this case, the repeating cycle-by-cycle over-current

protection level OCP1 cannot properly limit the inductor current due to the very steep slope of the current ramp and the

propagation delay in the peak current control. With the over-current protection OCP2, once the threshold VCSOCP2 = 0.8 V is

exceeded for longer than tCSOCP2BL = 616.2 ns during normal operation or tCSOCP2BL = 1.001 µs during startup operation, auto-

restart mode (see Chapter 4.3.1) is entered. In this way, over-heating of the flyback converter is avoided.

4.3.8 High input at CS pin (CShigh)

The CS pin can also be used in a combined manner for a high input signal like external over-temperature which is having a

temperature detection circuit together with a reference voltage, to trigger auto-restart mode (see Chapter 4.3.1).The auto-

restart mode is triggered by pushing up the CS pin for 10ms. The trigger threshold for CShigh is 0.5V ~ 0.8V. In case of

transformer short winding, VCS voltage goes quickly above VCSOCP2; IC will stop the gate and goes to auto-restart mode after

OCP2 blanking time tCSOCP2BL.

4.3.9 MFIO pin high (MFIOH)

There are several phenomena that causes MFIO pin high; feedback loop open, overload, etc. The feedback open-loop

protection is implemented by means of a digital comparator C2 (see Figure 3). When the voltage at MFIO pin exceeds the

threshold VMFIOH = 2.41 V, a timer is triggered. Auto-restart mode (see Chapter 4.3.1) is entered if the timer exceeds the period

of tMFIOH = 31.3 ms. This is mainly for open loop and startup protection, during startup, since the output voltage hasn’t reach

the setpoint, MFIO pin voltage is always high.

4.3.10 Internal over-temperature detection (IntOTP)

An internal over-temperature protection is implemented in this control IC. Once the internal temperature exceeds the

threshold of TJOTP = 130 °C for longer than the blanking time tJOTP = 10.5 ms, internal over-temperature is detected and the


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control IC enters auto-restart mode (see Chapter 4.3.1). The normal operation will be resumed if the internal temperature is

dropped by 20 °C from TJOTP.

4.3.11 Primary side output Over-Voltage Protection (VoutOVP)

The IC provides primary side output over-voltage detection via the ZCD pin. Here the reflected output voltage from the

flyback transformer is sampled at ZCD pin during the demagnetization phase (see Chapter 4.2.1.1). In each switching cycle,

the XDPS21071 compares the measured output voltage VZCDVO with the output over-voltage threshold VZCDOVP = 2.75V.

That comparison can refer to

• the demagnetization phase of the same switching cycle or

• the demagnetization phase of an earlier switching cycle.

A blanking filter is implemented to avoid erroneous output over-voltage detection. This filter consists of a symmetrical

counter. Each comparison where VZCDVO < VZCDOVP, will decrement the counter (but not below zero) while each comparison

where VZCDVO ≥ VZCDOVP will increment the counter. If the counter is increased to NZCDOVP+1, auto-restart mode (see Chapter 4.3.1)

is entered. This protection mode is a configurable parameter. It can be changed to latch mode (see Chapter 4.3.2) by .dp

Vision.

4.3.12 Over load power protection

The IC provides protection against over load by means of the integrated maximum peak current limitation combined with

an over-load timer (OLPT). Once OLP is detected, the control IC enters auto-restart mode (see Chapter 4.3.1).

XDPS21071 uses current mode control, so the OCP1 Look-Up-Table (LUT) values are designed by considering the propagation

delay at different line voltages and operation modes. Once the OCP1 LUT value is hit, the OLP timer will start to count up. The

counter will reduce the count if OCP1 LUT value is not hit in the cause of OCP1 protection. Finally the IC will enter AR if

protection timer reaches the pre-definite time.

This protection can distinguish with open loop protection by setting different OLP timer. E.g during power up, Vmfio is always

high before voltage rise up, so with different timer, it can separately control the open loop protection and over load

protection.

Table 7 Power protection parameters

4.3.13 CS pin short protection

During fisrt power up, IC will check three pulses continuously, if the pulses length are longer than 1.5 µs , IC will go to auto restart mode.

Protection Parameter Name Protection level Digital value Blanking time

OLP LOLP 0.594 V @ 80 VDC

0.392 V @ 376 VDC

255 @ 80 VDC

202 @ 376 VDC 31.3ms


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Configuration

5 Configuration This chapter contains an overview about the parameters and functions that can be configured via the UART interface at GPIO

pin. Furthermore the configuration procedure is described. Mapping overviews show the correlation between the data sheet

parameters and the correlated firmware symbols. Furthermore the equations are listed to provide the specific correlation

between the configured FW parameter and the system parameter.

The chapter “configuration” is grouped in following sections:

• Overview of configuration parameters using .dp Vision (Chapter 5.1)

• Overview of configurable parameters and functions (Chapter 5.2)

The following shown default parameter settings correlate to the firmware version REV 1.4 .

5.1 Overview of configurable parameters using .dp Vision

The Infineon graphic user interface (GUI) .dp Vision connects to XDPS21071 via the isolated USB interface board called .dp

Interface Gen2. The .dp interface Gen2 provides power via VCC to XDPS21071 and connects via UART interface at pin

GPIO/UART. The common UART interface enables communication with the IC even without the interactive GUI tool. This

allows easy configuration during mass production.

For project development, a graphic user interface called .dp Vision guides the designer through the configuration of

parameters. More detailed information on .dp Vision can be found in the .dp Vision User Manual prepared by Infineon.

5.2 Overview of configurable parameters and functions

There are 2 types of parameters; configurable and fixed. The configurable parameters are allowed to change. On the other

hands, the fixed parameters are not recommended to change. The list of parameters shown is default value and has been

verified in the 45W HD adapter demonstrator. The parameters are typical values. Please refer to the corresponding electrical

characteristics in Chapter 6.5 for the min/max tolerances.

5.2.1 Configurable parameters and functions

The following table shows the default value of the configurable parameters. If necessary, the parameters can be changed.

Table 8 List of configurable Parameters

Feature Parameter Default Description Chapter/Table

Propagation

delay

compensation for

peak current

control

PDC_FACTOR 13000d Propagation Delay Compensation factor

Chapter 4.2.3, PDC_OFFSET 0d Propagation Delay Compensation offset

Leading edge

blanking (LEB) tCSLEB 269 ns

Blanking filter at CS pin to avoid erroneous turn-

off of GD0 due to leading edge spike at GD0 turn-

on

Chapter 4.2.5

ZVS dead-time tZVSdead 220 ns Dead-time between end of ZVS pulse at GD1 and

start of GD0 Chapter 4.2.11

ZVS pulse length

factor kZVSonfactor 3200 ZVS pulse length factor

Gate driver

capability I_GD0_drive 31mA Sourcing current of Gate driver 0 Chapter 4.2.7

Protections TJOTP 130 °C Internal Over-temperature detection level Chapter 4.3.10


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Configuration

tocp2 600ns Blanking time for OCP2 of Vcs signal

tpeakpower 30ms Blanking time for overload protection

En_OLP Enabled To enable or disable over load protection

Response_OVP Autorestart Protection mode for OVP, configurable for AR or

Latch Chapter 4.1.5

Burst mode

parameters

Vcs_bst 0.128V Burst mode current limit

Chapter 4.2.10

Freq_bst 50.0 kHz Burst mode frequency

V_bst_pause 1.35V Pause threshold at MFIO pin during on-phase in

burst mode operation

V_bst_exit 2.00V Burst mode exit voltage at MFIO pin

T_reentry_bst 5ms minimum time to re-entry the burst mode

Frequency law

settings

Fsw_A 140kHz Frequency settings for point A Chapter 4.2.8

Vmfio_C 1.00V MFIO pin corner point C voltage

Vmifo_B 1.80V MFIO pin corner point B voltage

Vcs_BC 0.45V Current sense limit between point B and C

fclamp 105kHz Frequency clamp when Vin>200 V, Vzcd<1.28 V

Adaptive Vcs

offset

K_Vcs_offset 28000 Gradient for compensation curve

Chapter 4.2.1.3

Vcs_offset_Vzcdzeropoi

nt 79

ZCD voltage level( digital value) without Vcs

offset

En_Vcs_offset Enabled To enable or disable Vcs_offset compensation


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Electrical Characteristics

6 Electrical Characteristics All signals are measured with respect to ground GND pin. The voltage levels are valid if other ratings are not violated.

Attention: Limits are subject to change according to test engineering results

6.1 Definitions

Figure 31 illustrates the definition for the voltage and current parameters used in this data sheet.

Figure 31 Voltage and Current Definitions

Values indicated under “absolute maximum ratings” must not be exceeded.

Values indicated under “operating conditions” can be exceeded if a corresponding explicit “absolute maximum rating” is

given for this parameter, but the related function of the device is not ensured.

6.2 Absolute Maximum Ratings

Stresses above the values listed below may cause permanent damage to the device. Exposure to absolute maximum rating

conditions for given periods may affect device reliability. Maximum ratings are absolute ratings; exceeding anyone of these

values may cause irreversible damage to the device.

Table 9 Absolute Maximum Ratings

Parameter Symbol Limit Values Unit Remarks

min max

Voltage at VCC pin VVCC -0.5 26 V 3)

Voltage at GD0 pin VGD0 -0.5 VVCC+0.3 V Internally clamped to VGD0H

Average current at GD0 pin |IGD0|AVG — 20 mA 1), absolute average over

1 ms

RMS Current at GD0 pin IGD0RMS — 100 mA 2), RMS over 20 µs

Voltage at GD1 pin VGD1 -0.5 VVCC+0.3 V Internally clamped to

VGD1H

Voltage at HV pin VHV -0.5 600 V 3)

Current at HV pin IHV — 10 mA

Voltage at ZCD pin VZCD -0.5 3.6 V 3)

Maximum negative transient

input voltage for ZCD -VZCD_TR — 2.0 V 4) <500ns

Voltage at CS pin VCS -0.5 3.6 V 3)

DUT

DEFINITIONS_V_I_DS

+V+

_

+I

PIN

GND

+IPIN

+VPIN


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Maximum negative transient

input voltage for CS -VCS_TR — 3 V 4)<500ns

Maximum transient input

clamping current for ZCD

and CS

-ICLN_TR — 6 mA 4)<500ns

Maximum permanent input

clamping current for ZCD -ICLN_DC_ZCD — 3.5 mA

Maximum permanent input

clamping current for CS

-Icln_DC_CS — 2.5 mA

Voltage at MFIO pin VMFIO -0.5 3.6 V 3)

Voltage at GPIO pin VGPIO -0.5 3.6 V 3)

Junction temperature TJ -40 125 °C

Storage temperature TS -55 150 °C

Maximum power dissipation PTOT — 0.46 W TA = 60 °C

TJ = 125 °C

RthJA = 141 K/W

Soldering temperature TSold — 260 °C 5), wave soldering

ESD capability VHBM — 2 kV 6), human body model

VCDM — 500 V 7), charged device model

Latch-up capability ILU — 150 mA 8) 1) Relevant w.r.t. electromigration. 2) Relevant w.r.t. thermal heating at small duty cycles. 3) Permanently applied as DC value. 4) Negative range must fulfill clamping current limits 5) According to JESD22-A111A 6) According to ANSI/ESDA/JEDEC JS-001-2012 7) According to JESD22-C101F 8) According to JESD78D, 85 °C (Class II) temperature

6.3 Package Characteristics

Table 10 Thermal Characteristics


min max

Thermal resistance from junction to

ambient RthJA1 — 141 K/W 1), JEDEC 1s0p

RthJA2 — 81 K/W 1), JEDEC 2s2p

Creepage distance between HV vs.

GND-related pins

DCR 3.3 — mm

1) IC footprint and PCB trace with 35 µm Cu, TA = 85 °C, 180 mW power dissipation


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6.4 Operating Range

Table 11 shows the operating range, in which the electrical characteristics shown in Chapter 6.5 are valid.

Table 11 Operating Range


min max

Junction Temperature TJ -25 125 °C

Voltage at VCC pin VVCC VVCCoff VVCCon V 4)

Voltage at HV pin VHV -0.3 600 V

Current into HV pin IHV — 5 mA Limited by external RHV

Voltage at ZCD pin VZCD -0.3 3.3 V An applied voltage lower

than 0V needs to respect

the negative maximum

clamping current IZCD

Current into ZCD pin IZCD -1.5 — mA

Voltage at CS pin VCS -0.3 3.3 V

Current into CS pin ICS -10 0.1 mA

Voltage at MFIO pin VMFIO -0.3 3.3 V

Voltage at GPIO pin VGPIO -0.3 3.3 V

Voltage at GD0 pin VGD0 -0.3 VVCC+0.3 V Internally clamped at VGD0H

Voltage at GD1 pin VGD1 -0.3 VVCC+0.3 V Internally clamped at VGD1H

Minimum required capacitive load at

GDx pin CGDxload 1.5 — nF 1), 2), RGDxload = 10 Ω in

series to CGDxload

Low state output reverse current at

GDx pin

-IGDxLREV — 100 mA 3), applies if VGDx < 0 V

and driver at low state

1) Not tested in production test. 2) See figure in Chapter 8.1 3) Assured by design. 4) In practical application design, the applied Vcc voltage nees to be less than 19V ( min. value of VVCCon)


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6.5 Characteristics

The electrical characteristics involve the spread of values given within the specified supply voltage and junction

temperature range TJ from -25 °C to 125 °C. Typical values represent the median values related to TJ = 25°C. All voltages refer

to GND and the assumed supply voltage is VVCC = 14 V, if not otherwise mentioned.

The following characteristics are specified

• Power Supply at VCC pin (Table 12)

• HV pin (Table 13)

• ZCD pin(Table 14)

• MFIO pin (Table 15)

• GPIO pin (Table 16)

• CS pin (Table 17)

• GDx pin (Table 18)

• IC Control Features (Table 19)

• IC Protection Features (Table 20)

Table 12 Electrical Characteristics of the Power Supply at VCC pin

Parameter Symbol Values Unit Note/Test Condition

Min. Typ. Max.

VCC UVOFF current IVCCUVOFF — 30 50 µA VVCC < VVCCon(min) - 0.3 V

VCC operating current IVCCop1 — 7.5 8.7 mA 1), normal operation

with gate driver GDx

output low, GPIO pin

open, IMFIO-=280 µA

IVCCop2 — — 8.4 mA 1), as for IVCCop1, but

TJ = 110 °C


TJ = 100 °C


TJ = 85 °C

IVCCop5 — 11 — mA 1), Cload = 2 nF,

fSWGDx = 83 kHz,

IMFIO=-280µA,TJ=25˚C

VCC average quiescent

current in latched mode

IVCCquLM 0.080 0.150 0.300 mA VVCC=8 V, latch mode,

MFIO, GPIO open

VCC average quiescent

current during sleep

phase in auto-restart

mode

IVCCquAR — 0.160 0.310 mA VVCC=7 V, sleep phase

in auto-restart mode,

MFIO, GPIO open

VCC quiescent current

during sleep phase in

quiet burst mode

IVCCquBM1 — 0.18 1.2 mA Burst mode entered,

MFIO, GPIO pin open

IVCCquBM2 — 0.46 1.5 mA 1), 2), burst mode

entered, IMFIO=-280

µA,

GPIO pin open


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IVCCquBM3 — — 1.2 mA 1), as for IVCCquBM2,

TJ=110˚C


TJ=100˚C


TJ=85˚C

VCC turn-on threshold VVCCon 19 20.5 21.5 V dVVCC/dt =0.2 V/ms

VCC turn-off threshold VVCCoff

6.84

7.2

7.56

V

During normal

operation, IC latched

and auto-restart

break time

VVCCoffBO 9.12 9.6 10.08 V After brown-out

detected

VCC turn-on/off

hysteresis during normal

operation

VVCChysOP — 13.3 — V 1)

VCC turn-off blanking

time tVCCoff 550 — — ns 1), 1 V overdrive

VCC turn-on delay tVCCon — — 2 µs 1)

VCC threshold for turning

on HV startup cell in

protection mode

VVCCBBon

8.5

9

9.5

V

1), bang-bang mode

during auto-restart

and latch mode

Blanking time for turning

on HV startup cell in

auto-restart and latch

mode

tVCCBBon 0.6 — 2.2 µs 1), 1 V overdrive,

bang-bang mode

VCC threshold for turning

off HV startup cell in


mode

VVCCBBoff 19 20.5 21.5 V

Blanking time for turning

off HV startup cell in


mode

tVCCBBoff 0.7 — 2.4 µs 1), 1 V overdrive,

bang-bang mode

VCC brown-in threshold VVCCBI 8.4 9.1 9.7 V 1), 3) 1) Not tested in production test.

2) Current value is based on the sum of external sink current IMFIO and IC quiescent current IVCCquBM1. 3) See configuration Chapter5

Table 13 Electrical Characteristics of HV pin

Parameter

Symbol

Values Unit

Note/Test Condition

Min. Typ. Max.


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Brown-in threshold IHVBI 1.10 1.156 1.21 mA 1),2), no blanking

Brown-out threshold IHVBO 0.420 0.443 0.465 mA with blanking tHVBO

Brown-out blanking time

during normal load tHVBO 0.99 1.09 1.21 ms 1), 2), 3)

Brown-out blanking time

during soft-start tHVBOSS 4.95 5.27 5.59 ms 1), 2)

HV peak VCC charge

current capability IHVchargeVCC 2.4 5 10 mA 4), VVCC=1 V,

VHV=30 V

Leakage current at HV pin IHVLK — — 10 µA VHV=600 V,

HV startup cell

disabled

Bulk voltage threshold for

special frequency clamp

Vbulk_high 200 V 1)

1) Not tested in production test. 2) See configuration Chapter 5. 3) Min. and max. values are based on master clock period tMCLK limits (see Table 20). 4) Max. peak charge current will be limited in the application by an external resistor connected to HV pin.

Table 14 Electrical Characteristics of ZCD pin

Parameter

Symbol

Values Unit

Note/Test Condition

Min. Typ. Max.

Input leakage current, no pull

device IZCDLK -10 — 10 µA VZCD=0 V/3 V

-1 — 1 µA 1), TJ=85˚C

VZCD=0 V/3 V

ZCD voltage threshold VZCDTHR 20 35 55 mV

ZCD voltage threshold

debouncing time tZCDPW 150 — — ns 1), shorter pulses are

ignored

ZCD zero crossing

comparator propagation

delay

tZCDP 20 40 60 ns 1)

ZCD ringing suppression

time tZCDRS 1.80 1.91 2.03 µs 1), 2)

ZCD clamping of neg.

voltages

-VZCDclp 150 180 220 mV

Minimum time from GD0

turn off to first zero-

crossing to ensure settling

of ZCD sampling

tGD0offZCMin — — 3.33 µs 1)

ZCD output over-voltage

threshold in HV mode VZCDOVP 2.72 2.75 2.79 V 1), 2) tGD0offZC≥tGD0offZCMin


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ZCD debouncing counter

threshold for output over-

voltage detection

NZCDOVP — 2 — 1), 2) tGD0offZC≥tGD0offZCMin

ZCD threshold voltage for

special clamp of switching

frequency

Vzcd_low 1.272 1.296 1.320 V 1)

ZCD threshold voltage

hysteresis

- 0.177 - V 1)

1) Not tested in production test.

2) See configuration Chapter 5.

Table 15 Electrical Characteristics of MFIO pin

Parameter

Symbol

Values Unit

Note/Test Condition

Min. Typ. Max.

Input leakage current without

pull device activated IMFIOLK -10 — 10 µA VMFIO=0 V/3 V

-1 — 1 µA 1), TJ=85˚C

VMFIO=0 V/3 V

Open circuit output

voltage VMFIOOC 3.0 3.3 3.6 V Normal mode

3.0 3.2 3.4 V 1), 2), sleep mode

Open-loop detection

threshold VMFIOH 2.35 2.41 2.47 V 1), 3)

Maximum control range VMFIOmax — 2.42 — V 1), 3)

Setpoint B of the

frequency law VMFIOB 1.773 1.821 1.869 V 1), 3)

Setpoint C of the

frequency law VMFIOC 0.965 1.01 1.046 V 1), 3)

Setpoint D of the

frequency law

VMFIOD 0.372 0.408 0.443 V 1), 3)

Burst mode entry

threshold

VMFIOBMEN1 0.570 0.607 0.644 V 1), 3) Vzcd<1.723V

VMFIOBMEN2 0.419 0.455 0.491 V 1),3)

1.723V=<Vzcd<2.152V

VMFIOBMEN3 0.372 0.408 0.443 V 1), 3) Vzcd>=2.152V

Internal pull-up resistor RMFIOPU 8.8 11 13.2 kΩ 3)

Burst wake-up threshold

during burst-off phase VMFIOBMWK 1.47 1.60 1.73 V 1), 3)

Minimum input pulse

width for burst wake-up tMFIOBMWKPW 300 — — ns 1), shorter pulses will

be suppressed


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Time between burst

wake-up and the first

burst sequence pulse

tMFIOBMWK — 26.6 32 µs 1),

dVMFIO/dt = 100 mV/µs

Burst-off entering

threshold during burst-

on phase

VMFIOBMPA 1.322 1.366 1.410 V 1), 3)

BM exit threshold VMFIOBMEX 1.970 2.020 2.070 V 1), 3)

Not tested in production test.

During burst mode, auto restart and latch mode operation.

See configuration Chapter 5.

Table 16 Electrical Characteristics of GPIO pin

Parameter

Symbol

Values Unit

Note/Test Condition

Min. Typ. Max.


pull device activated IGPIOLK -10 — 10 µA VGPIO=0 V/3 V

-1 — 1 µA 1), TJ=85˚C

VGPIO=0 V/3 V

Open circuit output

voltage

VGPIOOC 3.0 3.3 3.6 V

Input capacitance CGPIOIN — — 10 pF 1

Threshold for logic “0” VGPIOIL — — 1.0 V

Threshold for logic “1” VGPIOIH 2.0 — — V

Low input pull-up

current

-IGPIOLPU 30 — 90 µA 2) at VGPIOIL(max)

Output sink current IGPIOSNKOL — — 2 mA

Output source current -IGPIOSRCOH — — 2 mA

Output rise time (0 → 1) tGPIORISE — — 50 ns 20 pF load, push/pull

output

Output fall time (1 → 0) tGPIOFALL — — 50 ns 20 pF load, push/pull

output 1) Not tested in production test. 2) Currents flowing out of the device (DUT) are marked with a negative sign in the ‘Symbol’ column

Table 17 Electrical Characteristics of CS pin

Parameter

Symbol

Values Unit

Note/Test Condition

Min. Typ. Max.


pull device activated ICSLK -10 — 10 µA VCS=0 V/3 V

-1 — 1 µA 1), TJ=85˚C

VCS=0 V/3 V


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CS OCP2 threshold VCSOCP2 0.76 0.80 0.84 V

CS OCP2 propagation delay

until GD0 turn-off at

IGD0>2mA

tCSGD0OCP2 125 155 190 ns 1) dVCS/dt=100 V/µs

CS OCP2 blanking time for

auto-restart

tCSOCP2BL 498.8

810

616.2

1001

733.6

1192

ns

ns

Normal operation

During startup 1), 2), 3)

CS OCP1 comparator

minimum pulse width tCSOCP1PW — 35 — ns 1), shorter pulses will

be suppressed

CS OCP1 propagation delay

until GD0 turn-off at

IGD0 > 2 mA

tCSOCP1PDLL 180 260 345 ns 1), low line use case

tCSOCP1PDHL 120 185 250 ns 1), high line use case

tCSOCP1PD 100 130 165 ns 1), dVCS/dt=100 V/µs

CS OCP1 threshold steps ∆VCSOCP1 — 2.371 — mV

CS OCP1 threshold

accuracy ∆VCSOCP1THR -25 — 25 mV 1)

Leading edge blanking time tCSLEB 255 269 284 ns 1), 2), 3)

CS OCP1 maximum CS limit VCSmaxLL 560 594 631 mV 1), 2), low line use case

VCSmaxHL 325 392 456 mV 1), 2), high line use case

Tolerance for CS OCP1

maximum CS FASTOPP

limit

∆VCSFASTOPPLL -50 — 50 mV 1),low line use case

∆VCSFASTOPPHL -60 — 60 mV 1), high line use case

CS limit at setpoint B VCSBLL 408 443 479 mV 1), 2),low line use case

VCSBHL 299 366 430 mV 1), 2),high line use case

CS limit at setpoint C VCSCLL 408 443 479 mV 1), 2),low line use case

VCSCHL 299 366 430 mV 1), 2),high line use case

Minimum CS limit at burst

mode entry

VCSminLL 57 92 128 mV 1), 2),low line use case

VCSminHL 0 15 79 mV 1), 2),high line use case

Burst sequence:

1st pulse CS limit

VCSBSP1LL — 120 — mV 1), 2),low line use case

VCSBSP1HL — 43 — mV 1), 2),high line use case

Burst sequence:

2nd pulse CS limit VCSBSP2LL — 120 — mV 1), 2),low line use case


Burst sequence:

3rd pulse CS limit VCSBSP3LL — 120 — mV 1), 2),low line use case


Maximum CS limit during

burst mode operation VCSBSP4LL 120 mV 1), 2), low line use case

4th and consecutive


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pulses after start of

burst sequence

VCSBSP4HL 43 mV 1), 2), high line use case

4th and consecutive

pulses after start of

burst sequence

CS limit for 1st pulse

directly after BM exit

VCSBMEXLL 92 mV 1), 2),low line use case

VCSBMEXHL 15 mV 1), 2),high line use case

Initial soft-start CS limit

limitation without PDC

VCSSSLL 45 — 110 mV 1), 2),low line use case

VCSSSHL 70 — 155 mV 1), 2),high line use case

Soft-start step for cycle by

cycle limitation

∆VCSS — 2.5 — mV 1), 2),step every t VCSS

1) Not tested in production test. 2) See configuration Chapter 5. 3) Min. and max. values are based on master clock period tMCLK limits (see Table 19).

Table 18 Electrical Characteristics of GDx pin

Parameter

Symbol

Values Unit

Note/Test Condition

Min. Typ. Max.

Low state sink peak current IGDxLPKSNK 500 — — mA 1), VGDx=4 V,

CLoad=2 nF

Low state resistance RGDxLSNK — — 6.5 Ω

High state peak source

current of GD1 -IGD1HPKSRC 100 118 136 mA 2), 3), CLoad=2 nF

High state peak source

current of GD0 -IGD0HPKSRC 30 35 41 mA 2), 3), CLoad=2 nF

High state output voltage VGDxH 9.97 10.5 11.03 V 3), IGDx=-1 mA

High state rail-to-rail output

voltage VGDxHRR VVCC-0.5 — VVCC V VVCC<VGDxH

APD low voltage

(active pull down while

device is not powered or

gate driver is not enabled)

VGDxAPD — — 1.6 V IGDx=5 mA

Permanent pull-down

resistor inside gate driver RGDxPPD 450 600 750 kΩ

1) Not tested in production test.

2) Currents flowing out of the device (DUT) are marked with a negative sign in the ‘Symbol’ column.

3) See configuration Chapter 5.

Table 19 Electrical Characteristics of IC Control

Parameter Symbol Values Unit Note/Test Condition


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Min. Typ. Max.

VREF internal voltage reference VREF 2.397 2.428 2.459 V

Time base 1 tBase1 49.50 52.1 54.78 µs 1)

Time base 2 tBase2 99.0 104.28 109.56 µs 1)

Master clock period tMCLK 15.0 15.8 16.6 ns 2)

Stand-by clock period tSTBCLK 9.09 10.0 11.11 µs 3)

Maximum soft-start time tSSmax 6.64 7.0 7.36 ms 1)

Boot sequence time when

activating IC

tBootIC — 1.2 — ms 1),4), VVCC>VVCCon

Maximum frequency

operation fSWmax 132.6 139.4 146.9 kHz 1)

Switching frequency

setting at minimum power

operation point

fSWmin 23.6 24.9 26.3 kHz 1)

Burst sequence:

1st pulse switching

frequency

fSWBSP1 — 50.2 — kHz 1)

Burst sequence:

2nd pulse switching

frequency

fSWBSP2 — 50.2 — kHz 1)

Burst sequence:

3rd pulse switching

frequency

fSWBSP3 — 50.2 — kHz 1)

Burst sequence:

4th and consecutive pulse

switching frequency

fSWBSP4 — 50.2 — kHz 1)

Switching frequency 1st

pulse directly after BM exit fSWBMEXHV 132.6 139.4 146.9 kHz 1)

1) Not tested in production test. 2) The master clock period is the base for all time measurements without stand-by. Relative tolerances of all performed time

measurements are same as with tMCLK. 3) The stand-by clock is the base for all time related characteristics during stand-by operation. 4) Phase for loading the OTP content to the internal RAM

Table 20 Electrical Characteristics of IC Protection Features

Parameter

Symbol

Values Unit

Note/Test Condition

Min. Typ. Max.

Auto-restart bang-bang mode

off-time tBBoffAR 455 500 556 ms 1),2)

Auto-restart time tAR 2.73 3 — s 1),2)

Blanking time of open-loop

timer tMFIOH 29.7 31.3 33 ms 1),3)

VMFIO>VMFIOOLP


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Over-temperature detection TJOTP 122 130 - °C 1),4)

Over-temperature blanking

time

tJOTP 9.90 10.50 11.10 ms 1),3)

Over-temperature

Hysteresis

TJHYS_OTP - 20 - °C 1)

1) Not tested in production test. 2) Min. and max. values are based on stand-by clock period tSTBCLK limits (see Table 20). 3) Min. and max. values are based on master clock period tMCLK (see Table 20). 4) The recommended temp is below 125 ˚C , above this temperature, IC function cannot be guaranteed, Customer should

guarantee the design will never exceed the 125 ˚C of IC die temperature.


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Package Information

7 Package Information The package information contains the outline dimensions (see Chapter 7.1); footprint and packing overviews (see Chapter

7.2).

Notes

1. You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”:

http://www.infineon.com/products.

2. Dimensions in mm.

7.1 Outline dimensions

Figure 32 PG-DSO-12-20 Package Outline


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Package Information

7.2 Footprint and packing

Figure 33 Overview footprint

Figure 34 Overview packing


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Marking

8 Marking

Figure 35 Marking of XDPS21071


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Appendix

9 Appendix This appendix contains additional information on electrical characteristics and specific test conditions.

9.1 Minimum required capacitive load at GD0 and GD1 pin

The output stage of GD0 and GD1 consist of a controlled current source (see 4.2.7). This current source charges up an external

capacitive load until the voltage level VGDxH = 10.5 V is reached. The internal control loop for this source current requires a

minimum load capacitance at GDx pin to avoid a turn-on ringing on the signal VGDx.

The minimum required capacitive load is depending on the dimensioned serial gate resistor at GDx pin, which is meant for

limiting the low state sink current.

Furthermore, the required load is depending on the configured source current. The shown dependency in Figure 36 is based

on the typical source current of –IGDxHPKSRC=118mA. Lower configured values for the source current requires also smaller

capactive loads.

Figure 36 Minimum required capacitive load at GDx pin in correlation with serial gate resistor


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References

10 References The following list shows the reference documents that are used as base for this data sheet.

[1] Development firmware version: REV 1.0


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Revision history

Revision history

Major changes since the last revision

Page or Reference Description of change

16/Aug/2019 Draft 0.9 release

Published by

Infineon Technologies AG

81726 München, Germany

© 2019 Infineon Technologies AG.

All Rights Reserved.

Do you have a question about this

document?

Email: [email protected]

Document reference

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Edition 2019-10-30

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