Foto1: Perangkat SMS Center

A1

Foto1: Perangkat SMS Center

Foto2: Perangkat Seven Segment

A2

Gambar1 : konfigurasi kabel downloader

B1

.include"C:\Program Files\Atmel\AVR Tools\AvrAssembler\Appnotes\m16defnor.inc"

.def txbyte = r17

.def rxbyte = r18

.equ SRAM = 0x0060

.def data = r23

.def teg = r24

.def tmmcbyte = r21

.def rmmcbyte = r22

.equ a = 0b01000001

.equ b = 0b00110001

.equ c = 0b01110011

.equ satu = 0b11101101

.equ dua = 0b01000011

.equ tiga = 0b01001001

.equ empat = 0b00101101

.equ lima = 0b00011001

.equ enam = 0b00010001

.equ tujuh = 0b11001101

.equ lapan = 0b00000001

.equ bilan = 0b00001001

.equ nol = 0b10000001

.org 0x0000 rjmp main

main: ldi r16, low(ramend) out spl, r16 ldi r16, high(ramend) out sph, r16

ldi r16,0xFF out ddra, r16 out ddrc,r16

clear: ldi r16, 0x00 ldi r23, 0x00 ldi Xl, low(0x0200) ldi Xh, high(0x0200) clir: st X+, r16 inc r23 cpi r23,0x8F breq main2 rcall clir

main2: rcall init_usart rcall spi_init rcall mmc_init ldi r25,0x00 rcall timer1d rcall kirim_CNMI

B2

tunggu_SMS: rcall usart_rx cpi rxbyte,$31 breq read rjmp tunggu_SMS

read: rcall kirim_CMGR

skip_cmgr1: rcall usart_rx cpi rxbyte,$30 breq skip_cmgr2 rjmp skip_cmgr1 skip_cmgr2: rcall usart_rx cpi rxbyte,$30 breq Simpan_1 rjmp skip_cmgr2

simpan_1:

ldi r16,0 ldi Xl, low(SRAM) ldi Xh, high(SRAM) simpan1: rcall usart_rx st X+, rxbyte cpi r16,0x40 breq pisahkannomer inc r16 rjmp simpan1

pisahkannomer: ldi r16, 0x00 ldi Xl, low(0x0100) ldi Xh, high(0x0100) ldi Yl, low(0x0071) ldi Yh, high(0x0071) pisah: ld r19, Y+ st X+, r19 cpi r16, 0x0F breq simpannommc1 inc r16 rcall pisah simpannommc1: rjmp simpannommc cek_poling: rcall timer1d ldi r16, 0x00 rcall kirim_cmgd ldi Xl, low(0x0093) ldi Xh, high(0x0093) ldi zl, low(2*datasms) ldi zh, high(2*datasms)

B3

loopcek: lpm ld r19, X+ cp r0, r19 brne cek_nomer cpi r16, 0x05 breq kirimtanya inc zl inc r16 rjmp loopcek kirimtanya: rjmp kirimtanya1

cek_nomer: ldi r16, 0x00 ldi Xl, low(0x0100) ldi Xh, high(0x0100) ldi Yl, low(0x0071) ldi Yh, high(0x0071) ceknomer: ld r19, Y+ ld r20, X+ cp r20, r19 brne tunggu cpi r16, 0x0F breq ceknotanya inc r16 rcall ceknomer tunggu: rjmp tunggu_SMS

ceknotanya: ldi Xl, low(0x009E) ldi Xh, high(0x009E) loopcekjwb1: ld r16,X cpi r16,$43 breq jwbtanya1 cpi r16,$34 breq jwbtanya2 rjmp tunggu_SMS

;=================== ;jawaban pertanyaan 1 ;=================== jwbtanya1: ldi Xl, low(0x00A0) ldi Xh, high(0x00A0) ld r16,X cpi r16,$35 breq jawaban_1A cpi r16,$39 breq jawaban_1B cpi r16,$44 breq jawaban_1C rjmp tunggu_SMS

B4

jawaban_1A: ldi Xl, low(0x0200) ldi Xh, high(0x0200) ld r16, X inc r16 st X, r16 rcall kirimtanya2 rjmp tunggu_SMS jawaban_1B: ldi Xl, low(0x0202) ldi Xh, high(0x0202) ld r16, X inc r16 st X, r16 rcall kirimtanya2 rjmp tunggu_SMS jawaban_1C: ldi Xl, low(0x0204) ldi Xh, high(0x0204) ld r16, X inc r16 st X, r16 rcall kirimtanya2 rjmp tunggu_SMS

;==================== ;jawaban pertanyaan 2 ;==================== jwbtanya2: ldi Xl, low(0x0200) ldi Xh, high(0x0200) ld r16,X cpi r16,$35 breq jawaban_2A cpi r16,$39 breq jawaban_2B cpi r16,$44 breq jawaban_2C rjmp tunggu_SMS

jawaban_2A: ldi Xl, low(0x0206) ldi Xh, high(0x0206) ld r16, X inc r16 st X, r16 rcall kirimmakasih rjmp tunggu_SMS jawaban_2B: ldi Xl, low(0x0208) ldi Xh, high(0x0208) ld r16, X inc r16 st X, r16 rcall kirimmakasih

B5

rjmp tunggu_SMS jawaban_2C: ldi Xl, low(0x020A) ldi Xh, high(0x020A) ld r16, X inc r16 st X, r16 rcall kirimmakasih rjmp tunggu_SMS

;=================== ;kirim pertanyaan 1 ;=================== kirimtanya1: ldi Xl, low(0x020C) ldi Xh, high(0x020C) ld r16, X cpi r16,0x01 breq tunggu_SMS1 inc r16 st X, r16 tunggu_SMS1: rjmp tunggu_SMS

rcall timer1d simpannommc: rcall cmd24 rcall tulis

rcall kirim_cmgs

tunggu1: rcall usart_rx cpi rxbyte,$3E breq kirimheadanno1 rjmp tunggu1

kirimheadanno1: rcall kirimheader

kirim_pertanyaan: ldi zl, low(2*datapertanyaan1) ldi zh, high(2*datapertanyaan1) loop_kirimpertanyaan: lpm mov txbyte,r0 cpi txbyte,0 breq cntrlZ1 rcall usart_tx inc zl rjmp loop_kirimpertanyaan

cntrlZ1: rcall cntrl_z rjmp tunggu_SMS

B6

;================= ;kirim pertanyaan 2 ;================= kirimtanya2: rcall timer1d rcall kirim_cmgs



kirim_tanya2: ldi zl, low(2*datapertanyaan2) ldi zh, high(2*datapertanyaan2) loop_kirimatanya2: lpm mov txbyte,r0 cpi txbyte,0 breq cntrlZ2 rcall usart_tx inc zl rjmp loop_kirimatanya2 cntrlZ2: rcall cntrl_z inc r25 rcall tampildata1 rjmp tunggu_SMS

;================= ;kirim terimakasih ;================= kirimmakasih: ldi Xl, low(0x020C) ldi Xh, high(0x020C) ld r16, X dec r16 st X, r16 rcall timer1d rcall kirim_cmgs



kirim_makasih: ldi zl, low(2*makasih)

B7

ldi zh, high(2*makasih) loop_kirimakasih: lpm mov txbyte,r0 cpi txbyte,0 breq cntrlZ3 rcall usart_tx inc zl rjmp loop_kirimakasih cntrlZ3: rcall cntrl_z rcall tampildata2 rjmp tunggu_SMS

;======================= ;kirim header dan nomer ;======================= kirimheader: rcall timer1d ldi zl, low(2*headerkirim) ldi zh, high(2*headerkirim) loop_header: lpm mov txbyte,r0 cpi txbyte,0 breq kirim_nomer rcall usart_tx inc zl rjmp loop_header

kirim_nomer: rcall cmd17 rcall baca ldi r16, 0x00 ldi Xl, low(0x0100) ldi Xh, high(0x0100) loop_kirimnomer: ld txbyte, X+ rcall usart_tx cpi r16,0x0F breq endheadno inc r16 rjmp loop_kirimnomer endheadno: ret

;======================= ;kirim at+cnmi=1,1,0,1,1 ;======================= kirim_CNMI: ldi zl, low(2*CNMI) ldi zh, high(2*CNMI) load_CNMI: lpm mov txbyte,r0

B8

cpi txbyte,0 breq tunggueror rcall usart_tx inc zl rjmp load_CNMI tunggueror: rcall usart_rx cpi rxbyte,$52 breq endcnmi rjmp tunggueror endcnmi: ret

;============= ;kirim at+cmgd ;============= kirim_cmgd: rcall timer1d rcall timer1d rcall timer1d ldi zl, low(2*cmgd) ldi zh, high(2*cmgd) loop_cmgd: lpm mov txbyte,r0 cpi txbyte,0 breq tunggu_ok rcall usart_tx inc zl rjmp loop_cmgd tunggu_ok: rcall usart_rx cpi rxbyte,$4B breq enddel rjmp tunggu_ok enddel: ret

;=============== ;kirim at+cmgr=1 ;=============== kirim_CMGR: ldi zl, low(2*CMGR) ldi zh, high(2*CMGR) load_CMGR: lpm mov txbyte,r0 cpi txbyte,0 breq endcmgr rcall usart_tx inc zl rjmp load_CMGR endcmgr: ret

B9

;================= ;kirim at+cmgs=77 ;================= kirim_cmgs: ldi zl, low(2*cmgs) ldi zh, high(2*cmgs) loop_cmgs: lpm mov txbyte,r0 cpi txbyte,0 breq endcmgs rcall usart_tx inc zl rjmp loop_cmgs endcmgs: ret

;============= ;kirim cntrl Z ;============= cntrl_Z: ldi txbyte,$1A rcall usart_tx tungguok: rcall usart_rx cpi rxbyte,$4B breq endz rjmp tungguok endz: ret

tampildata1: ldi r19,0x0F rcall data1a ldi r16,0xff out portc,r16 rcall timer1d ldi r19,0x0F rcall data1b ldi r16,0xff out portc,r16 rcall timer1d ldi r19,0x0F rcall data1c ldi r16,0xff out portc,r16 rcall timer1d ret

tampildata2: ldi r19,0x0F rcall data2a ldi r16,0xff out portc,r16 rcall timer1d ldi r19,0x0F

B10

rcall data2b ldi r16,0xff out portc,r16 rcall timer1d ldi r19,0x0F rcall data2c ldi r16,0xff out portc,r16 rcall timer1d ret

;======================= ;tampilkan data poling 1 ;======================= data1a: dec r19 cpi r19,0x00 breq return1a ldi r20,0xFF loop1a: dec r20 ldi Xl, low(0x0200) ldi Xh, high(0x0200) ld r16, X ldi teg,0x10 ldi data,satu rcall display ldi teg,0x08 ldi data,a rcall display ldi teg, 0x04 ldi data, nol rcall display ldi teg, 0x02 ldi data, nol rcall display rcall banding00x cpi r20,0x00 breq data1a rjmp loop1a return1a: ret

data1b: dec r19 cpi r19,0x00 breq return1b ldi r20,0xFF loop1b: dec r20 ldi Xl, low(0x0202) ldi Xh, high(0x0202) ld r16, X ldi teg,0x10 ldi data,satu rcall display ldi teg,0x08

B11

ldi data,b rcall display ldi teg, 0x04 ldi data, nol rcall display ldi teg, 0x02 ldi data, nol rcall display rcall banding00x cpi r20,0x00 breq data1b rjmp loop1b return1b: ret

data1c: dec r19 cpi r19,0x00 breq return1c ldi r20,0xFF loop1c: dec r20 ldi Xl, low(0x0204) ldi Xh, high(0x0204) ld r16, X ldi teg,0x10 ldi data,satu rcall display ldi teg,0x08 ldi data,c rcall display ldi teg, 0x04 ldi data, nol rcall display ldi teg, 0x02 ldi data, nol rcall display rcall banding00x cpi r20,0x00 breq data1c rjmp loop1c return1c: ret

;======================= ;tampilkan data poling ;======================= data2a: dec r19 cpi r19,0x00 breq return2a ldi r20,0xFF loop2a: dec r20 ldi Xl, low(0x0206) ldi Xh, high(0x0206) ld r16, X ldi teg,0x10

B12

ldi data,dua rcall display ldi teg,0x08 ldi data,a rcall display ldi teg, 0x04 ldi data, nol rcall display ldi teg, 0x02 ldi data, nol rcall display rcall banding00x cpi r20,0x00 breq data2a rjmp loop2a return2a: ret

data2b: dec r19 cpi r19,0x00 breq return2b ldi r20,0xFF loop2b: dec r20 ldi Xl, low(0x0208) ldi Xh, high(0x0208) ld r16, X ldi teg,0x10 ldi data,dua rcall display ldi teg,0x08 ldi data,b rcall display ldi teg, 0x04 ldi data, nol rcall display ldi teg, 0x02 ldi data, nol rcall display rcall banding00x cpi r20,0x00 breq data2b rjmp loop2b return2b: ret

data2c: dec r19 cpi r19,0x00 breq return2c ldi r20,0xFF loop2c: dec r20 ldi Xl, low(0x020A) ldi Xh, high(0x020A) ld r16, X ldi teg,0x10

B13

ldi data,dua rcall display ldi teg,0x08 ldi data,c rcall display ldi teg, 0x04 ldi data, nol rcall display ldi teg, 0x02 ldi data, nol rcall display rcall banding00x cpi r20,0x00 breq data2c rjmp loop2c return2c: ret

;================ ;bandingkan hasil ;================ banding00x: ldi teg, 0x01 andi r16,0x0F ldi data, nol cpi r16,0 breq display ldi data, satu cpi r16,1 breq display ldi data, dua cpi r16,2 breq display ldi data, tiga cpi r16,3 breq display ldi data, empat cpi r16,4 breq display ldi data, lima cpi r16,5 breq display ldi data, enam cpi r16,6 breq display ldi data, tujuh cpi r16,7 breq display ldi data, lapan cpi r16,8 breq display ldi data, bilan cpi r16,9 breq display ret

B14

display: out PORTA,teg out PORTC,data rcall timer ret

;================ ;inisialisasi SPI ;================ spi_init: cbi PortB,6 sbi PortB,5 sbi PortB,7 sbi PortB,4 ldi r16, 0b01010011 out spcr,r16 cbi PortB,4 ret

;=========== ;kirim CMD0 ;=========== cmd0: ldi tmmcbyte,0xFF rcall transmmc ldi tmmcbyte,0x40 rcall transmmc ldi tmmcbyte,0x00 rcall transmmc rcall transmmc ldi tmmcbyte,0x95 rcall transmmc cpi rmmcbyte,0x01 breq kembalimmc1 rjmp cmd0 kembalimmc1: ret

;=========== ;kirim CMD24 ;=========== cmd24: ldi tmmcbyte,0xFF rcall transmmc ldi tmmcbyte,0x58 rcall transmmc mov tmmcbyte,r25 rcall transmmc ldi tmmcbyte, high(0x200) rcall transmmc ldi tmmcbyte, low(0x200) rcall transmmc ldi tmmcbyte,0xFF rcall transmmc cpi rmmcbyte,0x00 breq kembalimmc2 rjmp cmd24

B15

kembalimmc2: ret

;=========== ;kirim CMD17 ;=========== cmd17: ldi tmmcbyte,0xFF rcall transmmc ldi tmmcbyte,0x51 rcall transmmc mov tmmcbyte,r25 rcall transmmc di tmmcbyte, high(0x200) rcall transmmc ldi tmmcbyte, low(0x200) rcall transmmc ldi tmmcbyte,0xFF rcall transmmc cpi rmmcbyte,0x01 breq kembalimmc3 rjmp cmd17 kembalimmc3: ret

;============ ;MMC initial ;============ mmc_init: sbi portb,4 ldi r16, 0 dummy: inc r16 ldi tmmcbyte,0xFF rcall transmmc cpi r16,80 brne dummy rcall cmd0 ret

transmmc: out spdr,tmmcbyte sbis spsr,spif rjmp transmmc in rmmcbyte,spdr ret

;========== ;tulis mmc ;========== tulis: ldi xl,low(0x100) ldi xh,high(0x100) ldi r16,0 ldi tmmcbyte,0xFF rcall transmmc rcall transmmc ldi tmmcbyte, 0xFE

B16

rcall transmmc loopwrite: ld tmmcbyte,X+ rcall transmmc inc r16 cpi r16,0x0F brne loopwrite ldi tmmcbyte,0xFF rcall transmmc rcall transmmc mov r16,rmmcbyte andi r16,0x1F cpi r16,0x05 breq tulis ret

;========= ;baca mmc ;========= baca: ldi tmmcbyte, 0xFF rcall transmmc cpi rmmcbyte, 0xFE brne baca ldi xl,low(0x100) ldi xh,high(0x100) ldi r16,0 loopbaca: sbis ucsra,udre rjmp loopbaca ldi tmmcbyte, 0xFF rcall transmmc st x+,rmmcbyte inc r16 cpi r16,0x0F breq slesaibaca rjmp loopbaca slesaibaca: ldi tmmcbyte,0xFF rcall transmmc rcall transmmc ret

;================== ;inisialisasi USART ;================== init_usart: ldi r16, 0x00 out UBRRH, r16 ldi r16, 0x23 out UBRRL,r16 ldi r16, 0xD8 out UCSRB, r16 ldi r16, 0x86 out UCSRC, r16 ret

B17

;============== ;transmit data ;============== usart_tx: sbis UCSRA,UDRE rjmp usart_tx out UDR,txbyte ret

;============ ;receive data ;============ usart_rx: sbis UCSRA,RXC rjmp usart_rx in rxbyte, UDR ret

;====== ;Timer ;====== timer1d: ldi r16, 0b00000100 out TIMSK, r16 ldi r16, high(0xD5D0) out TCNT1H, r16 ldi r16, low(0xD5D0) out TCNT1L, r16 ldi r16, 0b00000101 out TCCR1B, r16 looptimer: in r19, TIFR sbrs r19, TOV1 rjmp looptimer

ldi r16, 0b00000100 out TIFR, r16 ret

timer: ldi r16, 0b00000100 out TIMSK, r16 ldi r16, high(0xFFFF) out TCNT1H, r16 ldi r16, low(0xFFFF) out TCNT1L, r16 ldi r16, 0b00000101 out TCCR1B, r16 looptimer2: in r19, TIFR sbrs r19, TOV1 rjmp looptimer2 ldi r16, 0b00000100 out TIFR, r16 ret

B18

datasms: .db "07D0279399741E01",0 ;POLLING headerkirim: .db "07912618485400F91100",0 datapertanyaan1: .db

"00000047D3F49C5E6E83E065F93DCC4E87DDA069900A0AAFC36E90B82C5787D9613748 1C4EAF5DA0A06B5EA6D7D57590D0250F9FEBA0A18B9E2687D7A079995E57D701",0 datapertanyaan2: .db

"00000047D32015D42EB7C565797A1D7683E66F767D9E0691C3EC701B042FCBEF61763AE C76814041D7BC4CAFABEB20A14B1E3ED74143173D4D0EAF41F332BDAEAE8300",0 makasih: .db "00000048D4B23CDD0EAFC3F3341A14A687E72078584E4FCFD3F0F03C0D0ABBC96117881CA687 416137390C0AAFC36ED0BC7C2ECBC320721A2E7FCFCB7317284C6EA7DD",0 CNMI: .db "at+cnmi=1,1,0,1,1",13,10,0 CMGR: .db "at+cmgr=1",13,10,0 cmgs: .db "at+cmgs=77",13,10,0 cmgd: .db "at+cmgd=1",13,10,0

8-bit Microcontroller with 16K Bytes In-SystemProgrammable Flash

ATmega16ATmega16L

Preliminary

Rev. 2466E–AVR–10/02

Features• High-performance, Low-power AVR® 8-bit Microcontroller• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution– 32 x 8 General Purpose Working Registers– Fully Static Operation– Up to 16 MIPS Throughput at 16 MHz– On-chip 2-cycle Multiplier

• Nonvolatile Program and Data Memories– 16K Bytes of In-System Self-Programmable Flash

Endurance: 10,000 Write/Erase Cycles– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot ProgramTrue Read-While-Write Operation

– 512 Bytes EEPROMEndurance: 100,000 Write/Erase Cycles

– 1K Byte Internal SRAM– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface– Boundary-scan Capabilities According to the JTAG Standard– Extensive On-chip Debug Support– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode– Real Time Counter with Separate Oscillator– Four PWM Channels– 8-channel, 10-bit ADC

8 Single-ended Channels7 Differential Channels in TQFP Package Only2 Differential Channels with Programmable Gain at 1x, 10x, or 200x

– Byte-oriented Two-wire Serial Interface– Programmable Serial USART– Master/Slave SPI Serial Interface– Programmable Watchdog Timer with Separate On-chip Oscillator– On-chip Analog Comparator

• Special Microcontroller Features– Power-on Reset and Programmable Brown-out Detection– Internal Calibrated RC Oscillator– External and Internal Interrupt Sources– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby

and Extended Standby• I/O and Packages

– 32 Programmable I/O Lines– 40-pin PDIP, 44-lead TQFP, and 44-pad MLF

• Operating Voltages– 2.7 - 5.5V for ATmega16L– 4.5 - 5.5V for ATmega16

• Speed Grades– 0 - 8 MHz for ATmega16L– 0 - 16 MHz for ATmega16

1

Pin Configurations Figure 1. Pinouts ATmega16

Disclaimer Typical values contained in this data sheet are based on simulations and characteriza-tion of other AVR microcontrollers manufactured on the same process technology. Minand Max values will be available after the device is characterized.

(XCK/T0) PB0(T1) PB1

(INT2/AIN0) PB2(OC0/AIN1) PB3

(SS) PB4(MOSI) PB5(MISO) PB6(SCK) PB7

RESETVCCGND

XTAL2XTAL1

(RXD) PD0(TXD) PD1(INT0) PD2(INT1) PD3(OC1B) PD4(OC1A) PD5(ICP) PD6

PA0 (ADC0)PA1 (ADC1)PA2 (ADC2)PA3 (ADC3)PA4 (ADC4)PA5 (ADC5)PA6 (ADC6)PA7 (ADC7)AREFGNDAVCCPC7 (TOSC2)PC6 (TOSC1)PC5 (TDI)PC4 (TDO)PC3 (TMS)PC2 (TCK)PC1 (SDA)PC0 (SCL)PD7 (OC2)

PA4 (ADC4)PA5 (ADC5)PA6 (ADC6)PA7 (ADC7)AREFGNDAVCCPC7 (TOSC2)PC6 (TOSC1)PC5 (TDI)PC4 (TDO)

(MOSI) PB5(MISO) PB6(SCK) PB7

RESETVCCGND

XTAL2XTAL1

(RXD) PD0(TXD) PD1(INT0) PD2

(INT1) PD3

(OC1B) PD4

(OC1A) PD5

(ICP) PD6

(OC2) PD7

VCC

GND

(SCL) PC0

(SDA) PC1

(TCK) PC2

(TMS) PC3

PB4 (SS)

PB3 (AIN1/OC0)

PB2 (AIN0/INT2)

PB1 (T1)

PB0 (XCK/T0)

GND

VCC

PA0 (ADC0)

PA1 (ADC1)

PA2 (ADC2)

PA3 (ADC3)

PDIP

TQFP/MLF

2 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Overview The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhancedRISC architecture. By executing powerful instructions in a single clock cycle, theATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the systemdesigner to optimize power consumption versus processing speed.

Block Diagram Figure 2. Block Diagram

INTERNALOSCILLATOR

OSCILLATOR

WATCHDOGTIMER

MCU CTRL.& TIMING

OSCILLATOR

TIMERS/COUNTERS

INTERRUPTUNIT

STACKPOINTER

EEPROM

SRAM

STATUSREGISTER

USART

PROGRAMCOUNTER

PROGRAMFLASH

INSTRUCTIONREGISTER

INSTRUCTIONDECODER

PROGRAMMINGLOGIC SPI

ADCINTERFACE

COMP.INTERFACE

PORTA DRIVERS/BUFFERS

PORTA DIGITAL INTERFACE

GENERALPURPOSE

REGISTERS

X

Y

Z

ALU

+-

PORTC DRIVERS/BUFFERS

PORTC DIGITAL INTERFACE

PORTB DIGITAL INTERFACE

PORTB DRIVERS/BUFFERS

PORTD DIGITAL INTERFACE

PORTD DRIVERS/BUFFERS

XTAL1

XTAL2

RESET

CONTROLLINES

VCC

GND

MUX &ADC

AREF

PA0 - PA7 PC0 - PC7

PD0 - PD7PB0 - PB7

AVR CPU

TWI

AVCC

INTERNALCALIBRATEDOSCILLATOR

32466E–AVR–10/02

The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowingtwo independent registers to be accessed in one single instruction executed in one clockcycle. The resulting architecture is more code efficient while achieving throughputs up toten times faster than conventional CISC microcontrollers.

The ATmega16 provides the following features: 16K bytes of In-System ProgrammableFlash Program memory with Read-While-Write capabilities, 512 bytes EEPROM, 1Kbyte SRAM, 32 general purpose I/O lines, 32 general purpose working registers, aJTAG interface for Boundary-scan, On-chip Debugging support and programming, threeflexible Timer/Counters with compare modes, Internal and External Interrupts, a serialprogrammable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bitADC with optional differential input stage with programmable gain (TQFP package only),a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and sixsoftware selectable power saving modes. The Idle mode stops the CPU while allowingthe USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, andinterrupt system to continue functioning. The Power-down mode saves the register con-tents but freezes the Oscillator, disabling all other chip functions until the next ExternalInterrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continuesto run, allowing the user to maintain a timer base while the rest of the device is sleeping.The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchro-nous Timer and ADC, to minimize switching noise during ADC conversions. In Standbymode, the crystal/resonator Oscillator is running while the rest of the device is sleeping.This allows very fast start-up combined with low-power consumption. In ExtendedStandby mode, both the main Oscillator and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high density nonvolatile memory technology.The On-chip ISP Flash allows the program memory to be reprogrammed in-systemthrough an SPI serial interface, by a conventional nonvolatile memory programmer, orby an On-chip Boot program running on the AVR core. The boot program can use anyinterface to download the application program in the Application Flash memory. Soft-ware in the Boot Flash section will continue to run while the Application Flash section isupdated, providing true Read-While-Write operation. By combining an 8-bit RISC CPUwith In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16 isa powerful microcontroller that provides a highly-flexible and cost-effective solution tomany embedded control applications.

The ATmega16 AVR is supported with a full suite of program and system developmenttools including: C compilers, macro assemblers, program debugger/simulators, in-circuitemulators, and evaluation kits.

Pin Descriptions

VCC Digital supply voltage.

GND Ground.

Port A (PA7..PA0) Port A serves as the analog inputs to the A/D Converter.

Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.Port pins can provide internal pull-up resistors (selected for each bit). The Port A outputbuffers have symmetrical drive characteristics with both high sink and source capability.When pins PA0 to PA7 are used as inputs and are externally pulled low, they will sourcecurrent if the internal pull-up resistors are activated. The Port A pins are tri-stated whena reset condition becomes active, even if the clock is not running.

4 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port B output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port B pins that are externally pulled low will sourcecurrent if the pull-up resistors are activated. The Port B pins are tri-stated when a resetcondition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega16 as listedon page 55.

Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port C output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port C pins that are externally pulled low will sourcecurrent if the pull-up resistors are activated. The Port C pins are tri-stated when a resetcondition becomes active, even if the clock is not running. If the JTAG interface isenabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be acti-vated even if a reset occurs.

Port C also serves the functions of the JTAG interface and other special features of theATmega16 as listed on page 58.

Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port D output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port D pins that are externally pulled low will sourcecurrent if the pull-up resistors are activated. The Port D pins are tri-stated when a resetcondition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega16 as listedon page 60.

RESET Reset Input. A low level on this pin for longer than the minimum pulse length will gener-ate a reset, even if the clock is not running. The minimum pulse length is given in Table15 on page 35. Shorter pulses are not guaranteed to generate a reset.

XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting Oscillator amplifier.

AVCC AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externallyconnected to VCC, even if the ADC is not used. If the ADC is used, it should be con-nected to VCC through a low-pass filter.

AREF AREF is the analog reference pin for the A/D Converter.

About Code Examples

This documentation contains simple code examples that briefly show how to use variousparts of the device. These code examples assume that the part specific header file isincluded before compilation. Be aware that not all C Compiler vendors include bit defini-tions in the header files and interrupt handling in C is compiler dependent. Pleaseconfirm with the C Compiler documentation for more details.

52466E–AVR–10/02

AVR CPU Core

Introduction This section discusses the AVR core architecture in general. The main function of theCPU core is to ensure correct program execution. The CPU must therefore be able toaccess memories, perform calculations, control peripherals, and handle interrupts.

Architectural Overview Figure 3. Block Diagram of the AVR MCU Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture– with separate memories and buses for program and data. Instructions in the programmemory are executed with a single level pipelining. While one instruction is being exe-cuted, the next instruction is pre-fetched from the program memory. This conceptenables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

The fast-access Register file contains 32 x 8-bit general purpose working registers witha single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)operation. In a typical ALU operation, two operands are output from the Register file, theoperation is executed, and the result is stored back in the Register file – in one clockcycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers forData Space addressing – enabling efficient address calculations. One of the theseaddress pointers can also be used as an address pointer for look up tables in Flash Pro-gram memory. These added function registers are the 16-bit X-, Y-, and Z-register,described later in this section.

The ALU supports arithmetic and logic operations between registers or between a con-stant and a register. Single register operations can also be executed in the ALU. After

FlashProgramMemory

InstructionRegister

InstructionDecoder

ProgramCounter

Control Lines

32 x 8GeneralPurpose

Registrers

ALU

Statusand Control

I/O Lines

EEPROM

Data Bus 8-bit

DataSRAM

Direct

Addre

ssin

g

Indirect

Addre

ssin

g

InterruptUnit

SPIUnit

WatchdogTimer

AnalogComparator

I/O Module 2

I/O Module1

I/O Module n

6 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

an arithmetic operation, the Status Register is updated to reflect information about theresult of the operation.

Program flow is provided by conditional and unconditional jump and call instructions,able to directly address the whole address space. Most AVR instructions have a single16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot program section andthe Application Program section. Both sections have dedicated Lock bits for write andread/write protection. The SPM instruction that writes into the Application Flash memorysection must reside in the Boot Program section.

During interrupts and subroutine calls, the return address program counter (PC) isstored on the Stack. The Stack is effectively allocated in the general data SRAM, andconsequently the stack size is only limited by the total SRAM size and the usage of theSRAM. All user programs must initialize the SP in the reset routine (before subroutinesor interrupts are executed). The Stack Pointer SP is read/write accessible in the I/Ospace. The data SRAM can easily be accessed through the five different addressingmodes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additionalglobal interrupt enable bit in the Status Register. All interrupts have a separate interruptvector in the interrupt vector table. The interrupts have priority in accordance with theirinterrupt vector position. The lower the interrupt vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as ControlRegisters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or asthe Data Space locations following those of the Register file, $20 - $5F.

ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers. Within a single clock cycle, arithmetic operations betweengeneral purpose registers or between a register and an immediate are executed. TheALU operations are divided into three main categories – arithmetic, logical, and bit-func-tions. Some implementations of the architecture also provide a powerful multipliersupporting both signed/unsigned multiplication and fractional format. See the “Instruc-tion Set” section for a detailed description.

Status Register The Status Register contains information about the result of the most recently executedarithmetic instruction. This information can be used for altering program flow in order toperform conditional operations. Note that the Status Register is updated after all ALUoperations, as specified in the Instruction Set Reference. This will in many casesremove the need for using the dedicated compare instructions, resulting in faster andmore compact code.

The Status Register is not automatically stored when entering an interrupt routine andrestored when returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

Bit 7 6 5 4 3 2 1 0

I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

72466E–AVR–10/02

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individ-ual interrupt enable control is then performed in separate control registers. If the GlobalInterrupt Enable Register is cleared, none of the interrupts are enabled independent ofthe individual interrupt enable settings. The I-bit is cleared by hardware after an interrupthas occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, asdescribed in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source ordestination for the operated bit. A bit from a register in the Register file can be copiedinto T by the BST instruction, and a bit in T can be copied into a bit in a register in theRegister file by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a half carry in some arithmetic operations. Half Carry isuseful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the negative flag N and the two’s comple-ment overflow flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. Seethe “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. Seethe “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the“Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruc-tion Set Description” for detailed information.

General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order toachieve the required performance and flexibility, the following input/output schemes aresupported by the Register file:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 4 shows the structure of the 32 general purpose working registers in the CPU.

8 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 4. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers,and most of them are single cycle instructions.

As shown in Figure 4, each register is also assigned a data memory address, mappingthem directly into the first 32 locations of the user Data Space. Although not being phys-ically implemented as SRAM locations, this memory organization provides greatflexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set toindex any register in the file.

The X-register, Y-register and Z-register

The registers R26..R31 have some added functions to their general purpose usage.These registers are 16-bit address pointers for indirect addressing of the Data Space.The three indirect address registers X, Y, and Z are defined as described in Figure 5.

Figure 5. The X-, Y-, and Z-registers

In the different addressing modes these address registers have functions as fixed dis-placement, automatic increment, and automatic decrement (see the Instruction SetReference for details).

7 0 Addr.

R0 $00

R1 $01

R2 $02

…

R13 $0D

General R14 $0E

Purpose R15 $0F

Working R16 $10

Registers R17 $11

…

R26 $1A X-register Low Byte

R27 $1B X-register High Byte

R28 $1C Y-register Low Byte

R29 $1D Y-register High Byte

R30 $1E Z-register Low Byte

R31 $1F Z-register High Byte

15 XH XL 0

X - register 7 0 7 0

R27 ($1B) R26 ($1A)

15 YH YL 0

Y - register 7 0 7 0

R29 ($1D) R28 ($1C)

15 ZH ZL 0

Z - register 7 0 7 0

R31 ($1F) R30 ($1E)

92466E–AVR–10/02

Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and forstoring return addresses after interrupts and subroutine calls. The Stack Pointer Regis-ter always points to the top of the stack. Note that the stack is implemented as growingfrom higher memory locations to lower memory locations. This implies that a stackPUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM stack area where the Subroutine and Inter-rupt Stacks are located. This Stack space in the data SRAM must be defined by theprogram before any subroutine calls are executed or interrupts are enabled. The StackPointer must be set to point above $60. The Stack Pointer is decremented by one whendata is pushed onto the Stack with the PUSH instruction, and it is decremented by twowhen the return address is pushed onto the Stack with subroutine call or interrupt. TheStack Pointer is incremented by one when data is popped from the Stack with the POPinstruction, and it is incremented by two when data is popped from the Stack with returnfrom subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The num-ber of bits actually used is implementation dependent. Note that the data space in someimplementations of the AVR architecture is so small that only SPL is needed. In thiscase, the SPH Register will not be present.

Bit 15 14 13 12 11 10 9 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

7 6 5 4 3 2 1 0


R/W R/W R/W R/W R/W R/W R/W R/W


0 0 0 0 0 0 0 0

10 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. TheAVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clocksource for the chip. No internal clock division is used.

Figure 6 shows the parallel instruction fetches and instruction executions enabled by theHarvard architecture and the fast-access Register file concept. This is the basic pipelin-ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results forfunctions per cost, functions per clocks, and functions per power-unit.

Figure 6. The Parallel Instruction Fetches and Instruction Executions

Figure 7 shows the internal timing concept for the Register file. In a single clock cycle anALU operation using two register operands is executed, and the result is stored back tothe destination register.

Figure 7. Single Cycle ALU Operation

Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separatereset vector each have a separate program vector in the program memory space. Allinterrupts are assigned individual enable bits which must be written logic one togetherwith the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.Depending on the program counter value, interrupts may be automatically disabledwhen Boot Lock bits BLB02 or BLB12 are programmed. This feature improves softwaresecurity. See the section “Memory Programming” on page 254 for details.

The lowest addresses in the program memory space are by default defined as the Resetand Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 42.The list also determines the priority levels of the different interrupts. The lower theaddress the higher is the priority level. RESET has the highest priority, and next is INT0

clk

1st Instruction Fetch

1st Instruction Execute2nd Instruction Fetch

2nd Instruction Execute3rd Instruction Fetch

3rd Instruction Execute4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clkCPU

112466E–AVR–10/02

– the External Interrupt Request 0. The Interrupt Vectors can be moved to the start ofthe Boot Flash section by setting the IVSEL bit in the General Interrupt Control Register(GICR). Refer to “Interrupts” on page 42 for more information. The Reset Vector canalso be moved to the start of the boot Flash section by programming the BOOTRSTfuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 241.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interruptsare disabled. The user software can write logic one to the I-bit to enable nested inter-rupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit isautomatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event thatsets the interrupt flag. For these interrupts, the Program Counter is vectored to theactual Interrupt Vector in order to execute the interrupt handling routine, and hardwareclears the corresponding interrupt flag. Interrupt flags can also be cleared by writing alogic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while thecorresponding interrupt enable bit is cleared, the interrupt flag will be set and remem-bered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one ormore interrupt conditions occur while the Global Interrupt Enable bit is cleared, the cor-responding interrupt flag(s) will be set and remembered until the global interrupt enablebit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present.These interrupts do not necessarily have interrupt flags. If the interrupt condition disap-pears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and exe-cute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt rou-tine, nor restored when returning from an interrupt routine. This must be handled bysoftware.

When using the CLI instruction to disable interrupts, the interrupts will be immediatelydisabled. No interrupt will be executed after the CLI instruction, even if it occurs simulta-neously with the CLI instruction. The following example shows how this can be used toavoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

12 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

When using the SEI instruction to enable interrupts, the instruction following SEI will beexecuted before any pending interrupts, as shown in this example.

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cyclesminimum. After four clock cycles the program vector address for the actual interrupthandling routine is executed. During this four clock cycle period, the Program Counter ispushed onto the Stack. The vector is normally a jump to the interrupt routine, and thisjump takes three clock cycles. If an interrupt occurs during execution of a multi-cycleinstruction, this instruction is completed before the interrupt is served. If an interruptoccurs when the MCU is in sleep mode, the interrupt execution response time isincreased by four clock cycles. This increase comes in addition to the start-up time fromthe selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these fourclock cycles, the Program Counter (two bytes) is popped back from the Stack, the StackPointer is incremented by two, and the I-bit in SREG is set.


sei ; set global interrupt enable

sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_SEI(); /* set global interrupt enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

132466E–AVR–10/02

AVR ATmega16

MemoriesThis section describes the different memories in the ATmega16. The AVR architecturehas two main memory spaces, the Data Memory and the Program Memory space. Inaddition, the ATmega16 features an EEPROM Memory for data storage. All three mem-ory spaces are linear and regular.

In-System Reprogrammable Flash Program Memory

The ATmega16 contains 16K bytes On-chip In-System Reprogrammable Flash memoryfor program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is orga-nized as 8K x 16. For software security, the Flash Program memory space is dividedinto two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. TheATmega16 Program Counter (PC) is 13 bits wide, thus addressing the 8K programmemory locations. The operation of Boot Program section and associated Boot Lockbits for software protection are described in detail in “Boot Loader Support – Read-While-Write Self-Programming” on page 241. “Memory Programming” on page 254 con-tains a detailed description on Flash data serial downloading using the SPI pins or theJTAG interface.

Constant tables can be allocated within the entire program memory address space (seethe LPM – Load Program Memory Instruction Description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execu-tion Timing” on page 11.

Figure 8. Program Memory Map

$0000

$1FFF

Application Flash Section

Boot Flash Section

14 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

SRAM Data Memory Figure 9 shows how the ATmega16 SRAM Memory is organized.

The lower 1120 Data Memory locations address the Register file, the I/O Memory, andthe internal data SRAM. The first 96 locations address the Register file and I/O Memory,and the next 1024 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Dis-placement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. Inthe Register file, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the baseaddress given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of inter-nal data SRAM in the ATmega16 are all accessible through all these addressing modes.The Register file is described in “General Purpose Register File” on page 8.

Figure 9. Data Memory Map

Register File

R0R1R2

R29R30R31

I/O Registers$00$01$02

...

$3D$3E$3F

...

$0000$0001$0002

$001D$001E$001F

$0020$0021$0022

...

$005D$005E$005F

...

Data Address Space

$0060$0061

$045E$045F

...

Internal SRAM

152466E–AVR–10/02

Data Memory Access Times This section describes the general access timing concepts for internal memory access.The internal data SRAM access is performed in two clkCPU cycles as described in Figure10.

Figure 10. On-chip Data SRAM Access Cycles

EEPROM Data Memory The ATmega16 contains 512 bytes of data EEPROM memory. It is organized as a sep-arate data space, in which single bytes can be read and written. The EEPROM has anendurance of at least 100,000 write/erase cycles. The access between the EEPROMand the CPU is described in the following, specifying the EEPROM Address Registers,the EEPROM Data Register, and the EEPROM Control Register.

For a detailed description of SPI and JTAG data downloading to the EEPROM, seepage 268 and page 272, respectively.

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 1. A self-timing function, how-ever, lets the user software detect when the next byte can be written. If the user codecontains instructions that write the EEPROM, some precautions must be taken. Inheavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down. Thiscauses the device for some period of time to run at a voltage lower than specified asminimum for the clock frequency used. See “Preventing EEPROM Corruption” on page20 for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-lowed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the nextinstruction is executed. When the EEPROM is written, the CPU is halted for two clockcycles before the next instruction is executed.

clk

WR

RD

Data

Data

Address Address Valid

T1 T2 T3

Compute Address

Rea

dW

rite

CPU

Memory Access Instruction Next Instruction

16 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

The EEPROM Address Register – EEARH and EEARL

• Bits 15..9 – Res: Reserved Bits

These bits are reserved bits in the ATmega16 and will always read as zero.

• Bits 8..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM addressin the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearlybetween 0 and 511. The initial value of EEAR is undefined. A proper value must be writ-ten before the EEPROM may be accessed.

The EEPROM Data Register – EEDR

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written tothe EEPROM in the address given by the EEAR Register. For the EEPROM read oper-ation, the EEDR contains the data read out from the EEPROM at the address given byEEAR.

The EEPROM Control Register – EECR



• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates aconstant interrupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to bewritten. When EEMWE is set, setting EEWE within four clock cycles will write data to theEEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect.

Bit 15 14 13 12 11 10 9 8

– – – – – – – EEAR8 EEARH

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

7 6 5 4 3 2 1 0

Read/Write R R R R R R R R/W


Initial Value 0 0 0 0 0 0 0 X

X X X X X X X X

Bit 7 6 5 4 3 2 1 0

MSB LSB EEDR



Bit 7 6 5 4 3 2 1 0

– – – – EERIE EEMWE EEWE EERE EECR

Read/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 X 0

172466E–AVR–10/02

When EEMWE has been written to one by software, hardware clears the bit to zero afterfour clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. Whenaddress and data are correctly set up, the EEWE bit must be written to one to write thevalue into the EEPROM. The EEMWE bit must be written to one before a logical one iswritten to EEWE, otherwise no EEPROM write takes place. The following procedureshould be followed when writing the EEPROM (the order of steps 3 and 4 is notessential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN in SPMCR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. Thesoftware must check that the Flash programming is completed before initiating a newEEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowingthe CPU to program the Flash. If the Flash is never being updated by the CPU, step 2can be omitted. See “Boot Loader Support – Read-While-Write Self-Programming” onpage 241 for details about boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since theEEPROM Master Write Enable will time-out. If an interrupt routine accessing theEEPROM is interrupting another EEPROM Access, the EEAR or EEDR reGister will bemodified, causing the interrupted EEPROM Access to fail. It is recommended to havethe global interrupt flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. Theuser software can poll this bit and wait for a zero before writing the next byte. WhenEEWE has been set, the CPU is halted for two cycles before the next instruction isexecuted.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. Whenthe correct address is set up in the EEAR register, the EERE bit must be written to alogic one to trigger the EEPROM read. The EEPROM read access takes one instruction,and the requested data is available immediately. When the EEPROM is read, the CPUis halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operationis in progress, it is neither possible to read the EEPROM, nor to change the EEARregister.

The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typicalprogramming time for EEPROM access from the CPU.

Table 1. EEPROM Programming Time

SymbolNumber of Calibrated RC

Oscillator Cycles(1) Typ Programming Time

EEPROM write (from CPU) 8448 8.5 ms

18 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse setting.

The following code examples show one assembly and one C function for writing to theEEPROM. The examples assume that interrupts are controlled (for example by dis-abling interrupts globally) so that no interrupts will occur during execution of thesefunctions. The examples also assume that no Flash Boot Loader is present in the soft-ware. If such code is present, the EEPROM write function must also wait for anyongoing SPM command to finish.


EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address and data registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

192466E–AVR–10/02

The next code examples show assembly and C functions for reading the EEPROM. Theexamples assume that interrupts are controlled so that no interrupts will occur duringexecution of these functions.

Preventing EEPROM Corruption

During periods of low VCC, the EEPROM data can be corrupted because the supply volt-age is too low for the CPU and the EEPROM to operate properly. These issues are thesame as for board level systems using EEPROM, and the same design solutions shouldbe applied.

An EEPROM data corruption can be caused by two situations when the voltage is toolow. First, a regular write sequence to the EEPROM requires a minimum voltage tooperate correctly. Secondly, the CPU itself can execute instructions incorrectly, if thesupply voltage is too low.

EEPROM data corrupt ion can easi ly be avoided by fo l lowing this designrecommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply volt-age. This can be done by enabling the internal Brown-out Detector (BOD). If thedetection level of the internal BOD does not match the needed detection level, anexternal low VCC Reset Protection circuit can be used. If a reset occurs while a writeoperation is in progress, the write operation will be completed provided that thepower supply voltage is sufficient.


EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

20 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

I/O Memory The I/O space definition of the ATmega16 is shown in “Register Summary” on page 298.

All ATmega16 I/Os and peripherals are placed in the I/O space. The I/O locations areaccessed by the IN and OUT instructions, transferring data between the 32 general pur-pose working registers and the I/O space. I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI and CBI instructions. In these registers, thevalue of single bits can be checked by using the SBIS and SBIC instructions. Refer tothe Instruction Set section for more details. When using the I/O specific commands INand OUT, the I/O addresses $00 - $3F must be used. When addressing I/O Registers asdata space using LD and ST instructions, $20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed.Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical one to them. Note that the CBIand SBI instructions will operate on all bits in the I/O Register, writing a one back intoany flag read as set, thus clearing the flag. The CBI and SBI instructions work with reg-isters $00 to $1F only.

The I/O and peripherals control registers are explained in later sections.

212466E–AVR–10/02

System Clock and Clock Options

Clock Systems and their Distribution

Figure 11 presents the principal clock systems in the AVR and their distribution. All ofthe clocks need not be active at a given time. In order to reduce power consumption, theclocks to modules not being used can be halted by using different sleep modes, asdescribed in “Power Management and Sleep Modes” on page 30. The clock systemsare detailed Figure 11.

Figure 11. Clock Distribution

CPU Clock – clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVRcore. Examples of such modules are the General Purpose Register File, the Status Reg-ister and the data memory holding the Stack Pointer. Halting the CPU clock inhibits thecore from performing general operations and calculations.

I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, andUSART. The I/O clock is also used by the External Interrupt module, but note that someexternal interrupts are detected by asynchronous logic, allowing such interrupts to bedetected even if the I/O clock is halted. Also note that address recognition in the TWImodule is carried out asynchronously when clkI/O is halted, enabling TWI address recep-tion in all sleep modes.

Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usuallyactive simultaneously with the CPU clock.

General I/OModules

AsynchronousTimer/Counter

ADC CPU Core RAM

clkI/O

clkASY

AVR ClockControl Unit

clkCPU

Flash andEEPROM

clkFLASH

clkADC

Source Clock

Watchdog Timer

WatchdogOscillator

Reset Logic

ClockMultiplexer

Watchdog Clock

Calibrated RCOscillator

Timer/CounterOscillator

CrystalOscillator

Low-frequencyCrystal Oscillator

External RCOscillator

External Clock

22 ATmega16(L) 2466E–AVR–10/02

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Asynchronous Timer Clock – clkASY

The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clockeddirectly from an external 32 kHz clock crystal. The dedicated clock domain allows usingthis Timer/Counter as a real-time counter even when the device is in sleep mode.

ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU andI/O clocks in order to reduce noise generated by digital circuitry. This gives more accu-rate ADC conversion results.

Clock Sources The device has the following clock source options, selectable by Flash Fuse bits asshown below. The clock from the selected source is input to the AVR clock generator,and routed to the appropriate modules.

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When theCPU wakes up from Power-down or Power-save, the selected clock source is used totime the start-up, ensuring stable Oscillator operation before instruction execution starts.When the CPU starts from Reset, there is as an additional delay allowing the power toreach a stable level before commencing normal operation. The Watchdog Oscillator isused for timing this real-time part of the start-up time. The number of WDT Oscillatorcycles used for each time-out is shown in Table 3. The frequency of the WatchdogOscillator is voltage dependent as shown in “ATmega16 Typical Characteristics – Pre-liminary Data” on page 293. The device is shipped with CKSEL = “0001” and SUT = “10”(1 MHz Internal RC Oscillator, slowly rising power).

Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which canbe configured for use as an On-chip Oscillator, as shown in Figure 12. Either a quartzcrystal or a ceramic resonator may be used. The CKOPT Fuse selects between two dif-ferent Oscillator amplifier modes. When CKOPT is programmed, the Oscillator outputwill oscillate will a full rail-to-rail swing on the output. This mode is suitable when operat-ing in a very noisy environment or when the output from XTAL2 drives a second clockbuffer. This mode has a wide frequency range. When CKOPT is unprogrammed, theOscillator has a smaller output swing. This reduces power consumption considerably.This mode has a limited frequency range and it can not be used to drive other clockbuffers.

For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and16 MHz with CKOPT programmed. C1 and C2 should always be equal for both crystals

Table 2. Device Clocking Options Select(1)

Device Clocking Option CKSEL3..0

External Crystal/Ceramic Resonator 1111 - 1010

External Low-frequency Crystal 1001

External RC Oscillator 1000 - 0101

Calibrated Internal RC Oscillator 0100 - 0001

External Clock 0000

Table 3. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

4.1 ms 4.3 ms 4K (4,096)

65 ms 69 ms 64K (65,536)

232466E–AVR–10/02

and resonators. The optimal value of the capacitors depends on the crystal or resonatorin use, the amount of stray capacitance, and the electromagnetic noise of the environ-ment. Some initial guidelines for choosing capacitors for use with crystals are given inTable 4. For ceramic resonators, the capacitor values given by the manufacturer shouldbe used. For more information on how to choose capacitors and other details on Oscilla-tor operation, refer to the Multi-purpose Oscillator application note.

Figure 12. Crystal Oscillator Connections

The Oscillator can operate in three different modes, each optimized for a specific fre-quency range. The operating mode is selected by the fuses CKSEL3..1 as shown inTable 4.

Note: 1. This option should not be used with crystals, only with ceramic resonators.

Table 4. Crystal Oscillator Operating Modes

CKOPT CKSEL3..1 Frequency Range

(MHz)Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF)

1 101(1) 0.4 - 0.9 –

1 110 0.9 - 3.0 12 - 22

1 111 3.0 - 8.0 12 - 22

0 101, 110, 111 1.0 ≤ 12 - 22

XTAL2

XTAL1

GND

C2

C1

24 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

The CKSEL0 Fuse together with the SUT1..0 fuses select the start-up times as shown inTable 5.

Notes: 1. These options should only be used when not operating close to the maximum fre-quency of the device, and only if frequency stability at start-up is not important for theapplication. These options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure fre-quency stability at start-up. They can also be used with crystals when not operatingclose to the maximum frequency of the device, and if frequency stability at start-up isnot important for the application.

Table 5. Start-up Times for the Crystal Oscillator Clock Selection

CKSEL0 SUT1..0

Start-up Time fromPower-down and

Power-save

Additional Delayfrom Reset(VCC = 5.0V) Recommended Usage

0 00 258 CK(1) 4.1 msCeramic resonator, fast rising power

0 01 258 CK(1) 65 msCeramic resonator, slowly rising power

0 10 1K CK(2) –Ceramic resonator, BOD enabled

0 11 1K CK(2) 4.1 msCeramic resonator, fast rising power

1 00 1K CK(2) 65 msCeramic resonator, slowly rising power

1 01 16K CK –Crystal Oscillator, BOD enabled

1 10 16K CK 4.1 msCrystal Oscillator, fast rising power

1 11 16K CK 65 msCrystal Oscillator, slowly rising power

252466E–AVR–10/02

Low-frequency Crystal Oscillator

To use a 32.768 kHz watch crystal as the clock source for the device, the Low-fre-quency Crystal Oscillator must be selected by setting the CKSEL fuses to “1001”. Thecrystal should be connected as shown in Figure 12. By programming the CKOPT Fuse,the user can enable internal capacitors on XTAL1 and XTAL2, thereby removing theneed for external capacitors. The internal capacitors have a nominal value of 36 pF.Refer to the 32 kHz Crystal Oscillator application note for details on Oscillator operationand how to choose appropriate values for C1 and C2.

When this Oscillator is selected, start-up times are determined by the SUT fuses asshown in Table 6.

Note: 1. These options should only be used if frequency stability at start-up is not important forthe application.

External RC Oscillator For timing insensitive applications, the external RC configuration shown in Figure 13can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C shouldbe at least 22 pF. By programming the CKOPT Fuse, the user can enable an internal36 pF capacitor between XTAL1 and GND, thereby removing the need for an externalcapacitor. For more information on Oscillator operation and details on how to choose Rand C, refer to the External RC Oscillator application note.

Figure 13. External RC Configuration

The Oscillator can operate in four different modes, each optimized for a specific fre-quency range. The operating mode is selected by the fuses CKSEL3..0 as shown inTable 7.

Table 6. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

SUT1..0


Power-save

Additional Delay from Reset (VCC = 5.0V) Recommended Usage

00 1K CK(1) 4.1 ms Fast rising power or BOD enabled

01 1K CK(1) 65 ms Slowly rising power

10 32K CK 65 ms Stable frequency at start-up

11 Reserved

XTAL2

XTAL1

GNDC

R

VCC

NC

26 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

When this Oscillator is selected, start-up times are determined by the SUT fuses asshown in Table 8.

Note: 1. This option should not be used when operating close to the maximum frequency ofthe device.

Calibrated Internal RC Oscillator

The Calibrated Internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0 MHz clock. Allfrequencies are nominal values at 5V and 25°C. This clock may be selected as the sys-tem clock by programming the CKSEL fuses as shown in Table 9. If selected, it willoperate with no external components. The CKOPT Fuse should always be unpro-grammed when using this clock option. During Reset, hardware loads the calibrationbyte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator.At 5V, 25°C and 1.0 MHz Oscillator frequency selected, this calibration gives a fre-quency within ± 1% of the nominal frequency. When this Oscillator is used as the ChipClock, the Watchdog Oscillator will still be used for the Watchdog Timer and for thereset time-out. For more information on the pre-programmed calibration value, see thesection “Calibration Byte” on page 256.

Note: 1. The device is shipped with this option selected.

Table 7. External RC Oscillator Operating Modes

CKSEL3..0 Frequency Range (MHz)

0101 ≤ 0.9

0110 0.9 - 3.0

0111 3.0 - 8.0

1000 8.0 - 12.0

Table 8. Start-up Times for the External RC Oscillator Clock Selection

SUT1..0


Power-save

Additional Delayfrom Reset (VCC = 5.0V) Recommended Usage

00 18 CK – BOD enabled

01 18 CK 4.1 ms Fast rising power

10 18 CK 65 ms Slowly rising power

11 6 CK(1) 4.1 ms Fast rising power or BOD enabled

Table 9. Internal Calibrated RC Oscillator Operating Modes

CKSEL3..0 Nominal Frequency (MHz)

0001(1) 1.0

0010 2.0

0011 4.0

0100 8.0

272466E–AVR–10/02

When this Oscillator is selected, start-up times are determined by the SUT fuses asshown in Table 10. XTAL1 and XTAL2 should be left unconnected (NC).

Note: 1. The device is shipped with this option selected.

Oscillator Calibration Register – OSCCAL

• Bits 7..0 – CAL7..0: Oscillator Calibration Value

Writing the calibration byte to this address will trim the Internal Oscillator to remove pro-cess variations from the Oscillator frequency. This is done automatically during ChipReset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the Internal Oscillator. Writing$FF to the register gives the highest available frequency. The calibrated Oscillator isused to time EEPROM and Flash access. If EEPROM or Flash is written, do not cali-brate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flashwrite may fail. Note that the Oscillator is intended for calibration to 1.0, 2.0, 4.0, or8.0 MHz. Tuning to other values is not guaranteed, as indicated in Table 11.

Table 10. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

SUT1..0


Power-save




10(1) 6 CK 65 ms Slowly rising power

11 Reserved

Bit 7 6 5 4 3 2 1 0

CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL


Initial Value Device Specific Calibration Value

Table 11. Internal RC Oscillator Frequency Range.

OSCCAL ValueMin Frequency in Percentage of

Nominal Frequency (%)Max Frequency in Percentage of

Nominal Frequency (%)

$00 50 100

$7F 75 150

$FF 100 200

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External Clock To drive the device from an external clock source, XTAL1 should be driven as shown inFigure 14. To run the device on an external clock, the CKSEL fuses must be pro-grammed to “0000”. By programming the CKOPT Fuse, the user can enable an internal36 pF capacitor between XTAL1 and GND.

Figure 14. External Clock Drive Configuration

When this clock source is selected, start-up times are determined by the SUT fuses asshown in Table 12.

Timer/Counter Oscillator For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), thecrystal is connected directly between the pins. No external capacitors are needed. TheOscillator is optimized for use with a 32.768 kHz watch crystal. Applying an externalclock source to TOSC1 is not recommended.

Table 12. Start-up Times for the External Clock Selection

SUT1..0

Start-up Time from Power-down and

Power-save




10 6 CK 65 ms Slowly rising power

11 Reserved

EXTERNALCLOCKSIGNAL

292466E–AVR–10/02

Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, therebysaving power. The AVR provides various sleep modes allowing the user to tailor thepower consumption to the application’s requirements.

To enter any of the six sleep modes, the SE bit in MCUCR must be written to logic oneand a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in theMCUCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down,Power-save, Standby, or Extended Standby) will be activated by the SLEEP instruction.See Table 13 for a summary. If an enabled interrupt occurs while the MCU is in a sleepmode, the MCU wakes up. The MCU is then halted for four cycles in addition to thestart-up time, it executes the interrupt routine, and resumes execution from the instruc-tion following SLEEP. The contents of the Register File and SRAM are unaltered whenthe device wakes up from sleep. If a Reset occurs during sleep mode, the MCU wakesup and executes from the Reset Vector.

Figure 11 on page 22 presents the different clock systems in the ATmega16, and theirdistribution. The figure is helpful in selecting an appropriate sleep mode.

MCU Control Register – MCUCR

The MCU Control Register contains control bits for power management.

• Bits 7, 5, 4 – SM2..0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the six available sleep modes as shown in Table 13.

Note: 1. Standby mode and Extended Standby mode are only available with external crystalsor resonators.

• Bit 6 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when theSLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it isthe programmers purpose, it is recommended to write the Sleep Enable (SE) bit to onejust before the execution of the SLEEP instruction and to clear it immediately after wak-ing up.

Bit 7 6 5 4 3 2 1 0

SM2 SE SM1 SM0 ISC11 ISC10 ISC01 ISC00 MCUCR



Table 13. Sleep Mode Select

SM2 SM1 SM0 Sleep Mode

0 0 0 Idle

0 0 1 ADC Noise Reduction

0 1 0 Power-down

0 1 1 Power-save

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Standby(1)

1 1 1 Extended Standby(1)

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Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enterIdle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continueoperating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the otherclocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well asinternal ones like the Timer Overflow and USART Transmit Complete interrupts. Ifwake-up from the Analog Comparator interrupt is not required, the Analog Comparatorcan be powered down by setting the ACD bit in the Analog Comparator Control and Sta-tus Register – ACSR. This will reduce power consumption in Idle mode. If the ADC isenabled, a conversion starts automatically when this mode is entered.

ADC Noise Reduction Mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enterADC Noise Reduction mode, stopping the CPU but allowing the ADC, the External Inter-rupts, the Two-wire Serial Interface address watch, Timer/Counter2 and the Watchdogto continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clk-

FLASH, while allowing the other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measure-ments. If the ADC is enabled, a conversion starts automatically when this mode isentered. Apart form the ADC Conversion Complete interrupt, only an External Reset, aWatchdog Reset, a Brown-out Reset, a Two-wire Serial Interface Address Match Inter-rupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an External levelinterrupt on INT0 or INT1, or an external interrupt on INT2 can wake up the MCU fromADC Noise Reduction mode.

Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enterPower-down mode. In this mode, the External Oscillator is stopped, while the Externalinterrupts, the Two-wire Serial Interface address watch, and the Watchdog continueoperating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, aTwo-wire Serial Interface address match interrupt, an External level interrupt on INT0 orINT1, or an External interrupt on INT2 can wake up the MCU. This sleep mode basicallyhalts all generated clocks, allowing operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, thechanged level must be held for some time to wake up the MCU. Refer to “External Inter-rupts” on page 64 for details.

When waking up from Power-down mode, there is a delay from the wake-up conditionoccurs until the wake-up becomes effective. This allows the clock to restart and becomestable after having been stopped. The wake-up period is defined by the same CKSELfuses that define the reset time-out period, as described in “Clock Sources” on page 23.

Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enterPower-save mode. This mode is identical to Power-down, with one exception:

If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set,Timer/Counter2 will run during sleep. The device can wake up from either Timer Over-f low or Output Compare event from Timer/Counter2 i f the correspondingTimer/Counter2 interrupt enable bits are set in TIMSK, and the Global Interrupt Enablebit in SREG is set.

If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is rec-ommended instead of Power-save mode because the contents of the registers in the

312466E–AVR–10/02

Asynchronous Timer should be considered undefined after wake-up in Power-savemode if AS2 is 0.

This sleep mode basically halts all clocks except clkASY, allowing operation only of asyn-chronous modules, including Timer/Counter2 if clocked asynchronously.

Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected,the SLEEP instruction makes the MCU enter Standby mode. This mode is identical toPower-down with the exception that the Oscillator is kept running. From Standby mode,the device wakes up in six clock cycles.

Extended Standby Mode When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected,the SLEEP instruction makes the MCU enter Extended Standby mode. This mode isidentical to Power-save mode with the exception that the Oscillator is kept running.From Extended Standby mode, the device wakes up in six clock cycles..

Notes: 1. External Crystal or resonator selected as clock source.2. If AS2 bit in ASSR is set.3. Only INT2 or level interrupt INT1 and INT0.

Table 14. Active Clock Domains and Wake Up Sources in the Different Sleep Modes

Active Clock domains Oscillators Wake-up Sources

Sleep Mode clkCPU clkFLASH clkIO clkADC clkASY

Main Clock Source Enabled

Timer Osc. Enabled

INT2INT1INT0

TWI Address

MatchTimer

2

SPM / EEPROM

Ready ADCOther

I/O

Idle X X X X X(2) X X X X X X

ADC NoiseRedu-ction

X X X X(2) X(3) X X X X

Power Down

X(3) X

Power Save

X(2) X(2) X(3) X X(2)

Standby(1) X X(3) X

Exten-dedStandby(1)

X(2) X X(2) X(3) X X(2)

32 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption inan AVR controlled system. In general, sleep modes should be used as much as possi-ble, and the sleep mode should be selected so that as few as possible of the device’sfunctions are operating. All functions not needed should be disabled. In particular, thefollowing modules may need special consideration when trying to achieve the lowestpossible power consumption.

Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC shouldbe disabled before entering any sleep mode. When the ADC is turned off and on again,the next conversion will be an extended conversion. Refer to “Analog to Digital Con-verter” on page 198 for details on ADC operation.

Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. Whenentering ADC Noise Reduction mode, the Analog Comparator should be disabled. In theother sleep modes, the Analog Comparator is automatically disabled. However, if theAnalog Comparator is set up to use the Internal Voltage Reference as input, the AnalogComparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Ref-erence will be enabled, independent of sleep mode. Refer to “Analog Comparator” onpage 195 for details on how to configure the Analog Comparator.

Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turnedoff. If the Brown-out Detector is enabled by the BODEN Fuse, it will be enabled in allsleep modes, and hence, always consume power. In the deeper sleep modes, this willcontribute significantly to the total current consumption. Refer to “Brown-out Detection”on page 37 for details on how to configure the Brown-out Detector.

Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detec-tor, the Analog Comparator or the ADC. If these modules are disabled as described inthe sections above, the internal voltage reference will be disabled and it will not be con-suming power. When turned on again, the user must allow the reference to start upbefore the output is used. If the reference is kept on in sleep mode, the output can beused immediately. Refer to “Internal Voltage Reference” on page 39 for details on thestart-up time.

Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off.If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,always consume power. In the deeper sleep modes, this will contribute significantly tothe total current consumption. Refer to “Watchdog Timer” on page 39 for details on howto configure the Watchdog Timer.

Port Pins When entering a sleep mode, all port pins should be configured to use minimum power.The most important thing is then to ensure that no pins drive resistive loads. In sleepmodes where the both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, theinput buffers of the device will be disabled. This ensures that no power is consumed bythe input logic when not needed. In some cases, the input logic is needed for detectingwake-up conditions, and it will then be enabled. Refer to the section “Digital InputEnable and Sleep Modes” on page 51 for details on which pins are enabled. If the inputbuffer is enabled and the input signal is left floating or have an analog signal level closeto VCC/2, the input buffer will use excessive power.

332466E–AVR–10/02

System Control and Reset

Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts exe-cution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP– absolute jump – instruction to the reset handling routine. If the program never enablesan interrupt source, the Interrupt Vectors are not used, and regular program code canbe placed at these locations. This is also the case if the Reset Vector is in the Applica-tion section while the Interrupt Vectors are in the Boot section or vice versa. The circuitdiagram in Figure 15 shows the reset logic. Table 15 defines the electrical parameters ofthe reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset sourcegoes active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching theInternal Reset. This allows the power to reach a stable level before normal operationstarts. The time-out period of the delay counter is defined by the user through theCKSEL Fuses. The different selections for the delay period are presented in “ClockSources” on page 23.

Reset Sources The ATmega16 has five sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT).

• External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled.

• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan chains of the JTAG system. Refer to the section “IEEE 1149.1 (JTAG) Boundary-scan” on page 222 for details.

34 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 15. Reset Logic

Notes: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT(falling).

2. VBOT may be below nominal minimum operating voltage for some devices. Fordevices where this is the case, the device is tested down to VCC = VBOT during theproduction test. This guarantees that a Brown-out Reset will occur before VCC dropsto a voltage where correct operation of the microcontroller is no longer guaranteed.The test is performed using BODLEVEL = 1 for ATmega16L and BODLEVEL = 0 forATmega16. BODLEVEL = 1 is not applicable for ATmega16.

Table 15. Reset Characteristics

Symbol Parameter Condition Min Typ Max Units

VPOT

Power-on Reset Threshold Voltage (rising)

1.4 2.3 V

Power-on Reset Threshold Voltage (falling)(1)

1.3 2.3 V

VRST RESET Pin Threshold Voltage

0.2 VCC 0.85VCC V

tRSTMinimum pulse width on RESET Pin

50 ns

VBOT

Brown-out Reset Threshold Voltage(2)

BODLEVEL = 1 2.5 2.7 3.2V

BODLEVEL = 0 3.7 4.0 4.2

tBOD

Minimum low voltage period for Brown-out Detection

BODLEVEL = 1 2 µs

BODLEVEL = 0 2 µs

VHYSTBrown-out Detector hysteresis

50 mV

MCU Control and StatusRegister (MCUCSR)

BODENBODLEVEL

Delay Counters

CKSEL[3:0]

CKTIMEOUT

WD

RF

BO

RF

EX

TR

F

PO

RF

DATA BUS

ClockGenerator

SPIKEFILTER

Pull-up Resistor

JTR

F

JTAG ResetRegister

WatchdogOscillator

SUT[1:0]

WatchdogTimer

Reset Circuit

Brown-outReset Circuit

Power-onReset Circuit

INT

ER

NA

L R

ES

ET

CO

UN

TE

R R

ES

ET

352466E–AVR–10/02

Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-tion level is defined in Table 15. The POR is activated whenever VCC is below thedetection level. The POR circuit can be used to trigger the Start-up Reset, as well as todetect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reach-ing the Power-on Reset threshold voltage invokes the delay counter, which determineshow long the device is kept in RESET after VCC rise. The RESET signal is activatedagain, without any delay, when VCC decreases below the detection level.

Figure 16. MCU Start-up, RESET Tied to VCC.

Figure 17. MCU Start-up, RESET Extended Externally

External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longerthan the minimum pulse width (see Table 15) will generate a reset, even if the clock isnot running. Shorter pulses are not guaranteed to generate a reset. When the appliedsignal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delaycounter starts the MCU after the Time-out period tTOUT has expired.

V

RESET

TIME-OUT

INTERNALRESET

tTOUT

VPOT

VRST

CC

RESET

TIME-OUT

INTERNALRESET

tTOUT

VPOT

VRST

VCC

36 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 18. External Reset During Operation

Brown-out Detection ATmega16 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCClevel during operation by comparing it to a fixed trigger level. The trigger level for theBOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed),or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spikefree Brown-out Detection. The hysteresis on the detection level should be interpreted asVBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.

The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD isenabled (BODEN programmed), and VCC decreases to a value below the trigger level(VBOT- in Figure 19), the Brown-out Reset is immediately activated. When VCC increasesabove the trigger level (VBOT+ in Figure 19), the delay counter starts the MCU after theTime-out period tTOUT has expired.

The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger levelfor longer than tBOD given in Table 15.

Figure 19. Brown-out Reset During Operation

CC

VCC

RESET

TIME-OUT

INTERNALRESET

VBOT-VBOT+

tTOUT

372466E–AVR–10/02

Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-tion. On the falling edge of this pulse, the delay timer starts counting the Time-out periodtTOUT. Refer to page 39 for details on operation of the Watchdog Timer.

Figure 20. Watchdog Reset During Operation

MCU Control and Status Register – MCUCSR

The MCU Control and Status Register provides information on which reset sourcecaused an MCU Reset.

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Registerselected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, orby writing a logic zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or bywriting a logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or bywriting a logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or bywriting a logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero tothe flag.

To make use of the Reset Flags to identify a reset condition, the user should read andthen reset the MCUCSR as early as possible in the program. If the register is clearedbefore another reset occurs, the source of the reset can be found by examining the resetflags.

CK

CC

Bit 7 6 5 4 3 2 1 0

JTD ISC2 – JTRF WDRF BORF EXTRF PORF MCUCSR

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 0 See Bit Description

38 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Internal Voltage Reference

ATmega16 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The2.56V reference to the ADC is generated from the internal bandgap reference.

Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used.The start-up time is given in Table 16. To save power, the reference is not always turnedon. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODEN Fuse).

2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, theuser must always allow the reference to start up before the output from the Analog Com-parator or ADC is used. To reduce power consumption in Power-down mode, the usercan avoid the three conditions above to ensure that the reference is turned off beforeentering Power-down mode.

Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is the typical value at VCC = 5V. See characterization data for typical values atother VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Resetinterval can be adjusted as shown in Table 17 on page 40. The WDR – Watchdog Reset– instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it isdisabled and when a Chip Reset occurs. Eight different clock cycle periods can beselected to determine the reset period. If the reset period expires without anotherWatchdog Reset, the ATmega16 resets and executes from the Reset Vector. For timingdetails on the Watchdog Reset, refer to page 38.

To prevent unintentional disabling of the Watchdog, a special turn-off sequence must befollowed when the Watchdog is disabled. Refer to the description of the Watchdog TimerControl Register for details.

Figure 21. Watchdog Timer

Table 16. Internal Voltage Reference Characteristics

Symbol Parameter Min Typ Max Units

VBG Bandgap reference voltage 1.15 1.23 1.35 V

tBG Bandgap reference start-up time 40 70 µs

IBG Bandgap reference current consumption 10 µA

WATCHDOGOSCILLATOR

392466E–AVR–10/02

Watchdog Timer Control Register – WDTCR



• Bit 4 – WDTOE: Watchdog Turn-off Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdogwill not be disabled. Once written to one, hardware will clear this bit after four clockcycles. Refer to the description of the WDE bit for a Watchdog disable procedure.

• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE iswritten to logic zero, the Watchdog Timer function is disabled. WDE can only be clearedif the WDTOE bit has logic level one. To disable an enabled Watchdog Timer, the follow-ing procedure must be followed:

1. In the same operation, write a logic one to WDTOE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0

The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when theWatchdog Timer is enabled. The different prescaling values and their correspondingTimeout Periods are shown in Table 17.

Bit 7 6 5 4 3 2 1 0

– – – WDTOE WDE WDP2 WDP1 WDP0 WDTCR

Read/Write R R R R/W R/W R/W R/W R/W


Table 17. Watchdog Timer Prescale Select

WDP2 WDP1 WDP0Number of WDT

Oscillator CyclesTypical Time-out

at VCC = 3.0VTypical Time-out

at VCC = 5.0V

0 0 0 16K (16,384) 17.1 ms 16.3 ms

0 0 1 32K (32,768) 34.3 ms 32.5 ms

0 1 0 64K (65,536) 68.5 ms 65 ms

0 1 1 128K (131,072) 0.14 s 0.13 s

1 0 0 256K (262,144) 0.27 s 0.26 s

1 0 1 512K (524,288) 0.55 s 0.52 s

1 1 0 1,024K (1,048,576) 1.1 s 1.0 s

1 1 1 2,048K (2,097,152) 2.2 s 2.1 s

40 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

The following code example shows one assembly and one C function for turning off theWDT. The example assumes that interrupts are controlled (for example by disablinginterrupts globally) so that no interrupts will occur during execution of these functions.


WDT_off:

; Write logical one to WDTOE and WDE

ldi r16, (1<<WDTOE)|(1<<WDE)

out WDTCR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCR, r16

ret

C Code Example

void WDT_off(void)

/* Write logical one to WDTOE and WDE */

WDTCR = (1<<WDTOE) | (1<<WDE);

/* Turn off WDT */

WDTCR = 0x00;

412466E–AVR–10/02

Interrupts This section describes the specifics of the interrupt handling as performed inATmega16. For a general explanation of the AVR interrupt handling, refer to “Reset andInterrupt Handling” on page 11.

Interrupt Vectors in ATmega16

Notes: 1. When the BOOTRST fuse is programmed, the device will jump to the Boot Loaderaddress at reset, see “Boot Loader Support – Read-While-Write Self-Programming”on page 241.

2. When the IVSEL bit in GICR is set, interrupt vectors will be moved to the start of theBoot Flash section. The address of each Interrupt Vector will then be the address inthis table added to the start address of the Boot Flash section.

Table 19 shows Reset and Interrupt Vectors placement for the various combinations ofBOOTRST and IVSEL settings. If the program never enables an interrupt source, theInterrupt Vectors are not used, and regular program code can be placed at these loca-tions. This is also the case if the Reset Vector is in the Application section while theInterrupt Vectors are in the Boot section or vice versa.

Table 18. Reset and Interrupt Vectors

Vector No.Program

Address(2) Source Interrupt Definition

1 $000(1) RESET External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, and JTAG AVR Reset

2 $002 INT0 External Interrupt Request 0


4 $006 TIMER2 COMP Timer/Counter2 Compare Match

5 $008 TIMER2 OVF Timer/Counter2 Overflow

6 $00A TIMER1 CAPT Timer/Counter1 Capture Event

7 $00C TIMER1 COMPA Timer/Counter1 Compare Match A

8 $00E TIMER1 COMPB Timer/Counter1 Compare Match B



11 $014 SPI, STC Serial Transfer Complete

12 $016 USART, RXC USART, Rx Complete

13 $018 USART, UDRE USART Data Register Empty

14 $01A USART, TXC USART, Tx Complete

15 $01C ADC ADC Conversion Complete

16 $01E EE_RDY EEPROM Ready

17 $020 ANA_COMP Analog Comparator

18 $022 TWI Two-wire Serial Interface


20 $026 TIMER0 COMP Timer/Counter0 Compare Match

21 $028 SPM_RDY Store Program Memory Ready

42 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Note: 1. The Boot Reset Address is shown in Table 99 on page 252. For the BOOTRST Fuse“1” means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt VectorAddresses in ATmega16 is:

Address Labels Code Comments

$000 jmp RESET ; Reset Handler

$002 jmp EXT_INT0 ; IRQ0 Handler


$006 jmp TIM2_COMP ; Timer2 Compare Handler

$008 jmp TIM2_OVF ; Timer2 Overflow Handler

$00A jmp TIM1_CAPT ; Timer1 Capture Handler

$00C jmp TIM1_COMPA ; Timer1 CompareA Handler

$00E jmp TIM1_COMPB ; Timer1 CompareB Handler



$014 jmp SPI_STC ; SPI Transfer Complete Handler

$016 jmp USART_RXC ; USART RX Complete Handler

$018 jmp USART_UDRE ; UDR Empty Handler

$01A jmp USART_TXC ; USART TX Complete Handler

$01C jmp ADC ; ADC Conversion Complete Handler

$01E jmp EE_RDY ; EEPROM Ready Handler

$020 jmp ANA_COMP ; Analog Comparator Handler

$022 jmp TWSI ; Two-wire Serial Interface Handler


$026 jmp TIM0_COMP ; Timer0 Compare Handler

$028 jmp SPM_RDY ; Store Program Memory Ready Handler

;

$02A RESET: ldi r16,high(RAMEND) ; Main program start

$02B out SPH,r16 ; Set stack pointer to top of RAM

$02C ldi r16,low(RAMEND)

$02D out SPL,r16

$02E sei ; Enable interrupts

$02F <instr> xxx

... ... ...

Table 19. Reset and Interrupt Vectors Placement(1)

BOOTRST IVSEL Reset address Interrupt Vectors Start Address

1 0 $0000 $0002

1 1 $0000 Boot Reset Address + $0002

0 0 Boot Reset Address $0002

0 1 Boot Reset Address Boot Reset Address + $0002

432466E–AVR–10/02

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes andthe IVSEL bit in the GICR Register is set before any interrupts are enabled, the mosttypical and general program setup for the Reset and Interrupt Vector Addresses is:


$000 RESET: ldi r16,high(RAMEND) ; Main program start

$001 out SPH,r16 ; Set stack pointer to top of RAM

$002 ldi r16,low(RAMEND)

$003 out SPL,r16

$004 sei ; Enable interrupts

$005 <instr> xxx

;

.org $1C02

$1C02 jmp EXT_INT0 ; IRQ0 Handler


... .... .. ;

$1C28 jmp SPM_RDY ; Store Program Memory Ready Handler

When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, themost typical and general program setup for the Reset and Interrupt Vector Addresses is:


.org $002



... .... .. ;

$028 jmp SPM_RDY ; Store Program Memory Ready Handler

;

.org $1C00$1C00 RESET: ldi r16,high(RAMEND) ; Main program start

$1C01 out SPH,r16 ; Set stack pointer to top of RAM

$1C02 ldi r16,low(RAMEND)

$1C03 out SPL,r16

$1C04 sei ; Enable interrupts

$1C05 <instr> xxx

When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and theIVSEL bit in the GICR Register is set before any interrupts are enabled, the most typicaland general program setup for the Reset and Interrupt Vector Addresses is:


.org $1C00$1C00 jmp RESET ; Reset handler$1C02 jmp EXT_INT0 ; IRQ0 Handler


... .... .. ;

$1C28 jmp SPM_RDY ; Store Program Memory Ready Handler

;

$1C2A RESET: ldi r16,high(RAMEND) ; Main program start

$1C2B out SPH,r16 ; Set stack pointer to top of RAM

$1C2C ldi r16,low(RAMEND)

$1C2D out SPL,r16

$1C2E sei ; Enable interrupts

$1C2F <instr> xxx

44 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Moving Interrupts Between Application and Boot Space

The General Interrupt Control Register controls the placement of the Interrupt Vectortable.

General Interrupt Control Register – GICR

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of theFlash memory. When this bit is set (one), the interrupt vectors are moved to the begin-ning of the Boot Loader section of the Flash. The actual address of the start of the BootFlash section is determined by the BOOTSZ fuses. Refer to the section “Boot LoaderSupport – Read-While-Write Self-Programming” on page 241 for details. To avoid unin-tentional changes of Interrupt Vector tables, a special write procedure must be followedto change the IVSEL bit:

1. Write the Interrupt Vector Change Enable (IVCE) bit to one.

2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts aredisabled in the cycle IVCE is set, and they remain disabled until after the instruction fol-lowing the write to IVSEL. If IVSEL is not written, interrupts remain disabled for fourcycles. The I-bit in the Status Register is unaffected by the automatic disabling.

Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-grammed, interrupts are disabled while executing from the Application section. IfInterrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is pro-gramed, interrupts are disabled while executing from the Boot Loader section. Refer tothe section “Boot Loader Support – Read-While-Write Self-Programming” on page 241for details on Boot Lock bits.

Bit 7 6 5 4 3 2 1 0

INT1 INT0 INT2 – – – IVSEL IVCE GICR

Read/Write R/W R/W R/W R R R R/W R/W


452466E–AVR–10/02

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE iscleared by hardware four cycles after it is written or when IVSEL is written. Setting theIVCE bit will disable interrupts, as explained in the IVSEL description above. See CodeExample below.


Move_interrupts:

; Enable change of interrupt vectors

ldi r16, (1<<IVCE)

out GICR, r16

; Move interrupts to boot Flash section

ldi r16, (1<<IVSEL)

out GICR, r16

ret

C Code Example

void Move_interrupts(void)

/* Enable change of interrupt vectors */

GICR = (1<<IVCE);

/* Move interrupts to boot Flash section */

GICR = (1<<IVSEL);

46 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

I/O Ports

Introduction All AVR ports have true Read-Modify-Write functionality when used as general digitalI/O ports. This means that the direction of one port pin can be changed without uninten-tionally changing the direction of any other pin with the SBI and CBI instructions. Thesame applies when changing drive value (if configured as output) or enabling/disablingof pull-up resistors (if configured as input). Each output buffer has symmetrical drivecharacteristics with both high sink and source capability. The pin driver is strong enoughto drive LED displays directly. All port pins have individually selectable pull-up resistorswith a supply-voltage invariant resistance. All I/O pins have protection diodes to bothVCC and Ground as indicated in Figure 22. Refer to “Electrical Characteristics” on page285 for a complete list of parameters.

Figure 22. I/O Pin Equivalent Schematic

All registers and bit references in this section are written in general form. A lower case“x” represents the numbering letter for the port, and a lower case “n” represents the bitnumber. However, when using the register or bit defines in a program, the precise formmust be used. i.e., PORTB3 for bit no. 3 in Port B, here documented generally asPORTxn. The physical I/O Registers and bit locations are listed in “Register Descriptionfor I/O Ports” on page 62.

Three I/O memory address locations are allocated for each port, one each for the DataRegister – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. ThePort Input Pins I/O location is read only, while the Data Register and the Data DirectionRegister are read/write. In addition, the Pull-up Disable – PUD bit in SFIOR disables thepull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” onpage 48. Most port pins are multiplexed with alternate functions for the peripheral fea-tures on the device. How each alternate function interferes with the port pin is describedin “Alternate Port Functions” on page 52. Refer to the individual module sections for afull description of the alternate functions.

Note that enabling the alternate function of some of the port pins does not affect the useof the other pins in the port as general digital I/O.

Cpin

Logic

Rpu

See Figure 23"General Digital I/O" for

Details

Pxn

472466E–AVR–10/02

Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 23 shows afunctional description of one I/O-port pin, here generically called Pxn.

Figure 23. General Digital I/O(1)

Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,SLEEP, and PUD are common to all ports.

Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in“Register Description for I/O Ports” on page 62, the DDxn bits are accessed at the DDRxI/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINxI/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is writtenlogic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is config-ured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-upresistor is activated. To switch the pull-up resistor off, PORTxn has to be written logiczero or the pin has to be configured as an output pin. The port pins are tri-stated when areset condition becomes active, even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin isdriven high (one). If PORTxn is written logic zero when the pin is configured as an out-put pin, the port pin is driven low (zero).

When switching between tri-state (DDxn, PORTxn = 0b00) and output high (DDxn,PORTxn = 0b11), an intermediate state with either pull-up enabled (DDxn, PORTxn =0b01) or output low (DDxn, PORTxn = 0b10) must occur. Normally, the pull-up

clk

RPx

RRx

WPx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WPx: WRITE PORTxRRx: READ PORTx REGISTERRPx: READ PORTx PIN

PUD: PULLUP DISABLE

clkI/O: I/O CLOCK

RDx: READ DDRx

D

L

Q

Q

RESET

RESET

Q

QD

Q

Q D

CLR

PORTxn

Q

Q D

CLR

DDxn

PINxn

DAT

A B

US

SLEEP

SLEEP: SLEEP CONTROL

Pxn

I/O

48 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

enabled state is fully acceptable, as a high-impedant environment will not notice the dif-ference between a strong high driver and a pull-up. If this is not the case, the PUD bit inthe SFIOR Register can be set to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. Theuser must use either the tri-state (DDxn, PORTxn = 0b00) or the output high state(DDxn, PORTxn = 0b11) as an intermediate step.

Table 20 summarizes the control signals for the pin value.

Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read throughthe PINxn Register bit. As shown in Figure 23, the PINxn Register bit and the precedinglatch constitute a synchronizer. This is needed to avoid metastability if the physical pinchanges value near the edge of the internal clock, but it also introduces a delay. Figure24 shows a timing diagram of the synchronization when reading an externally appliedpin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,minrespectively.

Figure 24. Synchronization when Reading an Externally Applied Pin Value

Consider the clock period starting shortly after the first falling edge of the system clock.The latch is closed when the clock is low, and goes transparent when the clock is high,as indicated by the shaded region of the “SYNC LATCH” signal. The signal value islatched when the system clock goes low. It is clocked into the PINxn Register at the

Table 20. Port Pin Configurations

DDxn PORTxnPUD

(in SFIOR) I/O Pull-up Comment

0 0 X Input No Tri-state (Hi-Z)

0 1 0 Input YesPxn will source current if ext. pulled low.

0 1 1 Input No Tri-state (Hi-Z)

1 0 X Output No Output Low (Sink)

1 1 X Output No Output High (Source)

SYSTEM CLK

INSTRUCTIONS

SYNC LATCH

PINxn

r17

in r17, PINx

0xFF0x00

tpd, max

XXXXXX

tpd, min

492466E–AVR–10/02

succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, asingle signal transition on the pin will be delayed between ½ and 1½ system clockperiod depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted asindicated in Figure 25. The out instruction sets the “SYNC LATCH” signal at the positiveedge of the clock. In this case, the delay tpd through the synchronizer is one systemclock period.

Figure 25. Synchronization when Reading a Software Assigned Pin Value

nop in r17, PINx

0xFF

0x00 0xFF

tpd

out PORTx, r16

SYSTEM CLK

r16

INSTRUCTIONS

SYNC LATCH

PINxn

r17

50 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, anddefine the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. Theresulting pin values are read back again, but as previously discussed, a nop instructionis included to be able to read back the value recently assigned to some of the pins.

Note: 1. For the assembly program, two temporary registers are used to minimize the timefrom pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set,defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

Digital Input Enable and Sleep Modes

As shown in Figure 23, the digital input signal can be clamped to ground at the input ofthe schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU SleepController in Power-down mode, Power-save mode, Standby mode, and ExtendedStandby mode to avoid high power consumption if some input signals are left floating, orhave an analog signal level close to VCC/2.

SLEEP is overridden for port pins enabled as External Interrupt pins. If the ExternalInterrupt Request is not enabled, SLEEP is active also for these pins. SLEEP is alsooverridden by various other alternate functions as described in “Alternate Port Func-tions” on page 52.

If a logic high level (“one”) is present on an Asynchronous External Interrupt pin config-ured as “Interrupt on Any Logic Change on Pin” while the External Interrupt is notenabled, the corresponding External Interrupt Flag will be set when resuming from theabove mentioned sleep modes, as the clamping in these sleep modes produces therequested logic change.

Assembly Code Example(1)

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in r16,PINB

...

C Code Example(1)

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

_NOP();

/* Read port pins */

i = PINB;

...

512466E–AVR–10/02

Alternate Port Functions Most port pins have alternate functions in addition to being General Digital I/Os. Figure26 shows how the port pin control signals from the simplified Figure 23 can be overrid-den by alternate functions. The overriding signals may not be present in all port pins, butthe figure serves as a generic description applicable to all port pins in the AVR micro-controller family.

Figure 26. Alternate Port Functions(1)

Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

Table 21 summarizes the function of the overriding signals. The pin and port indexesfrom Figure 26 are not shown in the succeeding tables. The overriding signals are gen-erated internally in the modules having the alternate function.

clk

RPx

RRx

WPx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WPx: WRITE PORTxRRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

clkI/O: I/O CLOCK

RDx: READ DDRx

D

L

Q

Q

SET

CLR

0

1

0

1

0

1

DIxn

AIOxn

DIEOExn

PVOVxn

PVOExn

DDOVxn

DDOExn

PUOExn

PUOVxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLEPUOVxn: Pxn PULL-UP OVERRIDE VALUEDDOExn: Pxn DATA DIRECTION OVERRIDE ENABLEDDOVxn: Pxn DATA DIRECTION OVERRIDE VALUEPVOExn: Pxn PORT VALUE OVERRIDE ENABLEPVOVxn: Pxn PORT VALUE OVERRIDE VALUE

DIxn: DIGITAL INPUT PIN n ON PORTxAIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx

RESET

RESET

Q

Q D

CLR

Q

Q D

CLR

Q

QD

CLR

PINxn

PORTxn

DDxn

DAT

A B

US

0

1DIEOVxn

SLEEP

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLEDIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUESLEEP: SLEEP CONTROL

Pxn

I/O

52 ATmega16(L) 2466E–AVR–10/02

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The following subsections shortly describe the alternate functions for each port, andrelate the overriding signals to the alternate function. Refer to the alternate functiondescription for further details.

Table 21. Generic Description of Overriding Signals for Alternate Functions

Signal Name Full Name Description

PUOE Pull-up Override Enable

If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when DDxn, PORTxn, PUD = 0b010.

PUOV Pull-up Override Value

If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.

DDOE Data Direction Override Enable

If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit.

DDOV Data Direction Override Value

If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit.

PVOE Port Value Override Enable

If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit.

PVOV Port Value Override Value

If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit.

DIEOE Digital Input Enable Override Enable

If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU-state (Normal Mode, sleep modes).

DIEOV Digital Input Enable Override Value

If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal Mode, sleep modes).

DI Digital Input This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer.

AIO Analog Input/ output This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally.

532466E–AVR–10/02

Special Function I/O Register – SFIOR

• Bit 2 – PUD: Pull-up disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxnand PORTxn Registers are configured to enable the pull-ups (DDxn, PORTxn = 0b01).See “Configuring the Pin” on page 48 for more details about this feature.

Alternate Functions of Port A Port A has an alternate function as analog input for the ADC as shown in Table 22. Ifsome Port A pins are configured as outputs, it is essential that these do not switch whena conversion is in progress. This might corrupt the result of the conversion.

Table 23 and Table 24 relate the alternate functions of Port A to the overriding signalsshown in Figure 26 on page 52.

Bit 7 6 5 4 3 2 1 0

ADTS2 ADTS1 ADTS0 ADHSM ACME PUD PSR2 PSR10 SFIOR



Table 22. Port A Pins Alternate Functions

Port Pin Alternate Function

PA7 ADC7 (ADC input channel 7)








Table 23. Overriding Signals for Alternate Functions in PA7..PA4

Signal Name PA7/ADC7 PA6/ADC6 PA5/ADC5 PA4/ADC4

PUOE 0 0 0 0

PUOV 0 0 0 0

DDOE 0 0 0 0

DDOV 0 0 0 0

PVOE 0 0 0 0

PVOV 0 0 0 0

DIEOE 0 0 0 0

DIEOV 0 0 0 0

DI – – – –

AIO ADC7 INPUT ADC6 INPUT ADC5 INPUT ADC4 INPUT

54 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 25.

The alternate pin configuration is as follows:

• SCK – Port B, Bit 7

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI isenabled as a Slave, this pin is configured as an input regardless of the setting of DDB7.When the SPI is enabled as a Master, the data direction of this pin is controlled byDDB7. When the pin is forced by the SPI to be an input, the pull-up can still be con-trolled by the PORTB7 bit.

• MISO – Port B, Bit 6

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI isenabled as a Master, this pin is configured as an input regardless of the setting ofDDB6. When the SPI is enabled as a Slave, the data direction of this pin is controlled by

Table 24. Overriding Signals for Alternate Functions in PA3..PA0

Signal Name PA3/ADC3 PA2/ADC2 PA1/ADC1 PA0/ADC0

PUOE 0 0 0 0

PUOV 0 0 0 0

DDOE 0 0 0 0

DDOV 0 0 0 0

PVOE 0 0 0 0

PVOV 0 0 0 0

DIEOE 0 0 0 0

DIEOV 0 0 0 0

DI – – – –

AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT

Table 25. Port B Pins Alternate Functions

Port Pin Alternate Functions

PB7 SCK (SPI Bus Serial Clock)

PB6 MISO (SPI Bus Master Input/Slave Output)

PB5 MOSI (SPI Bus Master Output/Slave Input)

PB4 SS (SPI Slave Select Input)

PB3AIN1 (Analog Comparator Negative Input)

OC0 (Timer/Counter0 Output Compare Match Output)

PB2AIN0 (Analog Comparator Positive Input)

INT2 (External Interrupt 2 Input)

PB1 T1 (Timer/Counter1 External Counter Input)

PB0T0 (Timer/Counter0 External Counter Input)XCK (USART External Clock Input/Output)

552466E–AVR–10/02

DDB6. When the pin is forced by the SPI to be an input, the pull-up can still be con-trolled by the PORTB6 bit.

• MOSI – Port B, Bit 5

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI isenabled as a Slave, this pin is configured as an input regardless of the setting of DDB5.When the SPI is enabled as a Master, the data direction of this pin is controlled byDDB5. When the pin is forced by the SPI to be an input, the pull-up can still be con-trolled by the PORTB5 bit.

• SS – Port B, Bit 4

SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as aninput regardless of the setting of DDB4. As a Slave, the SPI is activated when this pin isdriven low. When the SPI is enabled as a Master, the data direction of this pin is con-trolled by DDB4. When the pin is forced by the SPI to be an input, the pull-up can still becontrolled by the PORTB4 bit.

• AIN1/OC0 – Port B, Bit 3

AIN1, Analog Comparator Negative Input. Configure the port pin as input with the inter-nal pull-up switched off to avoid the digital port function from interfering with the functionof the analog comparator.

OC0, Output Compare Match output: The PB3 pin can serve as an external output forthe Timer/Counter0 Compare Match. The PB3 pin has to be configured as an output(DDB3 set (one)) to serve this function. The OC0 pin is also the output pin for the PWMmode timer function.

• AIN0/INT2 – Port B, Bit 2

AIN0, Analog Comparator Positive input. Configure the port pin as input with the internalpull-up switched off to avoid the digital port function from interfering with the function ofthe Analog Comparator.

INT2, External Interrupt Source 2: The PB2 pin can serve as an external interruptsource to the MCU.

• T1 – Port B, Bit 1

T1, Timer/Counter1 Counter Source.

• T0/XCK – Port B, Bit 0

T0, Timer/Counter0 Counter Source.

XCK, USART External Clock. The Data Direction Register (DDB0) controls whether theclock is output (DDB0 set) or input (DDB0 cleared). The XCK pin is active only when theUSART operates in Synchronous mode.

Table 26 and Table 27 relate the alternate functions of Port B to the overriding signalsshown in Figure 26 on page 52. SPI MSTR INPUT and SPI SLAVE OUTPUT constitutethe MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVEINPUT.

56 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Table 26. Overriding Signals for Alternate Functions in PB7..PB4

SignalName PB7/SCK PB6/MISO PB5/MOSI PB4/SS

PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR

PUOV PORTB7 • PUD PORTB6 • PUD PORTB5 • PUD PORTB4 • PUD

DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR

DDOV 0 0 0 0

PVOE SPE • MSTR SPE • MSTR SPE • MSTR 0

PVOV SCK OUTPUT SPI SLAVE OUTPUT SPI MSTR OUTPUT 0

DIEOE 0 0 0 0

DIEOV 0 0 0 0

DI SCK INPUT SPI MSTR INPUT SPI SLAVE INPUT SPI SS

AIO – – – –

Table 27. Overriding Signals for Alternate Functions in PB3..PB0

Signal Name PB3/OC0/AIN1 PB2/INT2/AIN0 PB1/T1 PB0/T0/XCK

PUOE 0 0 0 0

PUOV 0 0 0 0

DDOE 0 0 0 0

DDOV 0 0 0 0

PVOE OC0 ENABLE 0 0 UMSEL

PVOV OC0 0 0 XCK OUTPUT

DIEOE 0 INT2 ENABLE 0 0

DIEOV 0 1 0 0

DI – INT2 INPUT T1 INPUT XCK INPUT/T0 INPUT

AIO AIN1 INPUT AIN0 INPUT – –

572466E–AVR–10/02

Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 28. If the JTAG interface isenabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be acti-vated even if a reset occurs.


• TOSC2 – Port C, Bit 7

TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable asyn-chronous clocking of Timer/Counter2, pin PC7 is disconnected from the port, andbecomes the inverting output of the Oscillator amplifier. In this mode, a Crystal Oscillatoris connected to this pin, and the pin can not be used as an I/O pin.

• TOSC1 – Port C, Bit 6

TOSC1, Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable asyn-chronous clocking of Timer/Counter2, pin PC6 is disconnected from the port, andbecomes the input of the inverting Oscillator amplifier. In this mode, a Crystal Oscillatoris connected to this pin, and the pin can not be used as an I/O pin.

• TDI – Port C, Bit 5

TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register orData Register (scan chains). When the JTAG interface is enabled, this pin can not beused as an I/O pin.

• TDO – Port C, Bit 4

TDO, JTAG Test Data Out: Serial output data from Instruction register or Data Register.When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TMS – Port C, Bit 3

TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controllerstate machine. When the JTAG interface is enabled, this pin can not be used as an I/Opin.

• TCK – Port C, Bit 2

TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG inter-face is enabled, this pin can not be used as an I/O pin.

Table 28. Port C Pins Alternate Functions


PC7 TOSC2 (Timer Oscillator Pin 2)

PC6 TOSC1 (Timer Oscillator Pin 1)

PC5 TDI (JTAG Test Data In)

PC4 TDO (JTAG Test Data Out)

PC3 TMS (JTAG Test Mode Select)

PC2 TCK (JTAG Test Clock)

PC1 SDA (Two-wire Serial Bus Data Input/Output Line)

PC0 SCL (Two-wire Serial Bus Clock Line)

58 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

• SDA – Port C, Bit 1

SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) toenable the Two-wire Serial Interface, pin PC1 is disconnected from the port andbecomes the Serial Data I/O pin for the Two-wire Serial Interface. In this mode, there isa spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and thepin is driven by an open drain driver with slew-rate limitation. When this pin is used bythe Two-wire Serial Interface, the pull-up can still be controlled by the PORTC1 bit.

• SCL – Port C, Bit 0

SCL, Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) toenable the Two-wire Serial Interface, pin PC0 is disconnected from the port andbecomes the Serial Clock I/O pin for the Two-wire Serial Interface. In this mode, there isa spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and thepin is driven by an open drain driver with slew-rate limitation. When this pin is used bythe Two-wire Serial Interface, the pull-up can still be controlled by the PORTC0 bit.

Table 29 and Table 30 relate the alternate functions of Port C to the overriding signalsshown in Figure 26 on page 52.

Table 29. Overriding Signals for Alternate Functions in PC7..PC4

SignalName PC7/TOSC2 PC6/TOSC1 PC5/TDI PC4/TDO

PUOE AS2 AS2 JTAGEN JTAGEN

PUOV 0 0 1 0

DDOE AS2 AS2 JTAGEN JTAGEN

DDOV 0 0 0 SHIFT_IR + SHIFT_DR

PVOE 0 0 0 JTAGEN

PVOV 0 0 0 TDO

DIEOE AS2 AS2 JTAGEN JTAGEN

DIEOV 0 0 0 0

DI – – – –

AIO T/C2 OSC OUTPUT T/C2 OSC INPUT TDI –

592466E–AVR–10/02

Note: 1. When enabled, the Two-wire Serial Interface enables slew-rate controls on the outputpins PC0 and PC1. This is not shown in the figure. In addition, spike filters are con-nected between the AIO outputs shown in the port figure and the digital logic of theTWI module.

Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 31.


• OC2 – Port D, Bit 7

OC2, Timer/Counter2 Output Compare Match output: The PD7 pin can serve as anexternal output for the Timer/Counter2 Output Compare. The pin has to be configuredas an output (DDD7 set (one)) to serve this function. The OC2 pin is also the output pinfor the PWM mode timer function.

• ICP – Port D, Bit 6

ICP – Input Capture Pin: The PD6 pin can act as an Input Capture pin forTimer/Counter1.

Table 30. Overriding Signals for Alternate Functions in PC3..PC0(1)

Signal Name PC3/TMS PC2/TCK PC1/SDA PC0/SCL

PUOE JTAGEN JTAGEN TWEN TWEN

PUOV 1 1 PORTC1 • PUD PORTC0 • PUD

DDOE JTAGEN JTAGEN TWEN TWEN

DDOV 0 0 SDA_OUT SCL_OUT

PVOE 0 0 TWEN TWEN

PVOV 0 0 0 0

DIEOE JTAGEN JTAGEN 0 0

DIEOV 0 0 0 0

DI – – – –

AIO TMS TCK SDA INPUT SCL INPUT

Table 31. Port D Pins Alternate Functions


PD7 OC2 (Timer/Counter2 Output Compare Match Output)

PD6 ICP (Timer/Counter1 Input Capture Pin)

PD5 OC1A (Timer/Counter1 Output Compare A Match Output)

PD4 OC1B (Timer/Counter1 Output Compare B Match Output)

PD3 INT1 (External Interrupt 1 Input)

PD2 INT0 (External Interrupt 0 Input)

PD1 TXD (USART Output Pin)

PD0 RXD (USART Input Pin)

60 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

• OC1A – Port D, Bit 5

OC1A, Output Compare Match A output: The PD5 pin can serve as an external outputfor the Timer/Counter1 Output Compare A. The pin has to be configured as an output(DDD5 set (one)) to serve this function. The OC1A pin is also the output pin for thePWM mode timer function.

• OC1B – Port D, Bit 4

OC1B, Output Compare Match B output: The PD4 pin can serve as an external outputfor the Timer/Counter1 Output Compare B. The pin has to be configured as an output(DDD4 set (one)) to serve this function. The OC1B pin is also the output pin for thePWM mode timer function.

• INT1 – Port D, Bit 3

INT1, External Interrupt Source 1: The PD3 pin can serve as an external interruptsource.

• INT0 – Port D, Bit 2

INT0, External Interrupt Source 0: The PD2 pin can serve as an external interruptsource.

• TXD – Port D, Bit 1

TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter isenabled, this pin is configured as an output regardless of the value of DDD1.

• RXD – Port D, Bit 0

RXD, Receive Data (Data input pin for the USART). When the USART Receiver isenabled this pin is configured as an input regardless of the value of DDD0. When theUSART forces this pin to be an input, the pull-up can still be controlled by the PORTD0bit.

Table 32 and Table 33 relate the alternate functions of Port D to the overriding signalsshown in Figure 26 on page 52.

Table 32. Overriding Signals for Alternate Functions PD7..PD4

Signal Name PD7/OC2 PD6/ICP PD5/OC1A PD4/OC1B

PUOE 0 0 0 0

PUOV 0 0 0 0

DDOE 0 0 0 0

DDOV 0 0 0 0

PVOE OC2 ENABLE 0 OC1A ENABLE OC1B ENABLE

PVOV OC2 0 OC1A OC1B

DIEOE 0 0 0 0

DIEOV 0 0 0 0

DI – ICP INPUT – –

AIO – – – –

612466E–AVR–10/02

Register Description for I/O Ports

Port A Data Register – PORTA

Port A Data Direction Register – DDRA

Port A Input Pins Address – PINA

Port B Data Register – PORTB

Port B Data Direction Register – DDRB

Table 33. Overriding Signals for Alternate Functions in PD3..PD0

Signal Name PD3/INT1 PD2/INT0 PD1/TXD PD0/RXD

PUOE 0 0 TXEN RXEN

PUOV 0 0 0 PORTD0 • PUD

DDOE 0 0 TXEN RXEN

DDOV 0 0 1 0

PVOE 0 0 TXEN 0

PVOV 0 0 TXD 0

DIEOE INT1 ENABLE INT0 ENABLE 0 0

DIEOV 1 1 0 0

DI INT1 INPUT INT0 INPUT – RXD

AIO – – – –

Bit 7 6 5 4 3 2 1 0

PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA



Bit 7 6 5 4 3 2 1 0

DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA



Bit 7 6 5 4 3 2 1 0

PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA

Read/Write R R R R R R R R

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 7 6 5 4 3 2 1 0

PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB



Bit 7 6 5 4 3 2 1 0

DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB



62 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Port B Input Pins Address – PINB

Port C Data Register – PORTC

Port C Data Direction Register – DDRC

Port C Input Pins Address – PINC

Port D Data Register – PORTD

Port D Data Direction Register – DDRD

Port D Input Pins Address – PIND

Bit 7 6 5 4 3 2 1 0

PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB



Bit 7 6 5 4 3 2 1 0

PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC



Bit 7 6 5 4 3 2 1 0

DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC



Bit 7 6 5 4 3 2 1 0

PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC



Bit 7 6 5 4 3 2 1 0

PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD



Bit 7 6 5 4 3 2 1 0

DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD



Bit 7 6 5 4 3 2 1 0

PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND



632466E–AVR–10/02

External Interrupts The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, ifenabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs.This feature provides a way of generating a software interrupt. The external interruptscan be triggered by a falling or rising edge or a low level (INT2 is only an edge triggeredinterrupt). This is set up as indicated in the specification for the MCU Control Register –MCUCR – and MCU Control and Status Register – MCUCSR. When the external inter-rupt is enabled and is configured as level triggered (only INT0/INT1), the interrupt willtrigger as long as the pin is held low. Note that recognition of falling or rising edge inter-rupts on INT0 and INT1 requires the presence of an I/O clock, described in “ClockSystems and their Distribution” on page 22. Low level interrupts on INT0/INT1 and theedge interrupt on INT2 are detected asynchronously. This implies that these interruptscan be used for waking the part also from sleep modes other than Idle mode. The I/Oclock is halted in all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, thechanged level must be held for some time to wake up the MCU. This makes the MCUless sensitive to noise. The changed level is sampled twice by the Watchdog Oscillatorclock. The period of the Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C. Thefrequency of the Watchdog Oscillator is voltage dependent as shown in “Electrical Char-acteristics” on page 285. The MCU will wake up if the input has the required level duringthis sampling or if it is held until the end of the start-up time. The start-up time is definedby the SUT fuses as described in “System Clock and Clock Options” on page 22. If thelevel is sampled twice by the Watchdog Oscillator clock but disappears before the endof the start-up time, the MCU will still wake up, but no interrupt will be generated. Therequired level must be held long enough for the MCU to complete the wake up to triggerthe level interrupt.

MCU Control Register – MCUCR

The MCU Control Register contains control bits for interrupt sense control and generalMCU functions.

• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and thecorresponding interrupt mask in the GICR are set. The level and edges on the externalINT1 pin that activate the interrupt are defined in Table 34. The value on the INT1 pin issampled before detecting edges. If edge or toggle interrupt is selected, pulses that lastlonger than one clock period will generate an interrupt. Shorter pulses are not guaran-teed to generate an interrupt. If low level interrupt is selected, the low level must be helduntil the completion of the currently executing instruction to generate an interrupt.

Bit 7 6 5 4 3 2 1 0

SM2 SE SM1 SM0 ISC11 ISC10 ISC01 ISC00 MCUCR



Table 34. Interrupt 1 Sense Control

ISC11 ISC10 Description

0 0 The low level of INT1 generates an interrupt request.

0 1 Any logical change on INT1 generates an interrupt request.

1 0 The falling edge of INT1 generates an interrupt request.

1 1 The rising edge of INT1 generates an interrupt request.

64 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and thecorresponding interrupt mask are set. The level and edges on the external INT0 pin thatactivate the interrupt are defined in Table 35. The value on the INT0 pin is sampledbefore detecting edges. If edge or toggle interrupt is selected, pulses that last longerthan one clock period will generate an interrupt. Shorter pulses are not guaranteed togenerate an interrupt. If low level interrupt is selected, the low level must be held untilthe completion of the currently executing instruction to generate an interrupt.


• Bit 6 – ISC2: Interrupt Sense Control 2

The Asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREGI-bit and the corresponding interrupt mask in GICR are set. If ISC2 is written to zero, afalling edge on INT2 activates the interrupt. If ISC2 is written to one, a rising edge onINT2 activates the interrupt. Edges on INT2 are registered asynchronously. Pulses onINT2 wider than the minimum pulse width given in Table 36 will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt. When changing the ISC2bit, an interrupt can occur. Therefore, it is recommended to first disable INT2 by clearingits Interrupt Enable bit in the GICR Register. Then, the ISC2 bit can be changed. Finally,the INT2 Interrupt Flag should be cleared by writing a logical one to its Interrupt Flag bit(INTF2) in the GIFR Register before the interrupt is re-enabled.

General Interrupt Control Register – GICR

• Bit 7 – INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and

Table 35. Interrupt 0 Sense Control

ISC01 ISC00 Description

0 0 The low level of INT0 generates an interrupt request.

0 1 Any logical change on INT0 generates an interrupt request.

1 0 The falling edge of INT0 generates an interrupt request.

1 1 The rising edge of INT0 generates an interrupt request.

Bit 7 6 5 4 3 2 1 0




Table 36. Asynchronous External Interrupt Characteristics


tINTMinimum pulse width for asynchronous external interrupt

50 ns

Bit 7 6 5 4 3 2 1 0

INT1 INT0 INT2 – – – IVSEL IVCE GICR

Read/Write R/W R/W R/W R R R R/W R/W


652466E–AVR–10/02

ISC10) in the MCU General Control Register (MCUCR) define whether the ExternalInterrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activityon the pin will cause an interrupt request even if INT1 is configured as an output. Thecorresponding interrupt of External Interrupt Request 1 is executed from the INT1 inter-rupt Vector.


When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 andISC00) in the MCU General Control Register (MCUCR) define whether the ExternalInterrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activityon the pin will cause an interrupt request even if INT0 is configured as an output. Thecorresponding interrupt of External Interrupt Request 0 is executed from the INT0 inter-rupt vector.


When the INT2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),the external pin interrupt is enabled. The Interrupt Sense Control2 bit (ISC2) in the MCUControl and Status Register (MCUCSR) defines whether the External Interrupt is acti-vated on rising or falling edge of the INT2 pin. Activity on the pin will cause an interruptrequest even if INT2 is configured as an output. The corresponding interrupt of ExternalInterrupt Request 2 is executed from the INT2 Interrupt Vector.

General Interrupt Flag Register – GIFR

• Bit 7 – INTF1: External Interrupt Flag 1

When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1becomes set (one). If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCUwill jump to the corresponding Interrupt Vector. The flag is cleared when the interruptroutine is executed. Alternatively, the flag can be cleared by writing a logical one to it.This flag is always cleared when INT1 is configured as a level interrupt.


When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0becomes set (one). If the I-bit in SREG and the INT0 bit in GICR are set (one), the MCUwill jump to the corresponding interrupt vector. The flag is cleared when the interruptroutine is executed. Alternatively, the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt.


When an event on the INT2 pin triggers an interrupt request, INTF2 becomes set (one).If the I-bit in SREG and the INT2 bit in GICR are set (one), the MCU will jump to the cor-responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.Alternatively, the flag can be cleared by writing a logical one to it. Note that when enter-ing some sleep modes with the INT2 interrupt disabled, the input buffer on this pin willbe disabled. This may cause a logic change in internal signals which will set the INTF2flag. See “Digital Input Enable and Sleep Modes” on page 51 for more information.

Bit 7 6 5 4 3 2 1 0

INTF1 INTF0 INTF2 – – – – – GIFR

Read/Write R/W R/W R/W R R R R R


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8-bit Timer/Counter0 with PWM

Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. Themain features are:• Single Channel Counter• Clear Timer on Compare Match (Auto Reload)• Glitch-free, Phase Correct Pulse Width Modulator (PWM)• Frequency Generator• External Event Counter• 10-bit Clock Prescaler• Overflow and Compare Match Interrupt Sources (TOV0 and OCF0)

Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 27. For theactual placement of I/O pins, refer to “Pinouts ATmega16” on page 2. CPU accessibleI/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/Oregister and bit locations are listed in the “8-bit Timer/Counter Register Description” onpage 77.

Figure 27. 8-bit Timer/Counter Block Diagram

Registers The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers.Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the TimerInterrupt Flag Register (TIFR). All interrupts are individually masked with the TimerInterrupt Mask register (TIMSK). TIFR and TIMSK are not shown in the figure sincethese registers are shared by other timer units.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clocksource on the T0 pin. The Clock Select logic block controls which clock source and edgethe Timer/Counter uses to increment (or decrement) its value. The Timer/Counter isinactive when no clock source is selected. The output from the Clock Select logic isreferred to as the timer clock (clkT0).

Timer/Counter

DAT

AB

US

=

TCNTn

WaveformGeneration

OCn

= 0

Control Logic

= 0xFF

BOTTOM

count

clear

direction

TOVn(Int.Req.)

OCRn

TCCRn

Clock Select

TnEdge

Detector

( From Prescaler )

clkTn

TOP

OCn(Int.Req.)

672466E–AVR–10/02

The double buffered Output Compare Register (OCR0) is compared with theTimer/Counter value at all times. The result of the compare can be used by the wave-form generator to generate a PWM or variable frequency output on the Output ComparePin (OC0). See “Output Compare Unit” on page 69. for details. The compare matchevent will also set the Compare Flag (OCF0) which can be used to generate an outputcompare interrupt request.

Definitions Many register and bit references in this document are written in general form. A lowercase “n” replaces the Timer/Counter number, in this case 0. However, when using theregister or bit defines in a program, the precise form must be used i.e., TCNT0 foraccessing Timer/Counter0 counter value and so on.

The definitions in Table 37 are also used extensively throughout the document.

Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clocksource is selected by the clock select logic which is controlled by the clock select(CS02:0) bits located in the Timer/Counter Control Register (TCCR0). For details onclock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” onpage 81.

Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.Figure 28 shows a block diagram of the counter and its surroundings.

Figure 28. Counter Unit Block Diagram

Signal description (internal signals):

count Increment or decrement TCNT0 by 1.

direction Select between increment and decrement.

clear Clear TCNT0 (set all bits to zero).

clkTn Timer/Counter clock, referred to as clkT0 in the following.

TOP Signalize that TCNT0 has reached maximum value.

Table 37. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x00.

MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP The counter reaches the TOP when it becomes equal to the highestvalue in the count sequence. The TOP value can be assigned to be thefixed value 0xFF (MAX) or the value stored in the OCR0 register. Theassignment is dependent on the mode of operation.

DATA BUS

TCNTn Control Logic

count

TOVn(Int. Req.)

Clock Select

TOP

TnEdge

Detector

( From Prescaler )

clkTn

BOTTOM

direction

clear

68 ATmega16(L) 2466E–AVR–10/02

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BOTTOM Signalize that TCNT0 has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or dec-remented at each timer clock (clkT0). clkT0 can be generated from an external or internalclock source, selected by the Clock Select bits (CS02:0). When no clock source isselected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessedby the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (haspriority over) all counter clear or count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bitslocated in the Timer/Counter Control Register (TCCR0). There are close connectionsbetween how the counter behaves (counts) and how waveforms are generated on theOutput Compare output OC0. For more details about advanced counting sequencesand waveform generation, see “Modes of Operation” on page 71.

The Timer/Counter Overflow (TOV0) flag is set according to the mode of operationselected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.

Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Register(OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match. A match willset the Output Compare Flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 =1 and Global Interrupt Flag in SREG is set), the Output Compare Flag generates an out-put compare interrupt. The OCF0 flag is automatically cleared when the interrupt isexecuted. Alternatively, the OCF0 flag can be cleared by software by writing a logicalone to its I/O bit location. The waveform generator uses the match signal to generate anoutput according to operating mode set by the WGM01:0 bits and Compare Outputmode (COM01:0) bits. The max and bottom signals are used by the waveform generatorfor handling the special cases of the extreme values in some modes of operation (See“Modes of Operation” on page 71.).

Figure 29 shows a block diagram of the output compare unit.

Figure 29. Output Compare Unit, Block Diagram

OCFn (Int.Req.)

= (8-bit Comparator )

OCRn

OCn

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMn1:0

bottom

692466E–AVR–10/02

The OCR0 Register is double buffered when using any of the Pulse Width Modulation(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation,the double buffering is disabled. The double buffering synchronizes the update of theOCR0 Compare Register to either top or bottom of the counting sequence. The synchro-nization prevents the occurrence of odd-length, non-symmetrical PWM pulses, therebymaking the output glitch-free.

The OCR0 Register access may seem complex, but this is not case. When the doublebuffering is enabled, the CPU has access to the OCR0 Buffer Register, and if doublebuffering is disabled the CPU will access the OCR0 directly.

Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can beforced by writing a one to the Force Output Compare (FOC0) bit. Forcing comparematch will not set the OCF0 flag or reload/clear the timer, but the OC0 pin will beupdated as if a real compare match had occurred (the COM01:0 bits settings definewhether the OC0 pin is set, cleared or toggled).

Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any compare match thatoccur in the next timer clock cycle, even when the timer is stopped. This feature allowsOCR0 to be initialized to the same value as TCNT0 without triggering an interrupt whenthe Timer/Counter clock is enabled.

Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all compare matches for onetimer clock cycle, there are risks involved when changing TCNT0 when using the outputcompare channel, independently of whether the Timer/Counter is running or not. If thevalue written to TCNT0 equals the OCR0 value, the compare match will be missed,resulting in incorrect waveform generation. Similarly, do not write the TCNT0 valueequal to BOTTOM when the counter is downcounting.

The setup of the OC0 should be performed before setting the Data Direction Register forthe port pin to output. The easiest way of setting the OC0 value is to use the Force Out-put Compare (FOC0) strobe bits in Normal mode. The OC0 Register keeps its valueeven when changing between waveform generation modes.

Be aware that the COM01:0 bits are not double buffered together with the comparevalue. Changing the COM01:0 bits will take effect immediately.

Compare Match Output Unit

The Compare Output mode (COM01:0) bits have two functions. The Waveform Genera-tor uses the COM01:0 bits for defining the Output Compare (OC0) state at the nextcompare match. Also, the COM01:0 bits control the OC0 pin output source. Figure 30shows a simplified schematic of the logic affected by the COM01:0 bit setting. The I/ORegisters, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of thegeneral I/O port Control Registers (DDR and PORT) that are affected by the COM01:0bits are shown. When referring to the OC0 state, the reference is for the internal OC0Register, not the OC0 pin. If a System Reset occur, the OC0 Register is reset to “0”.

70 ATmega16(L) 2466E–AVR–10/02

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Figure 30. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OC0) from theWaveform Generator if either of the COM01:0 bits are set. However, the OC0 pin direc-tion (input or output) is still controlled by the Data Direction Register (DDR) for the portpin. The Data Direction Register bit for the OC0 pin (DDR_OC0) must be set as outputbefore the OC0 value is visible on the pin. The port override function is independent ofthe Waveform Generation mode.

The design of the output compare pin logic allows initialization of the OC0 state beforethe output is enabled. Note that some COM01:0 bit settings are reserved for certainmodes of operation. See “8-bit Timer/Counter Register Description” on page 77.

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM01:0 bits differently in normal, CTC, and PWMmodes. For all modes, setting the COM01:0 = 0 tells the waveform generator that noaction on the OC0 Register is to be performed on the next compare match. For compareoutput actions in the non-PWM modes refer to Table 39 on page 78. For fast PWMmode, refer to Table 40 on page 78, and for phase correct PWM refer to Table 41 onpage 79.

A change of the COM01:0 bits state will have effect at the first compare match after thebits are written. For non-PWM modes, the action can be forced to have immediate effectby using the FOC0 strobe bits.

Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Comparepins, is defined by the combination of the Waveform Generation mode (WGM01:0) andCompare Output mode (COM01:0) bits. The Compare Output mode bits do not affectthe counting sequence, while the Waveform Generation mode bits do. The COM01:0bits control whether the PWM output generated should be inverted or not (inverted ornon-inverted PWM). For non-PWM modes the COM01:0 bits control whether the outputshould be set, cleared, or toggled at a compare match (See “Compare Match OutputUnit” on page 70.).

For detailed timing information refer to Figure 34, Figure 35, Figure 36 and Figure 37 in“Timer/Counter Timing Diagrams” on page 75.

PORT

DDR

D Q

D Q

OCnPinOCn

D QWaveformGenerator

COMn1

COMn0

0

1

DAT

A B

US

FOCn

clkI/O

712466E–AVR–10/02

Normal Mode The simplest mode of operation is the normal mode (WGM01:0 = 0). In this mode thecounting direction is always up (incrementing), and no counter clear is performed. Thecounter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and thenrestarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag(TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0flag in this case behaves like a ninth bit, except that it is only set, not cleared. However,combined with the timer overflow interrupt that automatically clears the TOV0 flag, thetimer resolution can be increased by software. There are no special cases to consider inthe normal mode, a new counter value can be written anytime.

The output compare unit can be used to generate interrupts at some given time. Usingthe output compare to generate waveforms in Normal mode is not recommended, sincethis will occupy too much of the CPU time.

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used tomanipulate the counter resolution. In CTC mode the counter is cleared to zero when thecounter value (TCNT0) matches the OCR0. The OCR0 defines the top value for thecounter, hence also its resolution. This mode allows greater control of the comparematch output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 31. The counter value(TCNT0) increases until a compare match occurs between TCNT0 and OCR0, and thencounter (TCNT0) is cleared.

Figure 31. CTC Mode, Timing Diagram

An interrupt can be generated each time the counter value reaches the TOP value byusing the OCF0 flag. If the interrupt is enabled, the interrupt handler routine can be usedfor updating the TOP value. However, changing TOP to a value close to BOTTOM whenthe counter is running with none or a low prescaler value must be done with care sincethe CTC mode does not have the double buffering feature. If the new value written toOCR0 is lower than the current value of TCNT0, the counter will miss the comparematch. The counter will then have to count to its maximum value (0xFF) and wraparound starting at 0x00 before the compare match can occur.

For generating a waveform output in CTC mode, the OC0 output can be set to toggle itslogical level on each compare match by setting the Compare Output mode bits to togglemode (COM01:0 = 1). The OC0 value will not be visible on the port pin unless the datadirection for the pin is set to output. The waveform generated will have a maximum fre-

TCNTn

OCn(Toggle)

OCn Interrupt Flag Set

1 4Period 2 3

(COMn1:0 = 1)

72 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

quency of fOC0 = fclk_I/O/2 when OCR0 is set to zero (0x00). The waveform frequency isdefined by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV0 flag is set in the same timer clock cyclethat the counter counts from MAX to 0x00.

Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high fre-quency PWM waveform generation option. The fast PWM differs from the other PWMoption by its single-slope operation. The counter counts from BOTTOM to MAX thenrestarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare(OC0) is cleared on the compare match between TCNT0 and OCR0, and set at BOT-TOM. In inverting Compare Output mode, the output is set on compare match andcleared at BOTTOM. Due to the single-slope operation, the operating frequency of thefast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for powerregulation, rectification, and DAC applications. High frequency allows physically smallsized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the MAXvalue. The counter is then cleared at the following timer clock cycle. The timing diagramfor the fast PWM mode is shown in Figure 32. The TCNT0 value is in the timing diagramshown as a histogram for illustrating the single-slope operation. The diagram includesnon-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0slopes represent compare matches between OCR0 and TCNT0.

Figure 32. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. Ifthe interrupt is enabled, the interrupt handler routine can be used for updating the com-pare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0pin. Setting the COM01:0 bits to 2 will produce a non-inverted PWM and an invertedPWM output can be generated by setting the COM01:0 to 3 (See Table 40 on page 78).The actual OC0 value will only be visible on the port pin if the data direction for the port

fOCn

fclk_I/O

2 N 1 OCRn+( )⋅ ⋅-----------------------------------------------=

TCNTn

OCRn Update andTOVn Interrupt Flag Set

1Period 2 3

OCn

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Interrupt Flag Set

4 5 6 7

732466E–AVR–10/02

pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0register at the compare match between OCR0 and TCNT0, and clearing (or setting) theOC0 Register at the timer clock cycle the counter is cleared (changes from MAX toBOTTOM).

The PWM frequency for the output can be calculated by the following equation:


The extreme values for the OCR0 Register represents special cases when generating aPWM waveform output in the fast PWM mode. If the OCR0 is set equal to BOTTOM, theoutput will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0 equalto MAX will result in a constantly high or low output (depending on the polarity of the out-put set by the COM01:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achievedby setting OC0 to toggle its logical level on each compare match (COM01:0 = 1). Thewaveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0 isset to zero. This feature is similar to the OC0 toggle in CTC mode, except the doublebuffer feature of the output compare unit is enabled in the fast PWM mode.

Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correctPWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then fromMAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0)is cleared on the compare match between TCNT0 and OCR0 while upcounting, and seton the compare match while downcounting. In inverting Output Compare mode, theoperation is inverted. The dual-slope operation has lower maximum operation frequencythan single slope operation. However, due to the symmetric feature of the dual-slopePWM modes, these modes are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phasecorrect PWM mode the counter is incremented until the counter value matches MAX.When the counter reaches MAX, it changes the count direction. The TCNT0 value willbe equal to MAX for one timer clock cycle. The timing diagram for the phase correctPWM mode is shown on Figure 33. The TCNT0 value is in the timing diagram shown asa histogram for illustrating the dual-slope operation. The diagram includes non-invertedand inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes repre-sent compare matches between OCR0 and TCNT0.

fOCnPWM

fclk_I/O

N 256⋅------------------=

74 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 33. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOT-TOM. The interrupt flag can be used to generate an interrupt each time the counterreaches the BOTTOM value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms onthe OC0 pin. Setting the COM01:0 bits to 2 will produce a non-inverted PWM. Aninverted PWM output can be generated by setting the COM01:0 to 3 (see Table 41 onpage 79). The actual OC0 value will only be visible on the port pin if the data directionfor the port pin is set as output. The PWM waveform is generated by clearing (or setting)the OC0 Register at the compare match between OCR0 and TCNT0 when the counterincrements, and setting (or clearing) the OC0 Register at compare match betweenOCR0 and TCNT0 when the counter decrements. The PWM frequency for the outputwhen using phase correct PWM can be calculated by the following equation:


The extreme values for the OCR0 Register represent special cases when generating aPWM waveform output in the phase correct PWM mode. If the OCR0 is set equal toBOTTOM, the output will be continuously low and if set equal to MAX the output will becontinuously high for non-inverted PWM mode. For inverted PWM the output will havethe opposite logic values.

Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT0) is thereforeshown as a clock enable signal in the following figures. The figures include informationon when interrupt flags are set. Figure 34 contains timing data for basic Timer/Counteroperation. The figure shows the count sequence close to the MAX value in all modesother than phase correct PWM mode.

TOVn Interrupt Flag Set


1 2 3

TCNTn

Period

OCn

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Update

fOCnPCPWM

fclk_I/O

N 510⋅------------------=

752466E–AVR–10/02

Figure 34. Timer/Counter Timing Diagram, no Prescaling

Figure 35 shows the same timing data, but with the prescaler enabled.

Figure 35. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

Figure 36 shows the setting of OCF0 in all modes except CTC mode.

Figure 36. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8)

clkTn(clkI/O/1)

TOVn

clkI/O

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

TOVn


clkI/O

clkTn(clkI/O/8)

OCFn

OCRn

TCNTn

OCRn Value

OCRn - 1 OCRn OCRn + 1 OCRn + 2

clkI/O

clkTn(clkI/O/8)

76 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 37 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.

Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, withPrescaler (fclk_I/O/8)

8-bit Timer/Counter Register Description

Timer/Counter Control Register – TCCR0

• Bit 7 – FOC0: Force Output Compare

The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However,for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 iswritten when operating in PWM mode. When writing a logical one to the FOC0 bit, animmediate compare match is forced on the Waveform Generation unit. The OC0 outputis changed according to its COM01:0 bits setting. Note that the FOC0 bit is implementedas a strobe. Therefore it is the value present in the COM01:0 bits that determines theeffect of the forced compare.

A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC modeusing OCR0 as TOP.

The FOC0 bit is always read as zero.

• Bit 6, 3 – WGM01:0: Waveform Generation Mode

These bits control the counting sequence of the counter, the source for the maximum(TOP) counter value, and what type of Waveform Generation to be used. Modes ofoperation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Com-pare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. SeeTable 38 and “Modes of Operation” on page 71.

OCFn

OCRn

TCNTn(CTC)

TOP

TOP - 1 TOP BOTTOM BOTTOM + 1

clkI/O

clkTn(clkI/O/8)

Bit 7 6 5 4 3 2 1 0

FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 TCCR0

Read/Write W R/W R/W R/W R/W R/W R/W R/W


772466E–AVR–10/02

Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-initions. However, the functionality and location of these bits are compatible withprevious versions of the timer.

• Bit 5:4 – COM01:0: Compare Match Output Mode

These bits control the Output Compare pin (OC0) behavior. If one or both of theCOM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/Opin it is connected to. However, note that the Data Direction Register (DDR) bit corre-sponding to the OC0 pin must be set in order to enable the output driver.

When OC0 is connected to the pin, the function of the COM01:0 bits depends on theWGM01:0 bit setting. Table 39 shows the COM01:0 bit functionality when the WGM01:0bits are set to a normal or CTC mode (non-PWM).

Table 40 shows the COM01:0 bit functionality when the WGM01:0 bits are set to fastPWM mode.

Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, thecompare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode”on page 73 for more details.

Table 41 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phasecorrect PWM mode.

Table 38. Waveform Generation Mode Bit Description(1)

ModeWGM01(CTC0)

WGM00(PWM0)

Timer/Counter Mode of Operation TOP

Update ofOCR0

TOV0 FlagSet-on

0 0 0 Normal 0xFF Immediate MAX

1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM

2 1 0 CTC OCR0 Immediate MAX

3 1 1 Fast PWM 0xFF TOP MAX

Table 39. Compare Output Mode, non-PWM Mode

COM01 COM00 Description

0 0 Normal port operation, OC0 disconnected.

0 1 Toggle OC0 on compare match

1 0 Clear OC0 on compare match

1 1 Set OC0 on compare match

Table 40. Compare Output Mode, Fast PWM Mode(1)



0 1 Reserved

1 0 Clear OC0 on compare match, set OC0 at TOP

1 1 Set OC0 on compare match, clear OC0 at TOP

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Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, thecompare match is ignored, but the set or clear is done at TOP. See “Phase CorrectPWM Mode” on page 74 for more details.

• Bit 2:0 – CS02:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin willclock the counter even if the pin is configured as an output. This feature allows softwarecontrol of the counting.

Timer/Counter Register – TCNT0

The Timer/Counter Register gives direct access, both for read and write operations, tothe Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes)the compare match on the following timer clock. Modifying the counter (TCNT0) whilethe counter is running, introduces a risk of missing a compare match between TCNT0and the OCR0 Register.

Table 41. Compare Output Mode, Phase Correct PWM Mode(1)



0 1 Reserved

1 0 Clear OC0 on compare match when up-counting. Set OC0 on compare match when downcounting.

1 1 Set OC0 on compare match when up-counting. Clear OC0 on compare match when downcounting.

Table 42. Clock Select Bit Description

CS02 CS01 CS00 Description

0 0 0 No clock source (Timer/Counter stopped).

0 0 1 clkI/O/(No prescaling)

0 1 0 clkI/O/8 (From prescaler)




1 1 0 External clock source on T0 pin. Clock on falling edge.

1 1 1 External clock source on T0 pin. Clock on rising edge.

Bit 7 6 5 4 3 2 1 0

TCNT0[7:0] TCNT0



792466E–AVR–10/02

Output Compare Register – OCR0

The Output Compare Register contains an 8-bit value that is continuously comparedwith the counter value (TCNT0). A match can be used to generate an output compareinterrupt, or to generate a waveform output on the OC0 pin.

Timer/Counter Interrupt Mask Register – TIMSK

• Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable

When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), theTimer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt isexecuted if a compare match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set inthe Timer/Counter Interrupt Flag Register – TIFR.

• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), theTimer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed ifan overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in theTimer/Counter Interrupt Flag Register – TIFR.

Timer/Counter Interrupt Flag Register – TIFR

• Bit 1 – OCF0: Output Compare Flag 0

The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0and the data in OCR0 – Output Compare Register0. OCF0 is cleared by hardware whenexecuting the corresponding interrupt handling vector. Alternatively, OCF0 is cleared bywriting a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Com-pare Match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 CompareMatch Interrupt is executed.

• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is clearedby hardware when executing the corresponding interrupt handling vector. Alternatively,TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0(Timer/Counter0 Overf low Interrupt Enable), and TOV0 are set (one), theTimer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit isset when Timer/Counter0 changes counting direction at $00.

Bit 7 6 5 4 3 2 1 0

OCR0[7:0] OCR0



Bit 7 6 5 4 3 2 1 0

OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 TIMSK



Bit 7 6 5 4 3 2 1 0

OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 TIFR



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Timer/Counter0 and Timer/Counter1 Prescalers

Timer/Counter1 and Timer/Counter0 share the same prescaler module, but theTimer/Counters can have different prescaler settings. The description below applies toboth Timer/Counter1 and Timer/Counter0.

Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 =1). This provides the fastest operation, with a maximum Timer/Counter clock frequencyequal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the pres-caler can be used as a clock source. The prescaled clock has a frequency of eitherfCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024.

Prescaler Reset The prescaler is free running, i.e., operates independently of the clock select logic of theTimer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the pres-caler is not affected by the Timer/Counter’s clock select, the state of the prescaler willhave implications for situations where a prescaled clock is used. One example of pres-caling artifacts occurs when the timer is enabled and clocked by the prescaler (6 >CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to thefirst count occurs can be from 1 to N+1 system clock cycles, where N equals the pres-caler divisor (8, 64, 256, or 1024).

It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to programexecution. However, care must be taken if the other Timer/Counter that shares thesame prescaler also uses prescaling. A prescaler reset will affect the prescaler periodfor all Timer/Counters it is connected to.

External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock(clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin syn-chronization logic. The synchronized (sampled) signal is then passed through the edgedetector. Figure 38 shows a functional equivalent block diagram of the T1/T0 synchroni-zation and edge detector logic. The registers are clocked at the positive edge of theinternal system clock (clkI/O). The latch is transparent in the high period of the internalsystem clock.

The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or neg-ative (CSn2:0 = 6) edge it detects.

Figure 38. T1/T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 systemclock cycles from an edge has been applied to the T1/T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when T1/T0 has been stable forat least one system clock cycle, otherwise it is a risk that a false Timer/Counter clockpulse is generated.

Each half period of the external clock applied must be longer than one system clockcycle to ensure correct sampling. The external clock must be guaranteed to have less

Tn_sync(To ClockSelect Logic)

Edge DetectorSynchronization

D QD Q

LE

D QTn

clkI/O

812466E–AVR–10/02

than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Sincethe edge detector uses sampling, the maximum frequency of an external clock it candetect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,resonator, and capacitors) tolerances, it is recommended that maximum frequency of anexternal clock source is less than fclk_I/O/2.5.

An external clock source can not be prescaled.

Figure 39. Prescaler for Timer/Counter0 and Timer/Counter1(1)

Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 38.

Special Function IO Register – SFIOR

• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0

When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will bereset. The bit will be cleared by hardware after the operation is performed. Writing azero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 sharethe same prescaler and a reset of this prescaler will affect both timers. This bit willalways be read as zero.

PSR10

Clear

clkT1 clkT0

T1

T0

clkI/O

Synchronization

Synchronization

Bit 7 6 5 4 3 2 1 0




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16-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event man-agement), wave generation, and signal timing measurement. The main features are:• True 16-bit Design (i.e., Allows 16-bit PWM)• Two Independent Output Compare Units• Double Buffered Output Compare Registers• One Input Capture Unit• Input Capture Noise Canceler• Clear Timer on Compare Match (Auto Reload)• Glitch-free, Phase Correct Pulse Width Modulator (PWM)• Variable PWM Period• Frequency Generator• External Event Counter• Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)

Overview Most register and bit references in this document are written in general form. A lowercase “n” replaces the Timer/Counter number, and a lower case “x” replaces the outputcompare unit channel. However, when using the register or bit defines in a program, theprecise form must be used (i.e., TCNT1 for accessing Timer/Counter1 counter valueand so on). The physical I/O Register and bit locations for ATmega16 are listed in the“16-bit Timer/Counter Register Description” on page 104.

A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 40. CPUaccessible I/O Registers, including I/O bits and I/O pins, are shown in bold.

832466E–AVR–10/02

Figure 40. 16-bit Timer/Counter Block Diagram(1)

Note: 1. Refer to Figure 1 on page 2, Table 25 on page 55, and Table 31 on page 60 forTimer/Counter1 pin placement and description.

Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input CaptureRegister (ICR1) are all 16-bit registers. Special procedures must be followed whenaccessing the 16-bit registers. These procedures are described in the section “Access-ing 16-bit Registers” on page 86. The Timer/Counter Control Registers (TCCR1A/B) are8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated toInt.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR).All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK).TIFR and TIMSK are not shown in the figure since these registers are shared by othertimer units.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clocksource on the T1 pin. The Clock Select logic block controls which clock source and edgethe Timer/Counter uses to increment (or decrement) its value. The Timer/Counter isinactive when no clock source is selected. The output from the clock select logic isreferred to as the timer clock (clkT1).

The double buffered Output Compare Registers (OCR1A/B) are compared with theTimer/Counter value at all time. The result of the compare can be used by the WaveformGenerator to generate a PWM or variable frequency output on the Output Compare pin

Clock Select

Timer/Counter

DAT

AB

US

OCRnA

OCRnB

ICRn

=

=

TCNTn

WaveformGeneration

WaveformGeneration

OCnA

OCnB

NoiseCanceler

ICPn

=

FixedTOP

Values

EdgeDetector

Control Logic

= 0

TOP BOTTOM

Count

Clear

Direction

TOVn(Int.Req.)

OCnA(Int.Req.)

OCnB(Int.Req.)

ICFn (Int.Req.)

TCCRnA TCCRnB

( From AnalogComparator Ouput )

TnEdge

Detector

( From Prescaler )

clkTn

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(OC1A/B). See “Output Compare Units” on page 91. The compare match event will alsoset the Compare Match Flag (OCF1A/B) which can be used to generate an output com-pare interrupt request.

The Input Capture Register can capture the Timer/Counter value at a given external(edge triggered) event on either the Input Capture Pin (ICP1) or on the Analog Compar-ator pins (See “Analog Comparator” on page 195.) The input capture unit includes adigital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation bedefined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values.When using OCR1A as TOP value in a PWM mode, the OCR1A Register can not beused for generating a PWM output. However, the TOP value will in this case be doublebuffered allowing the TOP value to be changed in run time. If a fixed TOP value isrequired, the ICR1 Register can be used as an alternative, freeing the OCR1A to beused as PWM output.

Definitions The following definitions are used extensively throughout the document:

Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of the16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlierversion regarding:

• All 16-bit Timer/Counter related I/O Register address locations, including timer interrupt registers.

• Bit locations inside all 16-bit Timer/Counter Registers, including timer interrupt registers.

• Interrupt Vectors.

The following control bits have changed name, but have same functionality and registerlocation:

• PWM10 is changed to WGM10.

• PWM11 is changed to WGM11.

• CTC1 is changed to WGM12.

The following bits are added to the 16-bit Timer/Counter Control Registers:

• FOC1A and FOC1B are added to TCCR1A.

• WGM13 is added to TCCR1B.

The 16-bit Timer/Counter has improvements that will affect the compatibility in somespecial cases.


BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.

MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 regis-ter. The assignment is dependent of the mode of operation.

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Accessing 16-bit Registers

The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVRCPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read orwrite operations. Each 16-bit timer has a single 8-bit register for temporary storing of thehigh byte of the 16-bit access. The same temporary register is shared between all 16-bitregisters within each 16-bit timer. Accessing the low byte triggers the 16-bit read or writeoperation. When the low byte of a 16-bit register is written by the CPU, the high bytestored in the temporary register, and the low byte written are both copied into the 16-bitregister in the same clock cycle. When the low byte of a 16-bit register is read by theCPU, the high byte of the 16-bit register is copied into the temporary register in thesame clock cycle as the low byte is read.

Not all 16-bit accesses uses the temporary register for the high byte. Reading theOCR1A/B 16-bit registers does not involve using the temporary register.

To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read,the low byte must be read before the high byte.

The following code examples show how to access the 16-bit timer registers assumingthat no interrupts updates the temporary register. The same principle can be useddirectly for accessing the OCR1A/B and ICR1 registers. Note that when using “C”, thecompiler handles the 16-bit access.

Note: 1. The example code assumes that the part specific header file is included.

The assembly code example returns the TCNT1 value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an inter-rupt occurs between the two instructions accessing the 16-bit register, and the interruptcode updates the temporary register by accessing the same or any other of the 16-bittimer registers, then the result of the access outside the interrupt will be corrupted.Therefore, when both the main code and the interrupt code update the temporary regis-ter, the main code must disable the interrupts during the 16-bit access.


...

; Set TCNT1 to 0x01FF

ldi r17,0x01

ldi r16,0xFF

out TCNT1H,r17

out TCNT1L,r16

; Read TCNT1 into r17:r16

in r16,TCNT1L

in r17,TCNT1H

...

C Code Example(1)

unsigned int i;

...

/* Set TCNT1 to 0x01FF */

TCNT1 = 0x1FF;

/* Read TCNT1 into i */

i = TCNT1;

...

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The following code examples show how to do an atomic read of the TCNT1 Registercontents. Reading any of the OCR1A/B or ICR1 Registers can be done by using thesame principle.


The assembly code example returns the TCNT1 value in the r17:r16 register pair.


TIM16_ReadTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Read TCNT1 into r17:r16

in r16,TCNT1L

in r17,TCNT1H

; Restore global interrupt flag

out SREG,r18

ret

C Code Example(1)

unsigned int TIM16_ReadTCNT1( void )

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Read TCNT1 into i */

i = TCNT1;

/* Restore global interrupt flag */

SREG = sreg;

return i;

872466E–AVR–10/02

The following code examples show how to do an atomic write of the TCNT1 Registercontents. Writing any of the OCR1A/B or ICR1 Registers can be done by using thesame principle.


The assembly code example requires that the r17:r16 register pair contains the value tobe written to TCNT1.

Reusing the Temporary High Byte Register

If writing to more than one 16-bit register where the high byte is the same for all registerswritten, then the high byte only needs to be written once. However, note that the samerule of atomic operation described previously also applies in this case.


The Timer/Counter can be clocked by an internal or an external clock source. The clocksource is selected by the Clock Select logic which is controlled by the Clock Select(CS12:0) bits located in the Timer/Counter Control Register B (TCCR1B). For details onclock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” onpage 81.

Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directionalcounter unit. Figure 41 shows a block diagram of the counter and its surroundings.


TIM16_WriteTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Set TCNT1 to r17:r16

out TCNT1H,r17

out TCNT1L,r16

; Restore global interrupt flag

out SREG,r18

ret

C Code Example(1)

void TIM16_WriteTCNT1 ( unsigned int i )

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Set TCNT1 to i */

TCNT1 = i;

/* Restore global interrupt flag */

SREG = sreg;

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Count Increment or decrement TCNT1 by 1.

Direction Select between increment and decrement.

Clear Clear TCNT1 (set all bits to zero).

clkT1 Timer/Counter clock.

TOP Signalize that TCNT1 has reached maximum value.

BOTTOM Signalize that TCNT1 has reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High(TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L)containing the lower 8 bits. The TCNT1H Register can only be indirectly accessed bythe CPU. When the CPU does an access to the TCNT1H I/O location, the CPUaccesses the high byte temporary register (TEMP). The temporary register is updatedwith the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with thetemporary register value when TCNT1L is written. This allows the CPU to read or writethe entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is impor-tant to notice that there are special cases of writing to the TCNT1 Register when thecounter is counting that will give unpredictable results. The special cases are describedin the sections where they are of importance.

Depending on the mode of operation used, the counter is cleared, incremented, or dec-remented at each timer clock (clkT1). The clkT1 can be generated from an external orinternal clock source, selected by the Clock Select bits (CS12:0). When no clock sourceis selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can beaccessed by the CPU, independent of whether clkT1 is present or not. A CPU write over-rides (has priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the Waveform Generation Modebits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A andTCCR1B). There are close connections between how the counter behaves (counts) andhow waveforms are generated on the Output Compare outputs OC1x. For more detailsabout advanced counting sequences and waveform generation, see “Modes of Opera-tion” on page 94.


TEMP (8-bit)

DATA BUS (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit)Control Logic

Count

Clear

Direction

TOVn(Int.Req.)

Clock Select

TOP BOTTOM

TnEdge

Detector

( From Prescaler )

clkTn

892466E–AVR–10/02

Input Capture Unit The Timer/Counter incorporates an input capture unit that can capture external eventsand give them a time-stamp indicating time of occurrence. The external signal indicatingan event, or multiple events, can be applied via the ICP1 pin or alternatively, via theAnalog Comparator unit. The time-stamps can then be used to calculate frequency,duty-cycle, and other features of the signal applied. Alternatively the time-stamps can beused for creating a log of the events.

The input capture unit is illustrated by the block diagram shown in Figure 42. The ele-ments of the block diagram that are not directly a part of the input capture unit are grayshaded. The small “n” in register and bit names indicates the Timer/Counter number.

Figure 42. Input Capture Unit Block Diagram

When a change of the logic level (an event) occurs on the Input Capture pin (ICP1),alternatively on the Analog Comparator output (ACO), and this change confirms to thesetting of the edge detector, a capture will be triggered. When a capture is triggered, the16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1). TheInput Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copiedinto ICR1 Register. If enabled (TICIE1 = 1), the input capture flag generates an inputcapture interrupt. The ICF1 flag is automatically cleared when the interrupt is executed.Alternatively the ICF1 flag can be cleared by software by writing a logical one to its I/Obit location.

Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading thelow byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the highbyte is copied into the high byte temporary register (TEMP). When the CPU reads theICR1H I/O location it will access the TEMP Register.

The ICR1 register can only be written when using a Waveform Generation mode thatutilizes the ICR1 Register for defining the counter’s TOP value. In these cases theWaveform Generation mode (WGM13:0) bits must be set before the TOP value can bewritten to the ICR1 Register. When writing the ICR1 register the high byte must be writ-ten to the ICR1H I/O location before the low byte is written to ICR1L.

ICFn (Int.Req.)

AnalogComparator

WRITE ICRn (16-bit Register)

ICRnH (8-bit)

NoiseCanceler

ICPn

EdgeDetector

TEMP (8-bit)

DATA BUS (8-bit)

ICRnL (8-bit)


TCNTnH (8-bit) TCNTnL (8-bit)

ACIC* ICNC ICESACO*

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For more information on how to access the 16-bit registers refer to “Accessing 16-bitRegisters” on page 86.

Input Capture Trigger Source The main trigger source for the input capture unit is the Input Capture pin (ICP1).Timer/Counter1 can alternatively use the Analog Comparator output as trigger sourcefor the input capture unit. The Analog Comparator is selected as trigger source by set-ting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Controland Status Register (ACSR). Be aware that changing trigger source can trigger a cap-ture. The input capture flag must therefore be cleared after the change.

Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs aresampled using the same technique as for the T1 pin (Figure 38 on page 81). The edgedetector is also identical. However, when the noise canceler is enabled, additional logicis inserted before the edge detector, which increases the delay by four system clockcycles. Note that the input of the noise canceler and edge detector is always enabledunless the Timer/Counter is set in a waveform generation mode that uses ICR1 todefine TOP.

An input capture can be triggered by software by controlling the port of the ICP1 pin.

Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme.The noise canceler input is monitored over four samples, and all four must be equal forchanging the output that in turn is used by the edge detector.

The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bitin Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler intro-duces additional four system clock cycles of delay from a change applied to the input, tothe update of the ICR1 Register. The noise canceler uses the system clock and is there-fore not affected by the prescaler.

Using the Input Capture Unit The main challenge when using the input capture unit is to assign enough processorcapacity for handling the incoming events. The time between two events is critical. If theprocessor has not read the captured value in the ICR1 Register before the next eventoccurs, the ICR1 will be overwritten with a new value. In this case the result of the cap-ture will be incorrect.

When using the input capture interrupt, the ICR1 Register should be read as early in theinterrupt handler routine as possible. Even though the input capture interrupt has rela-tively high priority, the maximum interrupt response time is dependent on the maximumnumber of clock cycles it takes to handle any of the other interrupt requests.

Using the input capture unit in any mode of operation when the TOP value (resolution) isactively changed during operation, is not recommended.

Measurement of an external signal’s duty cycle requires that the trigger edge is changedafter each capture. Changing the edge sensing must be done as early as possible afterthe ICR1 Register has been read. After a change of the edge, the input capture flag(ICF1) must be cleared by software (writing a logical one to the I/O bit location). Formeasuring frequency only, the clearing of the ICF1 flag is not required (if an interrupthandler is used).

Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis-ter (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will setthe Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x =1), the Output Compare flag generates an output compare interrupt. The OCF1x flag isautomatically cleared when the interrupt is executed. Alternatively the OCF1x flag can

912466E–AVR–10/02

be cleared by software by writing a logical one to its I/O bit location. The Waveform Gen-erator uses the match signal to generate an output according to operating mode set bythe Waveform Generation mode (WGM13:0) bits and Compare Output mode(COM1x1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generatorfor handling the special cases of the extreme values in some modes of operation (See“Modes of Operation” on page 94.)

A special feature of output compare unit A allows it to define the Timer/Counter TOPvalue (i.e., counter resolution). In addition to the counter resolution, the TOP valuedefines the period time for waveforms generated by the Waveform Generator.

Figure 43 shows a block diagram of the output compare unit. The small “n” in the regis-ter and bit names indicates the device number (n = 1 for Timer/Counter1), and the “x”indicates output compare unit (A/B). The elements of the block diagram that are notdirectly a part of the output compare unit are gray shaded.


The OCR1x register is double buffered when using any of the twelve Pulse Width Modu-lation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes ofoperation, the double buffering is disabled. The double buffering synchronizes theupdate of the OCR1x Compare Register to either TOP or BOTTOM of the countingsequence. The synchronization prevents the occurrence of odd-length, non-symmetricalPWM pulses, thereby making the output glitch-free.

The OCR1x Register access may seem complex, but this is not case. When the doublebuffering is enabled, the CPU has access to the OCR1x Buffer Register, and if doublebuffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x(buffer or compare) register is only changed by a write operation (the Timer/Counterdoes not update this register automatically as the TCNT1 and ICR1 Register). ThereforeOCR1x is not read via the high byte temporary register (TEMP). However, it is a goodpractice to read the low byte first as when accessing other 16-bit registers. Writing theOCR1x Registers must be done via the TEMP Register since the compare of all 16 bitsis done continuously. The high byte (OCR1xH) has to be written first. When the high

OCFnx (Int.Req.)


OCRnx Buffer (16-bit Register)

OCRnxH Buf. (8-bit)

OCnx

TEMP (8-bit)

DATA BUS (8-bit)

OCRnxL Buf. (8-bit)


TCNTnH (8-bit) TCNTnL (8-bit)

COMnx1:0WGMn3:0

OCRnx (16-bit Register)

OCRnxH (8-bit) OCRnxL (8-bit)

Waveform GeneratorTOP

BOTTOM

92 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

byte I/O location is written by the CPU, the TEMP Register will be updated by the valuewritten. Then when the low byte (OCR1xL) is written to the lower eight bits, the high bytewill be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Reg-ister in the same system clock cycle.

For more information of how to access the 16-bit registers refer to “Accessing 16-bitRegisters” on page 86.

Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can beforced by writing a one to the Force Output Compare (FOC1x) bit. Forcing comparematch will not set the OCF1x flag or reload/clear the timer, but the OC1x pin will beupdated as if a real compare match had occurred (the COM11:0 bits settings definewhether the OC1x pin is set, cleared or toggled).


All CPU writes to the TCNT1 Register will block any compare match that occurs in thenext timer clock cycle, even when the timer is stopped. This feature allows OCR1x to beinitialized to the same value as TCNT1 without triggering an interrupt when theTimer/Counter clock is enabled.


Since writing TCNT1 in any mode of operation will block all compare matches for onetimer clock cycle, there are risks involved when changing TCNT1 when using any of theoutput compare channels, independent of whether the Timer/Counter is running or not.If the value written to TCNT1 equals the OCR1x value, the compare match will bemissed, resulting in incorrect waveform generation. Do not write the TCNT1 equal toTOP in PWM modes with variable TOP values. The compare match for the TOP will beignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 valueequal to BOTTOM when the counter is downcounting.

The setup of the OC1x should be performed before setting the data direction register forthe port pin to output. The easiest way of setting the OC1x value is to use the force out-put compare (FOC1x) strobe bits in Normal mode. The OC1x register keeps its valueeven when changing between waveform generation modes.

Be aware that the COM1x1:0 bits are not double buffered together with the comparevalue. Changing the COM1x1:0 bits will take effect immediately.


The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Gener-ator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the nextcompare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Fig-ure 44 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting.The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts ofthe general I/O Port Control Registers (DDR and PORT) that are affected by theCOM1x1:0 bits are shown. When referring to the OC1x state, the reference is for theinternal OC1x register, not the OC1x pin. If a System Reset occur, the OC1x Register isreset to “0”.

932466E–AVR–10/02


The general I/O port function is overridden by the Output Compare (OC1x) from theWaveform Generator if either of the COM1x1:0 bits are set. However, the OC1x pindirection (input or output) is still controlled by the Data Direction Register (DDR) for theport pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be set asoutput before the OC1x value is visible on the pin. The port override function is generallyindependent of the Waveform Generation mode, but there are some exceptions. Referto Table 44, Table 45 and Table 46 for details.

The design of the output compare pin logic allows initialization of the OC1x state beforethe output is enabled. Note that some COM1x1:0 bit settings are reserved for certainmodes of operation. See “16-bit Timer/Counter Register Description” on page 104.

The COM1x1:0 bits have no effect on the input capture unit.


The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWMmodes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that noaction on the OC1x Register is to be performed on the next compare match. For com-pare output actions in the non-PWM modes refer to Table 44 on page 104. For fastPWM mode refer to Table 45 on page 105, and for phase correct and phase and fre-quency correct PWM refer to Table 46 on page 105.

A change of the COM1x1:0 bits state will have effect at the first compare match after thebits are written. For non-PWM modes, the action can be forced to have immediate effectby using the FOC1x strobe bits.

Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the output comparepins, is defined by the combination of the Waveform Generation mode (WGM13:0) andCompare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affectthe counting sequence, while the Waveform Generation mode bits do. The COM1x1:0bits control whether the PWM output generated should be inverted or not (inverted ornon-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the out-put should be set, cleared or toggle at a compare match (See “Compare Match OutputUnit” on page 93.)

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 102.

PORT

DDR

D Q

D Q

OCnxPinOCnx


COMnx1

COMnx0

0

1

DAT

AB

US

FOCnx

clkI/O

94 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode thecounting direction is always up (incrementing), and no counter clear is performed. Thecounter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) andthen restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Over-flow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero.The TOV1 flag in this case behaves like a 17th bit, except that it is only set, not cleared.However, combined with the timer overflow interrupt that automatically clears the TOV1flag, the timer resolution can be increased by software. There are no special cases toconsider in the Normal mode, a new counter value can be written anytime.

The input capture unit is easy to use in Normal mode. However, observe that the maxi-mum interval between the external events must not exceed the resolution of the counter.If the interval between events are too long, the timer overflow interrupt or the prescalermust be used to extend the resolution for the capture unit.

The output compare units can be used to generate interrupts at some given time. Usingthe output compare to generate waveforms in Normal mode is not recommended, sincethis will occupy too much of the CPU time.


In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1Register are used to manipulate the counter resolution. In CTC mode the counter iscleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0= 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for thecounter, hence also its resolution. This mode allows greater control of the comparematch output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 45. The counter value(TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and thencounter (TCNT1) is cleared.


An interrupt can be generated at each time the counter value reaches the TOP value byeither using the OCF1A or ICF1 flag according to the register used to define the TOPvalue. If the interrupt is enabled, the interrupt handler routine can be used for updatingthe TOP value. However, changing the TOP to a value close to BOTTOM when thecounter is running with none or a low prescaler value must be done with care since theCTC mode does not have the double buffering feature. If the new value written toOCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the com-pare match. The counter will then have to count to its maximum value (0xFFFF) andwrap around starting at 0x0000 before the compare match can occur. In many cases

TCNTn

OCnA(Toggle)

OCnA Interrupt Flag Setor ICFn Interrupt Flag Set(Interrupt on TOP)

1 4Period 2 3

(COMnA1:0 = 1)

952466E–AVR–10/02

this feature is not desirable. An alternative will then be to use the fast PWM mode usingOCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be doublebuffered.

For generating a waveform output in CTC mode, the OC1A output can be set to toggleits logical level on each compare match by setting the compare output mode bits to tog-gle mode (COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless thedata direction for the pin is set to output (DDR_OC1A = 1). The waveform generated willhave a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). Thewaveform frequency is defined by the following equation:

The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).


Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5,6,7,14, or 15) pro-vides a high frequency PWM waveform generation option. The fast PWM differs fromthe other PWM options by its single-slope operation. The counter counts from BOTTOMto TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the OutputCompare (OC1x) is set on the compare match between TCNT1 and OCR1x, andcleared at TOP. In inverting Compare Output mode output is cleared on compare matchand set at TOP. Due to the single-slope operation, the operating frequency of the fastPWM mode can be twice as high as the phase correct and phase and frequency correctPWM modes that use dual-slope operation. This high frequency makes the fast PWMmode well suited for power regulation, rectification, and DAC applications. High fre-quency allows physically small sized external components (coils, capacitors), hencereduces total system cost.

The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by eitherICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWMresolution in bits can be calculated by using the following equation:

In fast PWM mode the counter is incremented until the counter value matches eitherone of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value inICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The counter is thencleared at the following timer clock cycle. The timing diagram for the fast PWM mode isshown in Figure 46. The figure shows fast PWM mode when OCR1A or ICR1 is used todefine TOP. The TCNT1 value is in the timing diagram shown as a histogram for illus-trating the single-slope operation. The diagram includes non-inverted and inverted PWMoutputs. The small horizontal line marks on the TCNT1 slopes represent comparematches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a com-pare match occurs.

fOCnA

fclk_I/O

2 N 1 OCRnA+( )⋅ ⋅---------------------------------------------------=

RFPWMTOP 1+( )log

2( )log-----------------------------------=

96 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)


The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. Inaddition the OC1A or ICF1 flag is set at the same timer clock cycle as TOV1 is set wheneither OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts areenabled, the interrupt handler routine can be used for updating the TOP and comparevalues.

When changing the TOP value the program must ensure that the new TOP value ishigher or equal to the value of all of the compare registers. If the TOP value is lowerthan any of the compare registers, a compare match will never occur between theTCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits aremasked to zero when any of the OCR1x Registers are written.

The procedure for updating ICR1 differs from updating OCR1A when used for definingthe TOP value. The ICR1 Register is not double buffered. This means that if ICR1 ischanged to a low value when the counter is running with none or a low prescaler value,there is a risk that the new ICR1 value written is lower than the current value of TCNT1.The result will then be that the counter will miss the compare match at the TOP value.The counter will then have to count to the MAX value (0xFFFF) and wrap around start-ing at 0x0000 before the compare match can occur. The OCR1A Register however, isdouble buffered. This feature allows the OCR1A I/O location to be written anytime.When the OCR1A I/O location is written the value written will be put into the OCR1ABuffer Register. The OCR1A Compare Register will then be updated with the value inthe buffer register at the next timer clock cycle the TCNT1 matches TOP. The update isdone at the same timer clock cycle as the TCNT1 is cleared and the TOV1 flag is set.

Using the ICR1 Register for defining TOP works well when using fixed TOP values. Byusing ICR1, the OCR1A Register is free to be used for generating a PWM output onOC1A. However, if the base PWM frequency is actively changed (by changing the TOPvalue), using the OCR1A as TOP is clearly a better choice due to its double bufferfeature.

In fast PWM mode, the compare units allow generation of PWM waveforms on theOC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and aninverted PWM output can be generated by setting the COM1x1:0 to 3 (See Table 44 onpage 104). The actual OC1x value will only be visible on the port pin if the data directionfor the port pin is set as output (DDR_OC1x). The PWM waveform is generated by

TCNTn

OCRnx / TOP Update andTOVn Interrupt Flag Set andOCnA Interrupt Flag SetOCnA Interrupt Flag Set(Interrupt on TOP)

1 7Period 2 3 4 5 6 8

OCnx

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

972466E–AVR–10/02

seting (or clearing) the OC1x Register at the compare match between OCR1x andTCNT1, and clearing (or setting) the OC1x Register at the timer clock cycle the counteris cleared (changes from TOP to BOTTOM).


The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represents special cases when generatinga PWM waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM(0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting theOCR1x equal to TOP will result in a constant high or low output (depending on the polar-ity of the output set by the COM1x1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achievedby setting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1).This applies only if OCR1A is used to define the TOP value (WGM13:0 = 15). The wave-form generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set tozero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the dou-ble buffer feature of the output compare unit is enabled in the fast PWM mode.

Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 =1,2,3,10, or 11) provides a high resolution phase correct PWM waveform generationoption. The phase correct PWM mode is, like the phase and frequency correct PWMmode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Outputmode, the Output Compare (OC1x) is cleared on the compare match between TCNT1and OCR1x while upcounting, and set on the compare match while downcounting. Ininverting Output Compare mode, the operation is inverted. The dual-slope operation haslower maximum operation frequency than single slope operation. However, due to thesymmetric feature of the dual-slope PWM modes, these modes are preferred for motorcontrol applications.

The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, ordefined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 orOCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set toMAX). The PWM resolution in bits can be calculated by using the following equation:

In phase correct PWM mode the counter is incremented until the counter value matcheseither one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), thevalue in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counterhas then reached the TOP and changes the count direction. The TCNT1 value will beequal to TOP for one timer clock cycle. The timing diagram for the phase correct PWMmode is shown on Figure 47. The figure shows phase correct PWM mode when OCR1Aor ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as ahistogram for illustrating the dual-slope operation. The diagram includes non-invertedand inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes repre-sent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be setwhen a compare match occurs.

fOCnxPWM

fclk_I/O

N 1 TOP+( )⋅-----------------------------------=

RPCPWMTOP 1+( )log

2( )log-----------------------------------=

98 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)


The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOT-TOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A orICF1 flag is set accordingly at the same timer clock cycle as the OCR1x Registers areupdated with the double buffer value (at TOP). The interrupt flags can be used to gener-ate an interrupt each time the counter reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value ishigher or equal to the value of all of the compare registers. If the TOP value is lowerthan any of the compare registers, a compare match will never occur between theTCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits aremasked to zero when any of the OCR1x Registers are written. As the third period shownin Figure 47 illustrates, changing the TOP actively while the Timer/Counter is running inthe phase correct mode can result in an unsymmetrical output. The reason for this canbe found in the time of update of the OCR1x Register. Since the OCR1x update occursat TOP, the PWM period starts and ends at TOP. This implies that the length of the fall-ing slope is determined by the previous TOP value, while the length of the rising slope isdetermined by the new TOP value. When these two values differ the two slopes of theperiod will differ in length. The difference in length gives the unsymmetrical result on theoutput.

It is recommended to use the phase and frequency correct mode instead of the phasecorrect mode when changing the TOP value while the Timer/Counter is running. Whenusing a static TOP value there are practically no differences between the two modes ofoperation.

In phase correct PWM mode, the compare units allow generation of PWM waveforms onthe OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and aninverted PWM output can be generated by setting the COM1x1:0 to 3 (See Table 44 onpage 104). The actual OC1x value will only be visible on the port pin if the data directionfor the port pin is set as output (DDR_OC1x). The PWM waveform is generated by set-ting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1when the counter increments, and clearing (or setting) the OC1x Register at comparematch between OCR1x and TCNT1 when the counter decrements. The PWM frequency

OCRnx/TOP Update andOCnA Interrupt Flag Setor ICFn Interrupt Flag Set(Interrupt on TOP)

1 2 3 4

TOVn Interrupt Flag Set(Interrupt on Bottom)

TCNTn

Period

OCnx

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

992466E–AVR–10/02

for the output when using phase correct PWM can be calculated by the followingequation:


The extreme values for the OCR1x Register represent special cases when generating aPWM waveform output in the phase correct PWM mode. If the OCR1x is set equal toBOTTOM the output will be continuously low and if set equal to TOP the output will becontinuously high for non-inverted PWM mode. For inverted PWM the output will havethe opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11)and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.

Phase and Frequency Correct PWM Mode

The phase and frequency correct Pulse Width Modulation, or phase and frequency cor-rect PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequencycorrect PWM waveform generation option. The phase and frequency correct PWMmode is, like the phase correct PWM mode, based on a dual-slope operation. Thecounter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOT-TOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is clearedon the compare match between TCNT1 and OCR1x while upcounting, and set on thecompare match while downcounting. In inverting Compare Output mode, the operationis inverted. The dual-slope operation gives a lower maximum operation frequency com-pared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications.

The main difference between the phase correct, and the phase and frequency correctPWM mode is the time the OCR1x Register is updated by the OCR1x Buffer Register,(see Figure 47 and Figure 48).

The PWM resolution for the phase and frequency correct PWM mode can be defined byeither ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWMresolution in bits can be calculated using the following equation:

In phase and frequency correct PWM mode the counter is incremented until the countervalue matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A(WGM13:0 = 9). The counter has then reached the TOP and changes the count direc-tion. The TCNT1 value will be equal to TOP for one timer clock cycle. The timingdiagram for the phase correct and frequency correct PWM mode is shown on Figure 48.The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 isused to define TOP. The TCNT1 value is in the timing diagram shown as a histogram forillustrating the dual-slope operation. The diagram includes non-inverted and invertedPWM outputs. The small horizontal line marks on the TCNT1 slopes represent comparematches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a com-pare match occurs.

fOCnxPCPWM

fclk_I/O

2 N TOP⋅ ⋅----------------------------=

RPFCPWMTOP 1+( )log

2( )log-----------------------------------=

100 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 48. Phase and Frequency Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as theOCR1x registers are updated with the double buffer value (at BOTTOM). When eitherOCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag set whenTCNT1 has reached TOP. The interrupt flags can then be used to generate an interrupteach time the counter reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value ishigher or equal to the value of all of the compare registers. If the TOP value is lowerthan any of the compare registers, a compare match will never occur between theTCNT1 and the OCR1x.

As Figure 48 shows the output generated is, in contrast to the phase correct mode, sym-metrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the lengthof the rising and the falling slopes will always be equal. This gives symmetrical outputpulses and is therefore frequency correct.

Using the ICR1 Register for defining TOP works well when using fixed TOP values. Byusing ICR1, the OCR1A Register is free to be used for generating a PWM output onOC1A. However, if the base PWM frequency is actively changed by changing the TOPvalue, using the OCR1A as TOP is clearly a better choice due to its double bufferfeature.

In phase and frequency correct PWM mode, the compare units allow generation ofPWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0to 3 (See Table on page 105). The actual OC1x value will only be visible on the port pinif the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform isgenerated by setting (or clearing) the OC1x Register at the compare match betweenOCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1xRegister at compare match between OCR1x and TCNT1 when the counter decrements.The PWM frequency for the output when using phase and frequency correct PWM canbe calculated by the following equation:


OCRnx / TOP UpdateandTOVn Interrupt Flag Set(Interrupt on Bottom)

OCnA Interrupt Flag Setor ICFn Interrupt Flag Set(Interrupt on TOP)

1 2 3 4

TCNTn

Period

OCnx

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

fOCnxPFCPWM

fclk_I/O

2 N TOP⋅ ⋅----------------------------=

1012466E–AVR–10/02

The extreme values for the OCR1x Register represents special cases when generatinga PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal toBOTTOM the output will be continuously low and if set equal to TOP the output will beset to high for non-inverted PWM mode. For inverted PWM the output will have theopposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) andCOM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.


The Timer/Counter is a synchronous design and the timer clock (clkT1) is thereforeshown as a clock enable signal in the following figures. The figures include informationon when interrupt flags are set, and when the OCR1x Register is updated with theOCR1x buffer value (only for modes utilizing double buffering). Figure 49 shows a timingdiagram for the setting of OCF1x.

Figure 49. Timer/Counter Timing Diagram, Setting of OCF1x, No Prescaling


Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8)

clkTn(clkI/O/1)

OCFnx

clkI/O

OCRnx

TCNTn

OCRnx Value

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clkI/O

clkTn(clkI/O/8)

102 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 51 shows the count sequence close to TOP in various modes. When using phaseand frequency correct PWM mode the OCR1x Register is updated at BOTTOM. Thetiming diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 byBOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag atBOTTOM.




TOVn (FPWM)and ICFn (if used

as TOP)

OCRnx(Update at TOP)

TCNTn(CTC and FPWM)

TCNTn(PC and PFC PWM)

TOP - 1 TOP TOP - 1 TOP - 2

Old OCRnx Value New OCRnx Value


clkTn(clkI/O/1)

clkI/O

TOVn (FPWM)and ICFn (if used

as TOP)

OCRnx(Update at TOP)

TCNTn(CTC and FPWM)

TCNTn(PC and PFC PWM)

TOP - 1 TOP TOP - 1 TOP - 2

Old OCRnx Value New OCRnx Value


clkI/O

clkTn(clkI/O/8)

1032466E–AVR–10/02


Timer/Counter1 Control Register A – TCCR1A

• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A

• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B

The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1Brespectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1Aoutput overrides the normal port functionality of the I/O pin it is connected to. If one orboth of the COM1B1:0 bit are written to one, the OC1B output overrides the normal portfunctionality of the I/O pin it is connected to. However, note that the Data Direction Reg-ister (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enablethe output driver.

When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits isdependent of the WGM13:0 bits setting. Table 44 shows the COM1x1:0 bit functionalitywhen the WGM13:0 bits are set to a normal or a CTC mode (non-PWM).

Table 45 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to thefast PWM mode.

Bit 7 6 5 4 3 2 1 0

COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 TCCR1A

Read/Write R/W R/W R/W R/W W W R/W R/W


Table 44. Compare Output Mode, non-PWM

COM1A1/COM1B1 COM1A0/COM1B0 Description

0 0 Normal port operation, OC1A/OC1B disconnected.

0 1 Toggle OC1A/OC1B on compare match

1 0 Clear OC1A/OC1B on compare match (Set output to low level)

1 1 Set OC1A/OC1B on compare match (Set output to high level)

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Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 isset. In this case the compare match is ignored, but the set or clear is done at TOP.See “Fast PWM Mode” on page 96. for more details.

Table 46 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to thephase correct or the phase and frequency correct, PWM mode.

Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 isset. See “Phase Correct PWM Mode” on page 98. for more details.

• Bit 3 – FOC1A: Force Output Compare for Channel A

• Bit 2 – FOC1B: Force Output Compare for Channel B

The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWMmode. However, for ensuring compatibility with future devices, these bits must be set tozero when TCCR1A is written when operating in a PWM mode. When writing a logicalone to the FOC1A/FOC1B bit, an immediate compare match is forced on the WaveformGeneration unit. The OC1A/OC1B output is changed according to its COM1x1:0 bitssetting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it isthe value present in the COM1x1:0 bits that determine the effect of the forced compare.

Table 45. Compare Output Mode, Fast PWM(1)



0 1 WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation).For all other WGM13:0 settings, normal port operation, OCnA/OCnB disconnected.

1 0 Clear OC1A/OC1B on compare match, set OC1A/OC1B at TOP

1 1 Set OC1A/OC1B on compare match, clear OC1A/OC1B at TOP

Table 46. Compare Output Mode, Phase Correct and Phase and Frequency CorrectPWM (1)



0 1 WGM13:0 = 9 or 14: Toggle OCnA on Compare Match, OCnB disconnected (normal port operation).For all other WGM13:0 settings, normal port operation, OC1A/OC1B disconnected.

1 0 Clear OC1A/OC1B on compare match when up-counting. Set OC1A/OC1B on compare match when downcounting.

1 1 Set OC1A/OC1B on compare match when up-counting. Clear OC1A/OC1B on compare match when downcounting.

1052466E–AVR–10/02

A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in ClearTimer on Compare match (CTC) mode using OCR1A as TOP.

The FOC1A/FOC1B bits are always read as zero.

• Bit 1:0 – WGM11:0: Waveform Generation Mode

Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control thecounting sequence of the counter, the source for maximum (TOP) counter value, andwhat type of waveform generation to be used, see Table 47. Modes of operation sup-ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Comparematch (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See“Modes of Operation” on page 94.)

Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality andlocation of these bits are compatible with previous versions of the timer.


Mode WGM13WGM12(CTC1)

WGM11(PWM11)

WGM10(PWM10) Timer/Counter Mode of Operation TOP

Update of OCR1x

TOV1 Flag Set on

0 0 0 0 0 Normal 0xFFFF Immediate MAX

1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM



4 0 1 0 0 CTC OCR1A Immediate MAX

5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP



8 1 0 0 0 PWM, Phase and Frequency Correct ICR1 BOTTOM BOTTOM

9 1 0 0 1 PWM, Phase and Frequency Correct OCR1A BOTTOM BOTTOM

10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM

11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM

12 1 1 0 0 CTC ICR1 Immediate MAX

13 1 1 0 1 Reserved – – –

14 1 1 1 0 Fast PWM ICR1 TOP TOP

15 1 1 1 1 Fast PWM OCR1A TOP TOP

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Timer/Counter1 Control Register B – TCCR1B

• Bit 7 – ICNC1: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Canceler. When the NoiseCanceler is activated, the input from the Input Capture Pin (ICP1) is filtered. The filterfunction requires four successive equal valued samples of the ICP1 pin for changing itsoutput. The input capture is therefore delayed by four Oscillator cycles when the NoiseCanceler is enabled.

• Bit 6 – ICES1: Input Capture Edge Select

This bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a cap-ture event. When the ICES1 bit is written to zero, a falling (negative) edge is used astrigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger thecapture.

When a capture is triggered according to the ICES1 setting, the counter value is copiedinto the Input Capture Register (ICR1). The event will also set the Input Capture Flag(ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt isenabled.

When the ICR1 is used as TOP value (see description of the WGM13:0 bits located inthe TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequentlythe input capture function is disabled.

• Bit 5 – Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bitmust be written to zero when TCCR1B is written.

• Bit 4:3 – WGM13:2: Waveform Generation Mode

See TCCR1A Register description.


The three Clock Select bits select the clock source to be used by the Timer/Counter, seeFigure 49 and Figure 50.

Bit 7 6 5 4 3 2 1 0

ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B






0 0 1 clkI/O/1 (No prescaling)




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If external pin modes are used for the Timer/Counter1, transitions on the T1 pin willclock the counter even if the pin is configured as an output. This feature allows softwarecontrol of the counting.

Timer/Counter1 – TCNT1H and TCNT1L

The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) givedirect access, both for read and for write operations, to the Timer/Counter unit 16-bitcounter. To ensure that both the high and low bytes are read and written simultaneouslywhen the CPU accesses these registers, the access is performed using an 8-bit tempo-rary high byte register (TEMP). This temporary register is shared by all the other 16-bitregisters. See “Accessing 16-bit Registers” on page 86.

Modifying the counter (TCNT1) while the counter is running introduces a risk of missinga compare match between TCNT1 and one of the OCR1x Registers.

Writing to the TCNT1 Register blocks (removes) the compare match on the followingtimer clock for all compare units.

Output Compare Register 1 A – OCR1AH and OCR1AL

Output Compare Register 1 B – OCR1BH and OCR1BL

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT1). A match can be used to generate an output compareinterrupt, or to generate a waveform output on the OC1x pin.

The Output Compare Registers are 16-bit in size. To ensure that both the high and lowbytes are written simultaneously when the CPU writes to these registers, the access isperformed using an 8-bit temporary high byte register (TEMP). This temporary registeris shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 86.


1 1 0 External clock source on T1 pin. Clock on falling edge.

1 1 1 External clock source on T1 pin. Clock on rising edge.

Table 48. Clock Select Bit Description (Continued)


Bit 7 6 5 4 3 2 1 0

TCNT1[15:8] TCNT1H

TCNT1[7:0] TCNT1L



Bit 7 6 5 4 3 2 1 0

OCR1A[15:8] OCR1AH

OCR1A[7:0] OCR1AL



Bit 7 6 5 4 3 2 1 0

OCR1B[15:8] OCR1BH

OCR1B[7:0] OCR1BL



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ATmega16(L)

Input Capture Register 1 – ICR1H and ICR1L

The Input Capture is updated with the counter (TCNT1) value each time an event occurson the ICP1 pin (or optionally on the analog comparator output for Timer/Counter1). TheInput Capture can be used for defining the counter TOP value.

The Input Capture register is 16-bit in size. To ensure that both the high and low bytesare read simultaneously when the CPU accesses these registers, the access is per-formed using an 8-bit temporary high byte register (TEMP). This temporary register isshared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 86.

Timer/Counter Interrupt Mask Register – TIMSK(1)

Note: 1. This register contains interrupt control bits for several Timer/Counters, but onlyTimer1 bits are described in this section. The remaining bits are described in theirrespective timer sections.

• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-bally enabled), the Timer/Counter1 Input Capture Interrupt is enabled. Thecorresponding Interrupt Vector (See “Interrupts” on page 42.) is executed when theICF1 flag, located in TIFR, is set.

• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-bally enabled), the Timer/Counter1 Output Compare A match interrupt is enabled. Thecorresponding Interrupt Vector (See “Interrupts” on page 42.) is executed when theOCF1A flag, located in TIFR, is set.

• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-bally enabled), the Timer/Counter1 Output Compare B match interrupt is enabled. Thecorresponding Interrupt Vector (See “Interrupts” on page 42.) is executed when theOCF1B flag, located in TIFR, is set.

• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-bally enabled), the Timer/Counter1 Overflow Interrupt is enabled. The correspondingInterrupt Vector (See “Interrupts” on page 42.) is executed when the TOV1 flag, locatedin TIFR, is set.

Bit 7 6 5 4 3 2 1 0

ICR1[15:8] ICR1H

ICR1[7:0] ICR1L



Bit 7 6 5 4 3 2 1 0




1092466E–AVR–10/02


Note: This register contains flag bits for several Timer/Counters, but only Timer1 bits aredescribed in this section. The remaining bits are described in their respective timersections.

• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag

This flag is set when a capture event occurs on the ICP1 pin. When the Input CaptureRegister (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 flag is setwhen the counter reaches the TOP value.

ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alter-natively, ICF1 can be cleared by writing a logic one to its bit location.

• Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-put Compare Register A (OCR1A).

Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A flag.

OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector isexecuted. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.

• Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-put Compare Register B (OCR1B).

Note that a forced output compare (FOC1B) strobe will not set the OCF1B flag.

OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector isexecuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.

• Bit 2 – TOV1: Timer/Counter1, Overflow Flag

The setting of this flag is dependent of the WGM13:0 bits setting. In normal and CTCmodes, the TOV1 flag is set when the timer overflows. Refer to Table 47 on page 106for the TOV1 flag behavior when using another WGM13:0 bit setting.

TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector isexecuted. Alternatively, TOV1 can be cleared by writing a logic one to its bit location.

Bit 7 6 5 4 3 2 1 0




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8-bit Timer/Counter2 with PWM and Asynchronous Operation

Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. Themain features are:• Single Channel Counter• Clear Timer on Compare Match (Auto Reload)• Glitch-free, Phase Correct Pulse Width Modulator (PWM)• Frequency Generator• 10-bit Clock Prescaler• Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)• Allows clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 53. For theactual placement of I/O pins, refer to “Pinouts ATmega16” on page 2. CPU accessibleI/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/Oregister and bit locations are listed in the “8-bit Timer/Counter Register Description” onpage 121.

Figure 53. 8-bit Timer/Counter Block Diagram

Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers.Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt FlagRegister (TIFR). All interrupts are individually masked with the Timer Interrupt MaskRegister (TIMSK). TIFR and TIMSK are not shown in the figure since these registers areshared by other timer units.

The Timer/Counter can be clocked internally, via the prescaler, or asynchronouslyclocked from the TOSC1/2 pins, as detailed later in this section. The asynchronousoperation is controlled by the Asynchronous Status Register (ASSR). The Clock Selectlogic block controls which clock source the Timer/Counter uses to increment (or decre-ment) its value. The Timer/Counter is inactive when no clock source is selected. Theoutput from the Clock Select logic is referred to as the timer clock (clkT2).

Timer/Counter

DAT

AB

US

=

TCNTn

WaveformGeneration

OCn

= 0

Control Logic

= 0xFF

TOPBOTTOM

count

clear

direction

TOVn(Int.Req.)

OCn(Int.Req.)

Synchronization Unit

OCRn

TCCRn

ASSRnStatus flags

clkI/O

clkASY

Synchronized Status flags

asynchronous modeselect (ASn)

TOSC1

T/COscillator

TOSC2

Prescaler

clkTn

clkI/O

1112466E–AVR–10/02

The double buffered Output Compare Register (OCR2) is compared with theTimer/Counter value at all times. The result of the compare can be used by the wave-form generator to generate a PWM or variable frequency output on the Output ComparePin (OC2). See “Output Compare Unit” on page 113. for details. The compare matchevent will also set the Compare Flag (OCF2) which can be used to generate an outputcompare interrupt request.

Definitions Many register and bit references in this document are written in general form. A lowercase “n” replaces the Timer/Counter number, in this case 2. However, when using theregister or bit defines in a program, the precise form must be used (i.e., TCNT2 foraccessing Timer/Counter2 counter value and so on). The definitions in Table 49 are alsoused extensively throughout the document.


The Timer/Counter can be clocked by an internal synchronous or an external asynchro-nous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O.When the AS2 bit in the ASSR Register is written to logic one, the clock source is takenfrom the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details onasynchronous operation, see “Asynchronous Status Register – ASSR” on page 124. Fordetails on clock sources and prescaler, see “Timer/Counter Prescaler” on page 127.

Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.Figure 54 shows a block diagram of the counter and its surrounding environment.



count Increment or decrement TCNT2 by 1.

direction Selects between increment and decrement.

clear Clear TCNT2 (set all bits to zero).

clkT2 Timer/Counter clock.


BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).

MAX The counter reaches its MAXimum when it becomes 0xFF (decimal255).

TOP The counter reaches the TOP when it becomes equal to the highestvalue in the count sequence. The TOP value can be assigned to be thefixed value 0xFF (MAX) or the value stored in the OCR2 register. Theassignment is dependent on the mode of operation.

DATA BUS

TCNTn Control Logic

count

TOVn(Int.Req.)

topbottom

direction

clear

TOSC1

T/COscillator

TOSC2

Prescaler

clkI/O

clkTn

112 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

top Signalizes that TCNT2 has reached maximum value.

bottom Signalizes that TCNT2 has reached minimum value (zero).

Depending on the mode of operation used, the counter is cleared, incremented, or dec-remented at each timer clock (clkT2). clkT2 can be generated from an external or internalclock source, selected by the Clock Select bits (CS22:0). When no clock source isselected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessedby the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (haspriority over) all counter clear or count operations.

The counting sequence is determined by the setting of the WGM21 and WGM20 bitslocated in the Timer/Counter Control Register (TCCR2). There are close connectionsbetween how the counter behaves (counts) and how waveforms are generated on theOutput Compare output OC2. For more details about advanced counting sequencesand waveform generation, see “Modes of Operation” on page 115.


Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the output compare register(OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match willset the Output Compare Flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 =1), the output compare flag generates an output compare interrupt. The OCF2 flag isautomatically cleared when the interrupt is executed. Alternatively, the OCF2 flag canbe cleared by software by writing a logical one to its I/O bit location. The waveform gen-erator uses the match signal to generate an output according to operating mode set bythe WGM21:0 bits and Compare Output mode (COM21:0) bits. The max and bottom sig-nals are used by the waveform generator for handling the special cases of the extremevalues in some modes of operation (“Modes of Operation” on page 115). Figure 55shows a block diagram of the output compare unit.


OCFn (Int.Req.)


OCRn

OCxy

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMn1:0

bottom

1132466E–AVR–10/02

The OCR2 Register is double buffered when using any of the Pulse Width Modulation(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation,the double buffering is disabled. The double buffering synchronizes the update of theOCR2 Compare Register to either top or bottom of the counting sequence. The synchro-nization prevents the occurrence of odd-length, non-symmetrical PWM pulses, therebymaking the output glitch-free.

The OCR2 Register access may seem complex, but this is not case. When the doublebuffering is enabled, the CPU has access to the OCR2 Buffer Register, and if doublebuffering is disabled the CPU will access the OCR2 directly.

Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can beforced by writing a one to the Force Output Compare (FOC2) bit. Forcing comparematch will not set the OCF2 flag or reload/clear the timer, but the OC2 pin will beupdated as if a real compare match had occurred (the COM21:0 bits settings definewhether the OC2 pin is set, cleared or toggled).


All CPU write operations to the TCNT2 Register will block any compare match thatoccurs in the next timer clock cycle, even when the timer is stopped. This feature allowsOCR2 to be initialized to the same value as TCNT2 without triggering an interrupt whenthe Timer/Counter clock is enabled.


Since writing TCNT2 in any mode of operation will block all compare matches for onetimer clock cycle, there are risks involved when changing TCNT2 when using the outputcompare channel, independently of whether the Timer/Counter is running or not. If thevalue written to TCNT2 equals the OCR2 value, the compare match will be missed,resulting in incorrect waveform generation. Similarly, do not write the TCNT2 valueequal to BOTTOM when the counter is downcounting.

The setup of the OC2 should be performed before setting the Data Direction Register forthe port pin to output. The easiest way of setting the OC2 value is to use the Force Out-put Compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value evenwhen changing between Waveform Generation modes.

Be aware that the COM21:0 bits are not double buffered together with the comparevalue. Changing the COM21:0 bits will take effect immediately.


The Compare Output mode (COM21:0) bits have two functions. The Waveform Genera-tor uses the COM21:0 bits for defining the Output Compare (OC2) state at the nextcompare match. Also, the COM21:0 bits control the OC2 pin output source. Figure 56shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/ORegisters, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of thegeneral I/O Port Control Registers (DDR and PORT) that are affected by the COM21:0bits are shown. When referring to the OC2 state, the reference is for the internal OC2Register, not the OC2 pin.

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The general I/O port function is overridden by the Output Compare (OC2) from thewaveform generator if either of the COM21:0 bits are set. However, the OC2 pin direc-tion (input or output) is still controlled by the Data Direction Register (DDR) for the portpin. The Data Direction Register bit for the OC2 pin (DDR_OC2) must be set as outputbefore the OC2 value is visible on the pin. The port override function is independent ofthe Waveform Generation mode.

The design of the output compare pin logic allows initialization of the OC2 state beforethe output is enabled. Note that some COM21:0 bit settings are reserved for certainmodes of operation. See “8-bit Timer/Counter Register Description” on page 121.


The waveform generator uses the COM21:0 bits differently in Normal, CTC, and PWMmodes. For all modes, setting the COM21:0 = 0 tells the Waveform Generator that noaction on the OC2 Register is to be performed on the next compare match. For compareoutput actions in the non-PWM modes refer to Table 51 on page 122. For fast PWMmode, refer to Table 52 on page 122, and for phase correct PWM refer to Table 53 onpage 123.

A change of the COM21:0 bits state will have effect at the first compare match after thebits are written. For non-PWM modes, the action can be forced to have immediate effectby using the FOC2 strobe bits.

Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the output comparepins, is defined by the combination of the Waveform Generation mode (WGM21:0) andCompare Output mode (COM21:0) bits. The Compare Output mode bits do not affectthe counting sequence, while the Waveform Generation mode bits do. The COM21:0bits control whether the PWM output generated should be inverted or not (inverted ornon-inverted PWM). For non-PWM modes the COM21:0 bits control whether the outputshould be set, cleared, or toggled at a compare match (See “Compare Match OutputUnit” on page 114.).

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 119.

Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode thecounting direction is always up (incrementing), and no counter clear is performed. Thecounter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then

PORT

DDR

D Q

D Q

OCnPinOCn


COMn1

COMn0

0

1

DAT

A B

US

FOCn

clkI/O

1152466E–AVR–10/02

restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag(TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2flag in this case behaves like a ninth bit, except that it is only set, not cleared. However,combined with the timer overflow interrupt that automatically clears the TOV2 flag, thetimer resolution can be increased by software. There are no special cases to consider inthe normal mode, a new counter value can be written anytime.

The Output Compare unit can be used to generate interrupts at some given time. Usingthe output compare to generate waveforms in normal mode is not recommended, sincethis will occupy too much of the CPU time.


In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 register is used tomanipulate the counter resolution. In CTC mode the counter is cleared to zero when thecounter value (TCNT2) matches the OCR2. The OCR2 defines the top value for thecounter, hence also its resolution. This mode allows greater control of the comparematch output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 57. The counter value(TCNT2) increases until a compare match occurs between TCNT2 and OCR2, and thencounter (TCNT2) is cleared.


An interrupt can be generated each time the counter value reaches the TOP value byusing the OCF2 flag. If the interrupt is enabled, the interrupt handler routine can be usedfor updating the TOP value. However, changing the TOP to a value close to BOTTOMwhen the counter is running with none or a low prescaler value must be done with caresince the CTC mode does not have the double buffering feature. If the new value writtento OCR2 is lower than the current value of TCNT2, the counter will miss the comparematch. The counter will then have to count to its maximum value (0xFF) and wraparound starting at 0x00 before the compare match can occur.

For generating a waveform output in CTC mode, the OC2 output can be set to toggle itslogical level on each compare match by setting the Compare Output mode bits to togglemode (COM21:0 = 1). The OC2 value will not be visible on the port pin unless the datadirection for the pin is set to output. The waveform generated will have a maximum fre-quency of fOC2 = fclk_I/O/2 when OCR2 is set to zero (0x00). The waveform frequency isdefined by the following equation:

TCNTn

OCn(Toggle)


1 4Period 2 3

(COMn1:0 = 1)

fOCn

fclk_I/O

2 N 1 OCRn+( )⋅ ⋅-----------------------------------------------=

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The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).


Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high fre-quency PWM waveform generation option. The fast PWM differs from the other PWMoption by its single-slope operation. The counter counts from BOTTOM to MAX thenrestarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare(OC2) is cleared on the compare match between TCNT2 and OCR2, and set at BOT-TOM. In inverting Compare Output mode, the output is set on compare match andcleared at BOTTOM. Due to the single-slope operation, the operating frequency of thefast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for powerregulation, rectification, and DAC applications. High frequency allows physically smallsized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the MAXvalue. The counter is then cleared at the following timer clock cycle. The timing diagramfor the fast PWM mode is shown in Figure 58. The TCNT2 value is in the timing diagramshown as a histogram for illustrating the single-slope operation. The diagram includesnon-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2slopes represent compare matches between OCR2 and TCNT2.


The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. Ifthe interrupt is enabled, the interrupt handler routine can be used for updating the com-pare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM and an invertedPWM output can be generated by setting the COM21:0 to 3 (see Table 52 on page 122).The actual OC2 value will only be visible on the port pin if the data direction for the portpin is set as output. The PWM waveform is generated by setting (or clearing) the OC2register at the compare match between OCR2 and TCNT2, and clearing (or setting) theOC2 Register at the timer clock cycle the counter is cleared (changes from MAX toBOTTOM).

TCNTn

OCRn Update andTOVn Interrupt Flag Set

1Period 2 3

OCn

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Interrupt Flag Set

4 5 6 7

1172466E–AVR–10/02



The extreme values for the OCR2 Register represent special cases when generating aPWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, theoutput will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equalto MAX will result in a constantly high or low output (depending on the polarity of the out-put set by the COM21:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achievedby setting OC2 to toggle its logical level on each compare match (COM21:0 = 1). Thewaveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2 is setto zero. This feature is similar to the OC2 toggle in CTC mode, except the double bufferfeature of the output compare unit is enabled in the fast PWM mode.

Phase Correct PWM Mode The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correctPWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then fromMAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2)is cleared on the compare match between TCNT2 and OCR2 while upcounting, and seton the compare match while downcounting. In inverting Output Compare mode, theoperation is inverted. The dual-slope operation has lower maximum operation frequencythan single slope operation. However, due to the symmetric feature of the dual-slopePWM modes, these modes are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode is fixed to 8 bits. In phase correctPWM mode the counter is incremented until the counter value matches MAX. When thecounter reaches MAX, it changes the count direction. The TCNT2 value will be equal toMAX for one timer clock cycle. The timing diagram for the phase correct PWM mode isshown on Figure 59. The TCNT2 value is in the timing diagram shown as a histogramfor illustrating the dual-slope operation. The diagram includes non-inverted and invertedPWM outputs. The small horizontal line marks on the TCNT2 slopes represent comparematches between OCR2 and TCNT2.

fOCnPWM

fclk_I/O

N 256⋅------------------=

118 ATmega16(L) 2466E–AVR–10/02

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The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOT-TOM. The interrupt flag can be used to generate an interrupt each time the counterreaches the BOTTOM value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms onthe OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM. Aninverted PWM output can be generated by setting the COM21:0 to 3 (see Table 53 onpage 123). The actual OC2 value will only be visible on the port pin if the data directionfor the port pin is set as output. The PWM waveform is generated by clearing (or setting)the OC2 Register at the compare match between OCR2 and TCNT2 when the counterincrements, and setting (or clearing) the OC2 Register at compare match betweenOCR2 and TCNT2 when the counter decrements. The PWM frequency for the outputwhen using phase correct PWM can be calculated by the following equation:


The extreme values for the OCR2 Register represent special cases when generating aPWM waveform output in the phase correct PWM mode. If the OCR2 is set equal toBOTTOM, the output will be continuously low and if set equal to MAX the output will becontinuously high for non-inverted PWM mode. For inverted PWM the output will havethe opposite logic values.


The following figures show the Timer/Counter in Synchronous mode, and the timer clock(clkT2) is therefore shown as a clock enable signal. In Asynchronous mode, clkI/O shouldbe replaced by the Timer/Counter Oscillator clock. The figures include information onwhen interrupt flags are set. Figure 60 contains timing data for basic Timer/Counteroperation. The figure shows the count sequence close to the MAX value in all modesother than phase correct PWM mode.

TOVn Interrupt Flag Set


1 2 3

TCNTn

Period

OCn

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Update

fOCnPCPWM

fclk_I/O

N 510⋅------------------=

1192466E–AVR–10/02




Figure 62 shows the setting of OCF2 in all modes except CTC mode.

Figure 62. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8)

clkTn(clkI/O/1)

TOVn

clkI/O


TOVn


clkI/O

clkTn(clkI/O/8)

OCFn

OCRn

TCNTn

OCRn Value

OCRn - 1 OCRn OCRn + 1 OCRn + 2

clkI/O

clkTn(clkI/O/8)

120 ATmega16(L) 2466E–AVR–10/02

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Figure 63 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.

Figure 63. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, withPrescaler (fclk_I/O/8)


Timer/Counter Control Register – TCCR2

• Bit 7 – FOC2: Force Output Compare

The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, forensuring compatibility with future devices, this bit must be set to zero when TCCR2 iswritten when operating in PWM mode. When writing a logical one to the FOC2 bit, animmediate compare match is forced on the waveform generation unit. The OC2 output ischanged according to its COM21:0 bits setting. Note that the FOC2 bit is implementedas a strobe. Therefore it is the value present in the COM21:0 bits that determines theeffect of the forced compare.

A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC modeusing OCR2 as TOP.

The FOC2 bit is always read as zero.

• Bit 6, 3 – WGM21:0: Waveform Generation Mode

These bits control the counting sequence of the counter, the source for the maximum(TOP) counter value, and what type of waveform generation to be used. Modes of oper-ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Comparematch (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table50 and “Modes of Operation” on page 115.

OCFn

OCRn

CNTnCTC)

TOP


clkI/O

clkTnclkI/O/8)

Bit 7 6 5 4 3 2 1 0

FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 TCCR2

Read/Write W R/W R/W R/W R/W R/W R/W R/W


1212466E–AVR–10/02

Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 def-initions. However, the functionality and location of these bits are compatible withprevious versions of the timer.

• Bit 5:4 – COM21:0: Compare Match Output Mode

These bits control the Output Compare pin (OC2) behavior. If one or both of theCOM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/Opin it is connected to. However, note that the Data Direction Register (DDR) bit corre-sponding to OC2 pin must be set in order to enable the output driver.

When OC2 is connected to the pin, the function of the COM21:0 bits depends on theWGM21:0 bit setting. Table 51 shows the COM21:0 bit functionality when the WGM21:0bits are set to a normal or CTC mode (non-PWM).

Table 52 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fastPWM mode.

Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, thecompare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode”on page 117 for more details.

Table 53 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phasecorrect PWM mode


ModeWGM21(CTC2)

WGM20(PWM2)

Timer/Counter Mode of Operation TOP

Update ofOCR2

TOV2 FlagSet on

0 0 0 Normal 0xFF Immediate MAX

1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM

2 1 0 CTC OCR2 Immediate MAX

3 1 1 Fast PWM 0xFF TOP MAX

Table 51. Compare Output Mode, non-PWM Mode



0 1 Toggle OC2 on compare match

1 0 Clear OC2 on compare match

1 1 Set OC2 on compare match

Table 52. Compare Output Mode, Fast PWM Mode(1)



0 1 Reserved

1 0 Clear OC2 on compare match, set OC2 at TOP

1 1 Set OC2 on compare match, clear OC2 at TOP

122 ATmega16(L) 2466E–AVR–10/02

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.

Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, thecompare match is ignored, but the set or clear is done at TOP. See “Phase CorrectPWM Mode” on page 118 for more details.


The three Clock Select bits select the clock source to be used by the Timer/Counter, seeTable 54.

Timer/Counter Register – TCNT2

The Timer/Counter Register gives direct access, both for read and write operations, tothe Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes)the compare match on the following timer clock. Modifying the counter (TCNT2) whilethe counter is running, introduces a risk of missing a compare match between TCNT2and the OCR2 Register.

Table 53. Compare Output Mode, Phase Correct PWM Mode(1)



0 1 Reserved

1 0 Clear OC2 on compare match when up-counting. Set OC2 on compare match when downcounting.

1 1 Set OC2 on compare match when up-counting. Clear OC2 on compare match when downcounting.




0 0 1 clkT2S/(No prescaling)

0 1 0 clkT2S/8 (From prescaler)






Bit 7 6 5 4 3 2 1 0

TCNT2[7:0] TCNT2



1232466E–AVR–10/02

Output Compare Register – OCR2

The Output Compare Register contains an 8-bit value that is continuously comparedwith the counter value (TCNT2). A match can be used to generate an output compareinterrupt, or to generate a waveform output on the OC2 pin.

Asynchronous Operation of the Timer/Counter

Asynchronous Status Register – ASSR

• Bit 3 – AS2: Asynchronous Timer/Counter2

When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clkI/O. WhenAS2 is written to one, Timer/Counter2 is clocked from a Crystal Oscillator connected tothe Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents ofTCNT2, OCR2, and TCCR2 might be corrupted.

• Bit 2 – TCN2UB: Timer/Counter2 Update Busy

When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomesset. When TCNT2 has been updated from the temporary storage register, this bit iscleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to beupdated with a new value.

• Bit 1 – OCR2UB: Output Compare Register2 Update Busy

When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomesset. When OCR2 has been updated from the temporary storage register, this bit iscleared by hardware. A logical zero in this bit indicates that OCR2 is ready to beupdated with a new value.

• Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy

When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomesset. When TCCR2 has been updated from the temporary storage register, this bit iscleared by hardware. A logical zero in this bit indicates that TCCR2 is ready to beupdated with a new value.

If a write is performed to any of the three Timer/Counter2 registers while its update busyflag is set, the updated value might get corrupted and cause an unintentional interrupt tooccur.

The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When readingTCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in thetemporary storage register is read.

Bit 7 6 5 4 3 2 1 0

OCR2[7:0] OCR2



Bit 7 6 5 4 3 2 1 0

– – – – AS2 TCN2UB OCR2UB TCR2UB ASSR

Read/Write R R R R R/W R R R


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Asynchronous Operation of Timer/Counter2

When Timer/Counter2 operates asynchronously, some considerations must be taken.

• Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the timer registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock source is:

1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2.

2. Select clock source by setting AS2 as appropriate.

3. Write new values to TCNT2, OCR2, and TCCR2.

4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB.

5. Clear the Timer/Counter2 interrupt flags.

6. Enable interrupts, if needed.

• The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main clock frequency must be more than four times the Oscillator frequency.

• When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means for example that writing to TCNT2 does not disturb an OCR2 write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register – ASSR has been implemented.

• When entering Power-save or Extended Standby mode after having written to TCNT2, OCR2, or TCCR2, the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if the Output Compare2 interrupt is used to wake up the device, since the output compare function is disabled during writing to OCR2 or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up.

• If Timer/Counter2 is used to wake the device up from Power-save or Extended Standby mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power-save or Extended Standby mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed:

1. Write a value to TCCR2, TCNT2, or OCR2.

2. Wait until the corresponding Update Busy flag in ASSR returns to zero.

3. Enter Power-save or Extended Standby mode.

• When the asynchronous operation is selected, the 32.768 kHz Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 registers must be considered lost after a wake-up

1252466E–AVR–10/02

from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.

• Description of wake up from Power-save or Extended Standby mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP.

• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows:

1. Write any value to either of the registers OCR2 or TCCR2.

2. Wait for the corresponding Update Busy Flag to be cleared.

3. Read TCNT2.

• During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag. The output compare pin is changed on the timer clock and is not synchronized to the processor clock.

Timer/Counter Interrupt Mask Register – TIMSK

• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable

When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), theTimer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt isexecuted if a compare match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set inthe Timer/Counter Interrupt Flag Register – TIFR.

• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), theTimer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed ifan overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in theTimer/Counter Interrupt Flag Register – TIFR.

Bit 7 6 5 4 3 2 1 0




126 ATmega16(L) 2466E–AVR–10/02

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• Bit 7 – OCF2: Output Compare Flag 2

The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware whenexecuting the corresponding interrupt handling vector. Alternatively, OCF2 is cleared bywriting a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Com-pare match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Comparematch Interrupt is executed.

• Bit 6 – TOV2: Timer/Counter2 Overflow Flag

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is clearedby hardware when executing the corresponding interrupt handling vector. Alternatively,TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2(Timer/Counter2 Overf low Interrupt Enable), and TOV2 are set (one), theTimer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set whenTimer/Counter2 changes counting direction at $00.

Timer/Counter Prescaler Figure 64. Prescaler for Timer/Counter2

The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected tothe main system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asyn-chronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a RealTime Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected fromPort C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serveas an independent clock source for Timer/Counter2. The Oscillator is optimized for usewith a 32.768 kHz crystal. Applying an external clock source to TOSC1 is notrecommended.

Bit 7 6 5 4 3 2 1 0




10-BIT T/C PRESCALER

TIMER/COUNTER2 CLOCK SOURCE

clkI/O clkT2S

TOSC1

AS2

CS20CS21CS22

clk T

2S/8

clk T

2S/6

4

clk T

2S/1

28

clk T

2S/1

024

clk T

2S/2

56

clk T

2S/3

2

0PSR2

Clear

clkT2

1272466E–AVR–10/02

For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64,clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may beselected. Setting the PSR2 bit in SFIOR resets the prescaler. This allows the user tooperate with a predictable prescaler.


• Bit 1 – PSR2: Prescaler Reset Timer/Counter2

When this bit is written to one, the Timer/Counter2 prescaler will be reset. The bit will becleared by hardware after the operation is performed. Writing a zero to this bit will haveno effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internalCPU clock. If this bit is written when Timer/Counter2 is operating in asynchronousmode, the bit will remain one until the prescaler has been reset.

Bit 7 6 5 4 3 2 1 0




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Serial Peripheral Interface – SPI

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transferbetween the ATmega16 and peripheral devices or between several AVR devices. TheATmega16 SPI includes the following features:• Full-duplex, Three-wire Synchronous Data Transfer• Master or Slave Operation• LSB First or MSB First Data Transfer• Seven Programmable Bit Rates• End of Transmission Interrupt Flag• Write Collision Flag Protection• Wake-up from Idle Mode• Double Speed (CK/2) Master SPI Mode

Figure 65. SPI Block Diagram(1)

Note: 1. Refer to Figure 1 on page 2, and Table 25 on page 55 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 66.The system consists of two Shift Registers, and a Master clock generator. The SPI Mas-ter initiates the communication cycle when pulling low the Slave Select SS pin of thedesired Slave. Master and Slave prepare the data to be sent in their respective ShiftRegisters, and the Master generates the required clock pulses on the SCK line to inter-change data. Data is always shifted from Master to Slave on the Master Out – Slave In,MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. Aftereach data packet, the Master will synchronize the Slave by pulling high the Slave Select,SS, line.

SP

I2X

SP

I2X

DIVIDER/2/4/8/16/32/64/128

1292466E–AVR–10/02

When configured as a Master, the SPI interface has no automatic control of the SS line.This must be handled by user software before communication can start. When this isdone, writing a byte to the SPI Data Register starts the SPI clock generator, and thehardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock gener-ator stops, setting the end of transmission flag (SPIF). If the SPI Interrupt Enable bit(SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continueto shift the next byte by writing it into SPDR, or signal the end of packet by pulling highthe Slave Select, SS line. The last incoming byte will be kept in the buffer register forlater use.

When configured as a Slave, the SPI interface will remain sleeping with MISO tri-statedas long as the SS pin is driven high. In this state, software may update the contents ofthe SPI Data Register, SPDR, but the data will not be shifted out by incoming clockpulses on the SCK pin until the SS pin is driven low. As one byte has been completelyshifted, the end of transmission flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, inthe SPCR register is set, an interrupt is requested. The Slave may continue to placenew data to be sent into SPDR before reading the incoming data. The last incoming bytewill be kept in the buffer register for later use.

Figure 66. SPI Master-slave Interconnection

The system is single buffered in the transmit direction and double buffered in the receivedirection. This means that bytes to be transmitted cannot be written to the SPI DataRegister before the entire shift cycle is completed. When receiving data, however, areceived character must be read from the SPI Data Register before the next characterhas been completely shifted in. Otherwise, the first byte is lost.

In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. Toensure correct sampling of the clock signal, the frequency of the SPI clock should neverexceed fosc/4.

When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins isoverridden according to Table 55. For more details on automatic port overrides, refer to“Alternate Port Functions” on page 52.

Table 55. SPI Pin Overrides

Pin Direction, Master SPI Direction, Slave SPI

MOSI User Defined Input

MISO Input User Defined

SCK User Defined Input

SS User Defined Input

MSB MASTER LSB

8 BIT SHIFT REGISTER

MSB SLAVE LSB

8 BIT SHIFT REGISTERMISO

MOSI

SPICLOCK GENERATOR

SCK

SS

MISO

MOSI

SCK

SS

SHIFTENABLE

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Note: See “Alternate Functions of Port B” on page 55 for a detailed description of how to definethe direction of the user defined SPI pins.

The following code examples show how to initialize the SPI as a master and how to per-form a simple transmission. DDR_SPI in the examples must be replaced by the actualData Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCKmust be replaced by the actual data direction bits for these pins. For example if MOSI isplaced on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.



SPI_MasterInit:

; Set MOSI and SCK output, all others input

ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)

out DDR_SPI,r17

; Enable SPI, Master, set clock rate fck/16

ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)

out SPCR,r17

ret

SPI_MasterTransmit:

; Start transmission of data (r16)

out SPDR,r16

Wait_Transmit:

; Wait for transmission complete

sbis SPSR,SPIF

rjmp Wait_Transmit

ret

C Code Example(1)

void SPI_MasterInit(void)

/* Set MOSI and SCK output, all others input */

DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);

/* Enable SPI, Master, set clock rate fck/16 */

SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);

void SPI_MasterTransmit(char cData)

/* Start transmission */

SPDR = cData;

/* Wait for transmission complete */

while(!(SPSR & (1<<SPIF)))

;

1312466E–AVR–10/02

The following code examples show how to initialize the SPI as a Slave and how to per-form a simple reception.


SS Pin Functionality

Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. WhenSS is held low, the SPI is activated, and MISO becomes an output if configured so bythe user. All other pins are inputs. When SS is driven high, all pins are inputs, and theSPI is passive, which means that it will not receive incoming data. Note that the SPIlogic will be reset once the SS pin is driven high.

The SS pin is useful for packet/byte synchronization to keep the slave bit counter syn-chronous with the master clock generator. When the SS pin is driven high, the SPI Slave


SPI_SlaveInit:

; Set MISO output, all others input

ldi r17,(1<<DD_MISO)

out DDR_SPI,r17

; Enable SPI

ldi r17,(1<<SPE)

out SPCR,r17

ret

SPI_SlaveReceive:

; Wait for reception complete

sbis SPSR,SPIF

rjmp SPI_SlaveReceive

; Read received data and return

in r16,SPDR

ret

C Code Example(1)

void SPI_SlaveInit(void)

/* Set MISO output, all others input */

DDR_SPI = (1<<DD_MISO);

/* Enable SPI */

SPCR = (1<<SPE);

char SPI_SlaveReceive(void)

/* Wait for reception complete */

while(!(SPSR & (1<<SPIF)))

;

/* Return data register */

return SPDR;

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will immediately reset the send and receive logic, and drop any partially received data inthe Shift Register.

Master Mode When the SPI is configured as a Master (MSTR in SPCR is set), the user can determinethe direction of the SS pin.

If SS is configured as an output, the pin is a general output pin which does not affect theSPI system. Typically, the pin will be driving the SS pin of the SPI Slave.

If SS is configured as an input, it must be held high to ensure Master SPI operation. Ifthe SS pin is driven low by peripheral circuitry when the SPI is configured as a Masterwith the SS pin defined as an input, the SPI system interprets this as another masterselecting the SPI as a slave and starting to send data to it. To avoid bus contention, theSPI system takes the following actions:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of the SPI becoming a slave, the MOSI and SCK pins become inputs.

2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt routine will be executed.

Thus, when interrupt-driven SPI transmission is used in master mode, and there exists apossibility that SS is driven low, the interrupt should always check that the MSTR bit isstill set. If the MSTR bit has been cleared by a slave select, it must be set by the user tore-enable SPI master mode.

SPI Control Register – SPCR

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is setand the if the global interrupt enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

When the SPE bit is written to one, the SPI is enabled. This bit must be set to enableany SPI operations.

• Bit 5 – DORD: Data Order

When the DORD bit is written to one, the LSB of the data word is transmitted first.

When the DORD bit is written to zero, the MSB of the data word is transmitted first.

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI mode when written to one, and Slave SPI mode when writtenlogic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR willbe cleared, and SPIF in SPSR will become set. The user will then have to set MSTR tore-enable SPI Master mode.

Bit 7 6 5 4 3 2 1 0

SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR



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• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero,SCK is low when idle. Refer to Figure 67 and Figure 68 for an example. The CPOL func-tionality is summarized below:

• Bit 2 – CPHA: Clock Phase

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading(first) or trailing (last) edge of SCK. Refer to Figure 67 and Figure 68 for an example.The CPHA functionality is summarized below:

• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 andSPR0 have no effect on the Slave. The relationship between SCK and the OscillatorClock frequency fosc is shown in the following table:

SPI Status Register – SPSR

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIEin SPCR is set and global interrupts are enabled. If SS is an input and is driven lowwhen the SPI is in Master mode, this will also set the SPIF flag. SPIF is cleared by

Table 56. CPOL Functionality

CPOL Leading Edge Trailing Edge

0 Rising Falling

1 Falling Rising

Table 57. CPHA Functionality

CPHA Leading Edge Trailing Edge

0 Sample Setup

1 Setup Sample

Table 58. Relationship Between SCK and the Oscillator Frequency

SPI2X SPR1 SPR0 SCK Frequency

0 0 0 fosc/4

0 0 1 fosc/16

0 1 0 fosc/64

0 1 1 fosc/128

1 0 0 fosc/2

1 0 1 fosc/8

1 1 0 fosc/32

1 1 1 fosc/64

Bit 7 6 5 4 3 2 1 0

SPIF WCOL – – – – – SPI2X SPSR

Read/Write R R R R R R R R/W


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hardware when executing the corresponding interrupt handling vector. Alternatively, theSPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessingthe SPI Data Register (SPDR).

• Bit 6 – WCOL: Write COLlision flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Registerwith WCOL set, and then accessing the SPI Data Register.

• Bit 5..1 – Res: Reserved Bits


• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled whenthe SPI is in Master mode (see Table 58). This means that the minimum SCK period willbe two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaran-teed to work at fosc/4 or lower.

The SPI interface on the ATmega16 is also used for program memory and EEPROMdownloading or uploading. See page 268 for SPI Serial Programming and Verification.

SPI Data Register – SPDR

The SPI Data Register is a read/write register used for data transfer between the regis-ter file and the SPI Shift Register. Writing to the register initiates data transmission.Reading the register causes the Shift Register Receive buffer to be read.

Data Modes There are four combinations of SCK phase and polarity with respect to serial data,which are determined by control bits CPHA and CPOL. The SPI data transfer formatsare shown in Figure 67 and Figure 68. Data bits are shifted out and latched in on oppo-site edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This isclearly seen by summarizing Table 56 and Table 57, as done below:

Bit 7 6 5 4 3 2 1 0

MSB LSB SPDR


Initial Value X X X X X X X X Undefined

Table 59. CPOL and CPHA Functionality

Leading Edge Trailing Edge SPI Mode

CPOL = 0, CPHA = 0 Sample (Rising) Setup (Falling) 0

CPOL = 0, CPHA = 1 Setup (Rising) Sample (Falling) 1

CPOL = 1, CPHA = 0 Sample (Falling) Setup (Rising) 2

CPOL = 1, CPHA = 1 Setup (Falling) Sample (Rising) 3

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Figure 67. SPI Transfer Format with CPHA = 0

Figure 68. SPI Transfer Format with CPHA = 1

Bit 1Bit 6

LSBMSB

SCK (CPOL = 0)mode 0

SAMPLE IMOSI/MISO

CHANGE 0MOSI PIN

CHANGE 0MISO PIN


SS

MSBLSB

Bit 6Bit 1

Bit 5Bit 2

Bit 4Bit 3

Bit 3Bit 4

Bit 2Bit 5

MSB first (DORD = 0)LSB first (DORD = 1)


SAMPLE IMOSI/MISO

CHANGE 0MOSI PIN

CHANGE 0MISO PIN


SS

MSBLSB

Bit 6Bit 1

Bit 5Bit 2

Bit 4Bit 3

Bit 3Bit 4

Bit 2Bit 5

Bit 1Bit 6

LSBMSB

MSB first (DORD = 0)LSB first (DORD = 1)

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USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter(USART) is a highly flexible serial communication device. The main features are:• Full Duplex Operation (Independent Serial Receive and Transmit Registers)• Asynchronous or Synchronous Operation• Master or Slave Clocked Synchronous Operation• High Resolution Baud Rate Generator• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits• Odd or Even Parity Generation and Parity Check Supported by Hardware• Data OverRun Detection• Framing Error Detection• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter• Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete• Multi-processor Communication Mode• Double Speed Asynchronous Communication Mode

Overview A simplified block diagram of the USART transmitter is shown in Figure 69. CPU acces-sible I/O Registers and I/O pins are shown in bold.

Figure 69. USART Block Diagram(1)

Note: 1. Refer to Figure 1 on page 2, Table 33 on page 62, and Table 27 on page 57 forUSART pin placement.

PARITYGENERATOR

UBRR[H:L]

UDR (Transmit)

UCSRA UCSRB UCSRC

BAUD RATE GENERATOR

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER RxD

TxDPIN

CONTROL

UDR (Receive)

PINCONTROL

XCK

DATARECOVERY

CLOCKRECOVERY

PINCONTROL

TXCONTROL

RXCONTROL

PARITYCHECKER

DA

TA

BU

S

OSC

SYNC LOGIC

Clock Generator

Transmitter

Receiver

1372466E–AVR–10/02

The dashed boxes in the block diagram separate the three main parts of the USART(listed from the top): Clock Generator, Transmitter and Receiver. Control registers areshared by all units. The clock generation logic consists of synchronization logic for exter-nal clock input used by synchronous slave operation, and the baud rate generator. TheXCK (Transfer Clock) pin is only used by Synchronous Transfer mode. The Transmitterconsists of a single write buffer, a serial shift register, parity generator and control logicfor handling different serial frame formats. The write buffer allows a continuous transferof data without any delay between frames. The Receiver is the most complex part of theUSART module due to its clock and data recovery units. The recovery units are used forasynchronous data reception. In addition to the recovery units, the receiver includes aparity checker, control logic, a Shift Register and a two level receive buffer (UDR). Thereceiver supports the same frame formats as the transmitter, and can detect frameerror, data overrun and parity errors.

AVR USART vs. AVR UART – Compatibility

The USART is fully compatible with the AVR UART regarding:

• Bit locations inside all USART Registers

• Baud Rate Generation

• Transmitter Operation

• Transmit Buffer Functionality

• Receiver Operation

However, the receive buffering has two improvements that will affect the compatibility insome special cases:

• A second buffer register has been added. The two buffer registers operate as a circular FIFO buffer. Therefore the UDR must only be read once for each incoming data! More important is the fact that the error flags (FE and DOR) and the 9th data bit (RXB8) are buffered with the data in the receive buffer. Therefore the status bits must always be read before the UDR Register is read. Otherwise the error status will be lost since the buffer state is lost.

• The receiver Shift Register can now act as a third buffer level. This is done by allowing the received data to remain in the serial Shift Register (see Figure 69) if the buffer registers are full, until a new start bit is detected. The USART is therefore more resistant to Data OverRun (DOR) error conditions.

The following control bits have changed name, but have same functionality and registerlocation:

• CHR9 is changed to UCSZ2

• OR is changed to DOR

Clock Generation The clock generation logic generates the base clock for the Transmitter and Receiver.The USART supports four modes of clock operation: Normal Asynchronous, DoubleSpeed Asynchronous, Master Synchronous and Slave Synchronous mode. The UMSELbit in USART Control and Status Register C (UCSRC) selects between asynchronousand synchronous operation. Double Speed (Asynchronous mode only) is controlled bythe U2X found in the UCSRA Register. When using Synchronous mode (UMSEL = 1),the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clocksource is internal (Master mode) or external (Slave mode). The XCK pin is only activewhen using Synchronous mode.

Figure 70 shows a block diagram of the clock generation logic.

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Figure 70. Clock Generation Logic, Block Diagram

Signal description:

txclk Transmitter clock (Internal Signal).

rxclk Receiver base clock (Internal Signal).

xcki Input from XCK pin (Internal Signal). Used for synchronous slave operation.

xcko Clock output to XCK pin (Internal Signal). Used for synchronous masteroperation.

fosc XTAL pin frequency (System Clock).

Internal Clock Generation – The Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous mastermodes of operation. The description in this section refers to Figure 70.

The USART Baud Rate Register (UBRR) and the down-counter connected to it functionas a programmable prescaler or baud rate generator. The down-counter, running at sys-tem clock (fosc), is loaded with the UBRR value each time the counter has counteddown to zero or when the UBRRL Register is written. A clock is generated each time thecounter reaches zero. This clock is the baud rate generator clock output (=fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2, 8 or16 depending on mode. The baud rate generator output is used directly by the receiver’sclock and data recovery units. However, the recovery units use a state machine thatuses 2, 8 or 16 states depending on mode set by the state of the UMSEL, U2X andDDR_XCK bits.

Table 60 contains equations for calculating the baud rate (in bits per second) and forcalculating the UBRR value for each mode of operation using an internally generatedclock source.

PrescalingDown-Counter

/ 2

UBRR

/ 4 / 2

fosc

UBRR+1

SyncRegister

OSC

XCKPin

txclk

U2X

UMSEL

DDR_XCK

0

1

0

1

xcki

xcko

DDR_XCKrxclk

0

1

1

0

EdgeDetector

UCPOL

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Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps).

BAUD Baud rate (in bits per second, bps)

fOSC System Oscillator clock frequency

UBRR Contents of the UBRRH and UBRRL Registers, (0 - 4095)

Some examples of UBRR values for some system clock frequencies are found in Table68 (see page 162).

Double Speed Operation (U2X)

The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit onlyhas effect for the asynchronous operation. Set this bit to zero when using synchronousoperation.

Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectivelydoubling the transfer rate for asynchronous communication. Note however that thereceiver will in this case only use half the number of samples (reduced from 16 to 8) fordata sampling and clock recovery, and therefore a more accurate baud rate setting andsystem clock are required when this mode is used. For the Transmitter, there are nodownsides.

External Clock External clocking is used by the synchronous slave modes of operation. The descriptionin this section refers to Figure 70 for details.

External clock input from the XCK pin is sampled by a synchronization register to mini-mize the chance of meta-stability. The output from the synchronization register mustthen pass through an edge detector before it can be used by the Transmitter andreceiver. This process introduces a two CPU clock period delay and therefore the maxi-mum external XCK clock frequency is limited by the following equation:

Note that fosc depends on the stability of the system clock source. It is therefore recom-mended to add some margin to avoid possible loss of data due to frequency variations.

Synchronous Clock Operation When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clockinput (Slave) or clock output (Master). The dependency between the clock edges anddata sampling or data change is the same. The basic principle is that data input (onRxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) ischanged.

Table 60. Equations for Calculating Baud Rate Register Setting

Operating ModeEquation for Calculating

Baud Rate(1)

Equation for Calculating UBRR

Value

Asynchronous Normal Mode (U2X = 0)

Asynchronous Double Speed Mode (U2X = 1)

Synchronous Master Mode

BAUDfOSC

16 UBRR 1+( )---------------------------------------= UBRR

fOSC

16BAUD------------------------ 1–=

BAUDfOSC

8 UBRR 1+( )-----------------------------------= UBRR

fOSC

8BAUD-------------------- 1–=

BAUDfOSC

2 UBRR 1+( )-----------------------------------= UBRR

fOSC

2BAUD-------------------- 1–=

fXCK

fOSC

4-----------<

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Figure 71. Synchronous Mode XCK Timing.

The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling andwhich is used for data change. As Figure 71 shows, when UCPOL is zero the data willbe changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, thedata will be changed at falling XCK edge and sampled at rising XCK edge.

Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (startand stop bits), and optionally a parity bit for error checking. The USART accepts all 30combinations of the following as valid frame formats:

• 1 start bit

• 5, 6, 7, 8, or 9 data bits

• no, even or odd parity bit

• 1 or 2 stop bits

A frame starts with the start bit followed by the least significant data bit. Then the nextdata bits, up to a total of nine, are succeeding, ending with the most significant bit. Ifenabled, the parity bit is inserted after the data bits, before the stop bits. When a com-plete frame is transmitted, it can be directly followed by a new frame, or thecommunication line can be set to an idle (high) state. Figure 72 illustrates the possiblecombinations of the frame formats. Bits inside brackets are optional.

Figure 72. Frame Formats

St Start bit, always low.

(n) Data bits (0 to 8).

P Parity bit. Can be odd or even.

Sp Stop bit, always high.

IDLE No transfers on the communication line (RxD or TxD). An IDLE line must behigh.

The frame format used by the USART is set by the UCSZ2:0, UPM1:0, and USBS bits inUCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note thatchanging the setting of any of these bits will corrupt all ongoing communication for boththe Receiver and Transmitter.

RxD / TxD

XCK

RxD / TxD

XCKUCPOL = 0

UCPOL = 1

Sample

Sample

10 2 3 4 [5] [6] [7] [8] [P]St Sp1 [Sp2] (St / IDLE)(IDLE)

FRAME

1412466E–AVR–10/02

The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame.The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selec-tion between one or two stop bits is done by the USART Stop Bit Select (USBS) bit. Thereceiver ignores the second stop bit. An FE (Frame Error) will therefore only be detectedin the cases where the first stop bit is zero.

Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity isused, the result of the exclusive or is inverted. The relation between the parity bit anddata bits is as follows::

Peven Parity bit using even parity

Podd Parity bit using odd parity

dn Data bit n of the character

If used, the parity bit is located between the last data bit and first stop bit of a serialframe.

Peven dn 1– … d3 d2 d1 d0 0Podd

⊕ ⊕ ⊕ ⊕ ⊕ ⊕dn 1– … d3 d2 d1 d0 1⊕ ⊕ ⊕ ⊕ ⊕ ⊕

==

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USART Initialization The USART has to be initialized before any communication can take place. The initial-ization process normally consists of setting the baud rate, setting frame format andenabling the Transmitter or the Receiver depending on the usage. For interrupt drivenUSART operation, the global interrupt flag should be cleared (and interrupts globally dis-abled) when doing the initialization.

Before doing a re-initialization with changed baud rate or frame format, be sure thatthere are no ongoing transmissions during the period the registers are changed. TheTXC flag can be used to check that the Transmitter has completed all transfers, and theRXC flag can be used to check that there are no unread data in the receive buffer. Notethat the TXC flag must be cleared before each transmission (before UDR is written) if itis used for this purpose.

The following simple USART initialization code examples show one assembly and oneC function that are equal in functionality. The examples assume asynchronous opera-tion using polling (no interrupts enabled) and a fixed frame format. The baud rate isgiven as a function parameter. For the assembly code, the baud rate parameter isassumed to be stored in the r17:r16 registers. When the function writes to the UCSRCRegister, the URSEL bit (MSB) must be set due to the sharing of I/O location by UBRRHand UCSRC.


More advanced initialization routines can be made that include frame format as parame-ters, disable interrupts and so on. However, many applications use a fixed setting of thebaud and control registers, and for these types of applications the initialization code canbe placed directly in the main routine, or be combined with initialization code for otherI/O modules.


USART_Init:

; Set baud rate

out UBRRH, r17

out UBRRL, r16

; Enable receiver and transmitter

ldi r16, (1<<RXEN)|(1<<TXEN)

out UCSRB,r16

; Set frame format: 8data, 2stop bit

ldi r16, (1<<URSEL)|(1<<USBS)|(3<<UCSZ0)

out UCSRC,r16

ret

C Code Example(1)

void USART_Init( unsigned int baud )

/* Set baud rate */

UBRRH = (unsigned char)(baud>>8);

UBRRL = (unsigned char)baud;

/* Enable receiver and transmitter */

UCSRB = (1<<RXEN)|(1<<TXEN);

/* Set frame format: 8data, 2stop bit */

UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0);

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Data Transmission – The USART Transmitter

The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in theUCSRB Register. When the Transmitter is enabled, the normal port operation of theTxD pin is overridden by the USART and given the function as the transmitter’s serialoutput. The baud rate, mode of operation and frame format must be set up once beforedoing any transmissions. If synchronous operation is used, the clock on the XCK pin willbe overridden and used as transmission clock.

Sending Frames with 5 to 8 Data Bit

A data transmission is initiated by loading the transmit buffer with the data to be trans-mitted. The CPU can load the transmit buffer by writing to the UDR I/O location. Thebuffered data in the transmit buffer will be moved to the Shift Register when the ShiftRegister is ready to send a new frame. The Shift Register is loaded with new data if it isin idle state (no ongoing transmission) or immediately after the last stop bit of the previ-ous frame is transmitted. When the Shift Register is loaded with new data, it will transferone complete frame at the rate given by the baud register, U2X bit or by XCK dependingon mode of operation.

The following code examples show a simple USART transmit function based on pollingof the Data Register Empty (UDRE) flag. When using frames with less than eight bits,the most significant bits written to the UDR are ignored. The USART has to be initializedbefore the function can be used. For the assembly code, the data to be sent is assumedto be stored in Register R16


The function simply waits for the transmit buffer to be empty by checking the UDRE flag,before loading it with new data to be transmitted. If the data register empty interrupt isutilized, the interrupt routine writes the data into the buffer.


USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRA,UDRE

rjmp USART_Transmit

; Put data (r16) into buffer, sends the data

out UDR,r16

ret

C Code Example(1)

void USART_Transmit( unsigned char data )

/* Wait for empty transmit buffer */

while ( !( UCSRA & (1<<UDRE)) )

;

/* Put data into buffer, sends the data */

UDR = data;

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Sending Frames with 9 Data Bit

If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit inUCSRB before the low byte of the character is written to UDR. The following codeexamples show a transmit function that handles 9-bit characters. For the assemblycode, the data to be sent is assumed to be stored in Registers R17:R16.

Note: 1. These transmit functions are written to be general functions. They can be optimized ifthe contents of the UCSRB is static. (i.e., only the TXB8 bit of the UCSRB Register isused after initialization).

The ninth bit can be used for indicating an address frame when using multi processorcommunication mode or for other protocol handling as for example synchronization.

Transmitter Flags and Interrupts

The USART transmitter has two flags that indicate its state: USART Data RegisterEmpty (UDRE) and Transmit Complete (TXC). Both flags can be used for generatinginterrupts.

The Data Register Empty (UDRE) flag indicates whether the transmit buffer is ready toreceive new data. This bit is set when the transmit buffer is empty, and cleared when thetransmit buffer contains data to be transmitted that has not yet been moved into the ShiftRegister. For compatibility with future devices, always write this bit to zero when writingthe UCSRA register.

When the Data Register empty Interrupt Enable (UDRIE) bit in UCSRB is written to one,the USART Data Register Empty Interrupt will be executed as long as UDRE is set (pro-vided that global interrupts are enabled). UDRE is cleared by writing UDR. Wheninterrupt-driven data transmission is used, the data register empty Interrupt routine must


USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRA,UDRE

rjmp USART_Transmit

; Copy 9th bit from r17 to TXB8

cbi UCSRB,TXB8

sbrc r17,0

sbi UCSRB,TXB8

; Put LSB data (r16) into buffer, sends the data

out UDR,r16

ret

C Code Example(1)

void USART_Transmit( unsigned int data )

/* Wait for empty transmit buffer */

while ( !( UCSRA & (1<<UDRE))) )

;

/* Copy 9th bit to TXB8 */

UCSRB &= ~(1<<TXB8);

if ( data & 0x0100 )

UCSRB |= (1<<TXB8);

/* Put data into buffer, sends the data */

UDR = data;

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either write new data to UDR in order to clear UDRE or disable the Data Register emptyInterrupt, otherwise a new interrupt will occur once the interrupt routine terminates.

The Transmit Complete (TXC) flag bit is set one when the entire frame in the transmitShift Register has been shifted out and there are no new data currently present in thetransmit buffer. The TXC flag bit is automatically cleared when a transmit completeinterrupt is executed, or it can be cleared by writing a one to its bit location. The TXCflag is useful in half-duplex communication interfaces (like the RS485 standard), wherea transmitting application must enter receive mode and free the communication busimmediately after completing the transmission.

When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USARTTransmit Complete Interrupt will be executed when the TXC flag becomes set (providedthat global interrupts are enabled). When the transmit complete interrupt is used, theinterrupt handling routine does not have to clear the TXC flag, this is done automaticallywhen the interrupt is executed.

Parity Generator The parity generator calculates the parity bit for the serial frame data. When parity bit isenabled (UPM1 = 1), the transmitter control logic inserts the parity bit between the lastdata bit and the first stop bit of the frame that is sent.

Disabling the Transmitter The disabling of the transmitter (setting the TXEN to zero) will not become effective untilongoing and pending transmissions are completed, i.e., when the transmit Shift Registerand transmit Buffer Register do not contain data to be transmitted. When disabled, thetransmitter will no longer override the TxD pin.

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Data Reception – The USART Receiver

The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in theUCSRB Register to one. When the receiver is enabled, the normal pin operation of theRxD pin is overridden by the USART and given the function as the receiver’s serialinput. The baud rate, mode of operation and frame format must be set up once beforeany serial reception can be done. If synchronous operation is used, the clock on theXCK pin will be used as transfer clock.

Receiving Frames with 5 to 8 Data Bits

The receiver starts data reception when it detects a valid start bit. Each bit that followsthe start bit will be sampled at the baud rate or XCK clock, and shifted into the receiveShift Register until the first stop bit of a frame is received. A second stop bit will beignored by the receiver. When the first stop bit is received, i.e., a complete serial frameis present in the receive Shift Register, the contents of the Shift Register will be movedinto the receive buffer. The receive buffer can then be read by reading the UDR I/Olocation.

The following code example shows a simple USART receive function based on pollingof the Receive Complete (RXC) flag. When using frames with less than eight bits themost significant bits of the data read from the UDR will be masked to zero. The USARThas to be initialized before the function can be used.


The function simply waits for data to be present in the receive buffer by checking theRXC flag, before reading the buffer and returning the value.


USART_Receive:

; Wait for data to be received

sbis UCSRA, RXC

rjmp USART_Receive

; Get and return received data from buffer

in r16, UDR

ret

C Code Example(1)

unsigned char USART_Receive( void )

/* Wait for data to be received */

while ( !(UCSRA & (1<<RXC)) )

;

/* Get and return received data from buffer */

return UDR;

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Receiving Frames with 9 Databits

If 9 bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit inUCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR andPE status flags as well. Read status from UCSRA, then data from UDR. Reading theUDR I/O location will change the state of the receive buffer FIFO and consequently theTXB8, FE, DOR and PE bits, which all are stored in the FIFO, will change.

The following code example shows a simple USART receive function that handles both9-bit characters and the status bits.



USART_Receive:

; Wait for data to be received

sbis UCSRA, RXC

rjmp USART_Receive

; Get status and 9th bit, then data from buffer

in r18, UCSRA

in r17, UCSRB

in r16, UDR

; If error, return -1

andi r18,(1<<FE)|(1<<DOR)|(1<<PE)

breq USART_ReceiveNoError

ldi r17, HIGH(-1)

ldi r16, LOW(-1)

USART_ReceiveNoError:

; Filter the 9th bit, then return

lsr r17

andi r17, 0x01

ret

C Code Example(1)

unsigned int USART_Receive( void )

unsigned char status, resh, resl;

/* Wait for data to be received */

while ( !(UCSRA & (1<<RXC)) )

;

/* Get status and 9th bit, then data */

/* from buffer */

status = UCSRA;

resh = UCSRB;

resl = UDR;

/* If error, return -1 */

if ( status & (1<<FE)|(1<<DOR)|(1<<PE) )

return -1;

/* Filter the 9th bit, then return */

resh = (resh >> 1) & 0x01;

return ((resh << 8) | resl);

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The receive function example reads all the I/O registers into the register file before anycomputation is done. This gives an optimal receive buffer utilization since the bufferlocation read will be free to accept new data as early as possible.

Receive Compete Flag and Interrupt

The USART Receiver has one flag that indicates the receiver state.

The Receive Complete (RXC) flag indicates if there are unread data present in thereceive buffer. This flag is one when unread data exist in the receive buffer, and zerowhen the receive buffer is empty (i.e., does not contain any unread data). If the receiveris disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bitwill become zero.

When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USARTReceive Complete Interrupt will be executed as long as the RXC flag is set (providedthat global interrupts are enabled). When interrupt-driven data reception is used, thereceive complete routine must read the received data from UDR in order to clear theRXC flag, otherwise a new interrupt will occur once the interrupt routine terminates.

Receiver Error Flags The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) andParity Error (PE). All can be accessed by reading UCSRA. Common for the error flags isthat they are located in the receive buffer together with the frame for which they indicatethe error status. Due to the buffering of the error flags, the UCSRA must be read beforethe receive buffer (UDR), since reading the UDR I/O location changes the buffer readlocation. Another equality for the error flags is that they can not be altered by softwaredoing a write to the flag location. However, all flags must be set to zero when theUCSRA is written for upward compatibility of future USART implementations. None ofthe error flags can generate interrupts.

The Frame Error (FE) flag indicates the state of the first stop bit of the next readableframe stored in the receive buffer. The FE flag is zero when the stop bit was correctlyread (as one), and the FE flag will be one when the stop bit was incorrect (zero). Thisflag can be used for detecting out-of-sync conditions, detecting break conditions andprotocol handling. The FE flag is not affected by the setting of the USBS bit in UCSRCsince the receiver ignores all, except for the first, stop bits. For compatibility with futuredevices, always set this bit to zero when writing to UCSRA.

The Data OverRun (DOR) flag indicates data loss due to a receiver buffer full condition.A Data OverRun occurs when the receive buffer is full (two characters), it is a new char-acter waiting in the receive Shift Register, and a new start bit is detected. If the DOR flagis set there was one or more serial frame lost between the frame last read from UDR,and the next frame read from UDR. For compatibility with future devices, always writethis bit to zero when writing to UCSRA. The DOR flag is cleared when the framereceived was successfully moved from the Shift Register to the receive buffer.

The Parity Error (PE) flag indicates that the next frame in the receive buffer had a parityerror when received. If parity check is not enabled the PE bit will always be read zero.For compatibility with future devices, always set this bit to zero when writing to UCSRA.For more details see “Parity Bit Calculation” on page 142 and “Parity Checker” on page149.

Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Typeof parity check to be performed (odd or even) is selected by the UPM0 bit. Whenenabled, the parity checker calculates the parity of the data bits in incoming frames andcompares the result with the parity bit from the serial frame. The result of the check isstored in the receive buffer together with the received data and stop bits. The ParityError (PE) flag can then be read by software to check if the frame had a parity error.

1492466E–AVR–10/02

The PE bit is set if the next character that can be read from the receive buffer had a par-ity error when received and the parity checking was enabled at that point (UPM1 = 1).This bit is valid until the receive buffer (UDR) is read.

Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data fromongoing receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero)the Receiver will no longer override the normal function of the RxD port pin. The receiverbuffer FIFO will be flushed when the receiver is disabled. Remaining data in the bufferwill be lost

Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the bufferwill be emptied of its contents. Unread data will be lost. If the buffer has to be flushedduring normal operation, due to for instance an error condition, read the UDR I/O loca-tion until the RXC flag is cleared. The following code example shows how to flush thereceive buffer.


Asynchronous Data Reception

The USART includes a clock recovery and a data recovery unit for handling asynchro-nous data reception. The clock recovery logic is used for synchronizing the internallygenerated baud rate clock to the incoming asynchronous serial frames at the RxD pin.The data recovery logic samples and low pass filters each incoming bit, thereby improv-ing the noise immunity of the receiver. The asynchronous reception operational rangedepends on the accuracy of the internal baud rate clock, the rate of the incomingframes, and the frame size in number of bits.

Asynchronous Clock Recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Fig-ure 73 illustrates the sampling process of the start bit of an incoming frame. The samplerate is 16 times the baud rate for Normal mode, and 8 times the baud rate for DoubleSpeed mode. The horizontal arrows illustrate the synchronization variation due to thesampling process. Note the larger time variation when using the double speed mode(U2X = 1) of operation. Samples denoted zero are samples done when the RxD line isidle (i.e., no communication activity).


USART_Flush:

sbis UCSRA, RXC

ret

in r16, UDR

rjmp USART_Flush

C Code Example(1)

void USART_Flush( void )

unsigned char dummy;

while ( UCSRA & (1<<RXC) ) dummy = UDR;

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Figure 73. Start Bit Sampling

When the clock recovery logic detects a high (idle) to low (start) transition on the RxDline, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sam-ple as shown in the figure. The clock recovery logic then uses samples 8, 9, and 10 forNormal mode, and samples 4, 5, and 6 for Double Speed mode (indicated with samplenumbers inside boxes on the figure), to decide if a valid start bit is received. If two ormore of these three samples have logical high levels (the majority wins), the start bit isrejected as a noise spike and the receiver starts looking for the next high to low-transi-tion. If however, a valid start bit is detected, the clock recovery logic is synchronized andthe data recovery can begin. The synchronization process is repeated for each start bit.

Asynchronous Data Recovery When the receiver clock is synchronized to the start bit, the data recovery can begin.The data recovery unit uses a state machine that has 16 states for each bit in normalmode and 8 states for each bit in Double Speed mode. Figure 74 shows the sampling ofthe data bits and the parity bit. Each of the samples is given a number that is equal tothe state of the recovery unit.

Figure 74. Sampling of Data and Parity Bit

The decision of the logic level of the received bit is taken by doing a majority voting ofthe logic value to the three samples in the center of the received bit. The center samplesare emphasized on the figure by having the sample number inside boxes. The majorityvoting process is done as follows: If two or all three samples have high levels, thereceived bit is registered to be a logic 1. If two or all three samples have low levels, thereceived bit is registered to be a logic 0. This majority voting process acts as a low passfilter for the incoming signal on the RxD pin. The recovery process is then repeated untila complete frame is received. Including the first stop bit. Note that the receiver only usesthe first stop bit of a frame.

Figure 75 shows the sampling of the stop bit and the earliest possible beginning of thestart bit of the next frame.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2

STARTIDLE

00

BIT 0

3

1 2 3 4 5 6 7 8 1 20

RxD

Sample(U2X = 0)

Sample(U2X = 1)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1

BIT n

1 2 3 4 5 6 7 8 1

RxD

Sample(U2X = 0)

Sample(U2X = 1)

1512466E–AVR–10/02

Figure 75. Stop Bit Sampling and Next Start Bit Sampling

The same majority voting is done to the stop bit as done for the other bits in the frame. Ifthe stop bit is registered to have a logic 0 value, the Frame Error (FE) flag will be set.

A new high to low transition indicating the start bit of a new frame can come right afterthe last of the bits used for majority voting. For Normal Speed mode, the first low levelsample can be at point marked (A) in Figure 75. For Double Speed mode the first lowlevel must be delayed to (B). (C) marks a stop bit of full length. The early start bit detec-tion influences the operational range of the receiver.

Asynchronous Operational Range

The operational range of the receiver is dependent on the mismatch between thereceived bit rate and the internally generated baud rate. If the Transmitter is sendingframes at too fast or too slow bit rates, or the internally generated baud rate of thereceiver does not have a similar (see Table 61) base frequency, the receiver will not beable to synchronize the frames to the start bit.

The following equations can be used to calculate the ratio of the incoming data rate andinternal receiver baud rate.

D Sum of character size and parity size (D = 5 to 10 bit)

S Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed mode.

SF First sample number used for majority voting. SF = 8 for Normal Speed and SF = 4 for Double Speed mode.

SM Middle sample number used for majority voting. SM = 9 for Normal Speed and SM = 5 for Double Speed mode.

Rslow is the ratio of the slowest incoming data rate that can be accepted in relation to thereceiver baud rate. Rfast is the ratio of the fastest incoming data rate that can beaccepted in relation to the receiver baud rate.

1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1

STOP 1

1 2 3 4 5 6 0/1

RxD

Sample(U2X = 0)

Sample(U2X = 1)

(A) (B) (C)

RslowD 1+( )S

S 1– D S⋅ SF+ +-------------------------------------------=

RfastD 2+( )S

D 1+( )S SM+-----------------------------------=

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Table 61 and Table 62 list the maximum receiver baud rate error that can be tolerated.Note that Normal Speed mode has higher toleration of baud rate variations.

The recommendations of the maximum receiver baud rate error was made under theassumption that the receiver and transmitter equally divides the maximum total error.

There are two possible sources for the receivers baud rate error. The receiver’s systemclock (XTAL) will always have some minor instability over the supply voltage range andthe temperature range. When using a crystal to generate the system clock, this is rarelya problem, but for a resonator the system clock may differ more than 2% depending ofthe resonators tolerance. The second source for the error is more controllable. The baudrate generator can not always do an exact division of the system frequency to get thebaud rate wanted. In this case an UBRR value that gives an acceptable low error can beused if possible.

Table 61. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode(U2X = 0)

D# (Data+Parity Bit) Rslow (%) Rfast(%)

Max Total Error (%)

Recommended Max Receiver Error (%)

5 93.20 106.67 +6.67/-6.8 ± 3.0

6 94.12 105.79 +5.79/-5.88 ± 2.5

7 94.81 105.11 +5.11/-5.19 ± 2.0

8 95.36 104.58 +4.58/-4.54 ± 2.0

9 95.81 104.14 +4.14/-4.19 ± 1.5

10 96.17 103.78 +3.78/-3.83 ± 1.5

Table 62. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode(U2X = 1)

D# (Data+Parity Bit) Rslow (%) Rfast (%)

Max Total Error (%)

Recommended Max Receiver Error (%)

5 94.12 105.66 +5.66/-5.88 ± 2.5

6 94.92 104.92 +4.92/-5.08 ± 2.0

7 95.52 104.35 +4.35/-4.48 ± 1.5

8 96.00 103.90 +3.90/-4.00 ± 1.5

9 96.39 103.53 +3.53/-3.61 ± 1.5

10 96.70 103.23 +3.23/-3.30 ± 1.0

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Multi-processor Communication Mode

Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a fil-tering function of incoming frames received by the USART Receiver. Frames that do notcontain address information will be ignored and not put into the receive buffer. Thiseffectively reduces the number of incoming frames that has to be handled by the CPU,in a system with multiple MCUs that communicate via the same serial bus. The Trans-mitter is unaffected by the MPCM setting, but has to be used differently when it is a partof a system utilizing the Multi-processor Communication mode.

If the receiver is set up to receive frames that contain 5 to 8 data bits, then the first stopbit indicates if the frame contains data or address information. If the receiver is set up forframes with nine data bits, then the ninth bit (RXB8) is used for identifying address anddata frames. When the frame type bit (the first stop or the ninth bit) is one, the framecontains an address. When the frame type bit is zero the frame is a data frame.

The Multi-processor Communication mode enables several slave MCUs to receive datafrom a master MCU. This is done by first decoding an address frame to find out whichMCU has been addressed. If a particular Slave MCU has been addressed, it will receivethe following data frames as normal, while the other slave MCUs will ignore the receivedframes until another address frame is received.

Using MPCM For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZ =7). The ninth bit (TXB8) must be set when an address frame (TXB8 = 1) or cleared whena data frame (TXB = 0) is being transmitted. The slave MCUs must in this case be set touse a 9-bit character frame format.

The following procedure should be used to exchange data in Multi-processor Communi-cation mode:

1. All slave MCUs are in Multi-processor Communication mode (MPCM in UCSRA is set).

2. The Master MCU sends an address frame, and all slaves receive and read this frame. In the Slave MCUs, the RXC flag in UCSRA will be set as normal.

3. Each Slave MCU reads the UDR Register and determines if it has been selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next address byte and keeps the MPCM setting.

4. The addressed MCU will receive all data frames until a new address frame is received. The other slave MCUs, which still have the MPCM bit set, will ignore the data frames.

5. When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCM bit and waits for a new address frame from Master. The process then repeats from 2.

Using any of the 5- to 8-bit character frame formats is possible, but impractical since thereceiver must change between using n and n+1 character frame formats. This makesfull-duplex operation difficult since the transmitter and receiver uses the same charactersize setting. If 5- to 8-bit character frames are used, the transmitter must be set to usetwo stop bit (USBS = 1) since the first stop bit is used for indicating the frame type.

Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit.The MPCM bit shares the same I/O location as the TXC flag and this might accidentallybe cleared when using SBI or CBI instructions.

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Accessing UBRRH/ UCSRC Registers

The UBRRH Register shares the same I/O location as the UCSRC Register. Thereforesome special consideration must be taken when accessing this I/O location.

Write Access When doing a write access of this I/O location, the high bit of the value written, theUSART Register Select (URSEL) bit, controls which one of the two registers that will bewritten. If URSEL is zero during a write operation, the UBRRH value will be updated. IfURSEL is one, the UCSRC setting will be updated.

The following code examples show how to access the two registers.


As the code examples illustrate, write accesses of the two registers are relatively unaf-fected of the sharing of I/O location.


...

; Set UBRRH to 2

ldi r16,0x02

out UBRRH,r16

...

; Set the USBS and the UCSZ1 bit to one, and

; the remaining bits to zero.

ldi r16,(1<<URSEL)|(1<<USBS)|(1<<UCSZ1)

out UCSRC,r16

...

C Code Example(1)

...

/* Set UBRRH to 2 */

UBRRH = 0x02;

...

/* Set the USBS and the UCSZ1 bit to one, and */

/* the remaining bits to zero. */

UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1);

...

1552466E–AVR–10/02

Read Access Doing a read access to the UBRRH or the UCSRC Register is a more complex opera-tion. However, in most applications, it is rarely necessary to read any of these registers.

The read access is controlled by a timed sequence. Reading the I/O location oncereturns the UBRRH Register contents. If the register location was read in previous sys-tem clock cycle, reading the register in the current clock cycle will return the UCSRCcontents. Note that the timed sequence for reading the UCSRC is an atomic operation.Interrupts must therefore be controlled (for example by disabling interrupts globally) dur-ing the read operation.

The following code example shows how to read the UCSRC Register contents.


The assembly code example returns the UCSRC value in r16.

Reading the UBRRH contents is not an atomic operation and therefore it can be read asan ordinary register, as long as the previous instruction did not access the registerlocation.

USART Register Description

USART I/O Data Register – UDR

The USART Transmit Data Buffer Register and USART Receive Data Buffer Registersshare the same I/O address referred to as USART Data Register or UDR. The TransmitData Buffer Register (TXB) will be the destination for data written to the UDR registerlocation. Reading the UDR Register location will return the contents of the receive databuffer register (RXB).

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitterand set to zero by the Receiver.


USART_ReadUCSRC:

; Read UCSRC

in r16,UBRRH

in r16,UCSRC

ret

C Code Example(1)

unsigned char USART_ReadUCSRC( void )

unsigned char ucsrc;

/* Read UCSRC */

ucsrc = UBRRH;

ucsrc = UCSRC;

return ucsrc;

Bit 7 6 5 4 3 2 1 0

RXB[7:0] UDR (Read)

TXB[7:0] UDR (Write)



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The transmit buffer can only be written when the UDRE flag in the UCSRA Register isset. Data written to UDR when the UDRE flag is not set, will be ignored by the USARTTransmitter. When data is written to the transmit buffer, and the Transmitter is enabled,the Transmitter will load the data into the transmit Shift Register when the Shift Registeris empty. Then the data will be serially transmitted on the TxD pin.

The receive buffer consists of a two level FIFO. The FIFO will change its state wheneverthe receive buffer is accessed. Due to this behavior of the receive buffer, do not useread modify write instructions (SBI and CBI) on this location. Be careful when using bittest instructions (SBIC and SBIS), since these also will change the state of the FIFO.

USART Control and Status Register A – UCSRA

• Bit 7 – RXC: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when thereceive buffer is empty (i.e., does not contain any unread data). If the receiver is dis-abled, the receive buffer will be flushed and consequently the RXC bit will become zero.The RXC flag can be used to generate a Receive Complete interrupt (see description ofthe RXCIE bit).

• Bit 6 – TXC: USART Transmit Complete

This flag bit is set when the entire frame in the transmit Shift Register has been shiftedout and there are no new data currently present in the transmit buffer (UDR). The TXCflag bit is automatically cleared when a transmit complete interrupt is executed, or it canbe cleared by writing a one to its bit location. The TXC flag can generate a TransmitComplete interrupt (see description of the TXCIE bit).

• Bit 5 – UDRE: USART Data Register Empty

The UDRE flag indicates if the transmit buffer (UDR) is ready to receive new data. IfUDRE is one, the buffer is empty, and therefore ready to be written. The UDRE flag cangenerate a Data Register empty Interrupt (see description of the UDRIE bit).

UDRE is set after a reset to indicate that the transmitter is ready.

• Bit 4 – FE: Frame Error

This bit is set if the next character in the receive buffer had a Frame Error whenreceived. i.e., when the first stop bit of the next character in the receive buffer is zero.This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stopbit of received data is one. Always set this bit to zero when writing to UCSRA.

• Bit 3 – DOR: Data OverRun

This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when thereceive buffer is full (two characters), it is a new character waiting in the receive ShiftRegister, and a new start bit is detected. This bit is valid until the receive buffer (UDR) isread. Always set this bit to zero when writing to UCSRA.

Bit 7 6 5 4 3 2 1 0

RXC TXC UDRE FE DOR PE U2X MPCM UCSRA

Read/Write R R/W R R R R R/W R/W


1572466E–AVR–10/02

• Bit 2 – PE: Parity Error

This bit is set if the next character in the receive buffer had a Parity Error when receivedand the parity checking was enabled at that point (UPM1 = 1). This bit is valid until thereceive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.

• Bit 1 – U2X: Double the USART Transmission Speed

This bit only has effect for the asynchronous operation. Write this bit to zero when usingsynchronous operation.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effec-tively doubling the transfer rate for asynchronous communication.

• Bit 0 – MPCM: Multi-processor Communication Mode

This bit enables the Multi-processor Communication mode. When the MPCM bit is writ-ten to one, all the incoming frames received by the USART receiver that do not containaddress information will be ignored. The transmitter is unaffected by the MPCM setting.For more detailed information see “Multi-processor Communication Mode” on page 154.

USART Control and Status Register B – UCSRB

• Bit 7 – RXCIE: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXC flag. A USART Receive CompleteInterrupt will be generated only if the RXCIE bit is written to one, the Global InterruptFlag in SREG is written to one and the RXC bit in UCSRA is set.

• Bit 6 – TXCIE: TX Complete Interrupt Enable

Writing this bit to one enables interrupt on the TXC flag. A USART Transmit CompleteInterrupt will be generated only if the TXCIE bit is written to one, the Global InterruptFlag in SREG is written to one and the TXC bit in UCSRA is set.

• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable

Writing this bit to one enables interrupt on the UDRE flag. A Data Register Empty Inter-rupt will be generated only if the UDRIE bit is written to one, the Global Interrupt Flag inSREG is written to one and the UDRE bit in UCSRA is set.

• Bit 4 – RXEN: Receiver Enable

Writing this bit to one enables the USART Receiver. The Receiver will override normalport operation for the RxD pin when enabled. Disabling the Receiver will flush thereceive buffer invalidating the FE, DOR, and PE flags.

• Bit 3 – TXEN: Transmitter Enable

Writing this bit to one enables the USART Transmitter. The Transmitter will override nor-mal port operation for the TxD pin when enabled. The disabling of the Transmitter(writing TXEN to zero) will not become effective until ongoing and pending transmis-sions are completed, i.e., when the transmit Shift Register and transmit Buffer Register

Bit 7 6 5 4 3 2 1 0

RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 UCSRB

Read/Write R/W R/W R/W R/W R/W R/W R R/W


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do not contain data to be transmitted. When disabled, the transmitter will no longer over-ride the TxD port.

• Bit 2 – UCSZ2: Character Size

The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits(Character Size) in a frame the receiver and transmitter use.

• Bit 1 – RXB8: Receive Data Bit 8

RXB8 is the ninth data bit of the received character when operating with serial frameswith nine data bits. Must be read before reading the low bits from UDR.

• Bit 0 – TXB8: Transmit Data Bit 8

TXB8 is the ninth data bit in the character to be transmitted when operating with serialframes with nine data bits. Must be written before writing the low bits to UDR.

USART Control and Status Register C – UCSRC

The UCSRC Register shares the same I/O location as the UBRRH Register. See the“Accessing UBRRH/ UCSRC Registers” on page 155 section which describes how toaccess this register.

• Bit 7 – URSEL: Register Select

This bit selects between accessing the UCSRC or the UBRRH Register. It is read asone when reading UCSRC. The URSEL must be one when writing the UCSRC.

• Bit 6 – UMSEL: USART Mode Select

This bit selects between Asynchronous and Synchronous mode of operation.

Bit 7 6 5 4 3 2 1 0

URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL UCSRC



Table 63. UMSEL Bit Settings

UMSEL Mode

0 Asynchronous Operation

1 Synchronous Operation

1592466E–AVR–10/02

• Bit 5:4 – UPM1:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the transmit-ter will automatically generate and send the parity of the transmitted data bits withineach frame. The Receiver will generate a parity value for the incoming data and com-pare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSRA will be set.

• Bit 3 – USBS: Stop Bit Select

This bit selects the number of Stop Bits to be inserted by the Transmitter. The Receiverignores this setting.

• Bit 2:1 – UCSZ1:0: Character Size

The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits(Character Size) in a frame the Receiver and Transmitter use.

Table 64. UPM Bits Settings

UPM1 UPM0 Parity Mode

0 0 Disabled

0 1 Reserved

1 0 Enabled, Even Parity

1 1 Enabled, Odd Parity

Table 65. USBS Bit Settings

USBS Stop Bit(s)

0 1-bit

1 2-bit

Table 66. UCSZ Bits Settings

UCSZ2 UCSZ1 UCSZ0 Character Size

0 0 0 5-bit

0 0 1 6-bit

0 1 0 7-bit

0 1 1 8-bit

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Reserved

1 1 1 9-bit

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• Bit 0 – UCPOL: Clock Polarity

This bit is used for Synchronous mode only. Write this bit to zero when Asynchronousmode is used. The UCPOL bit sets the relationship between data output change anddata input sample, and the synchronous clock (XCK).

USART Baud Rate Registers – UBRRL and UBRRH

The UBRRH Register shares the same I/O location as the UCSRC Register. See the“Accessing UBRRH/ UCSRC Registers” on page 155 section which describes how toaccess this register.

• Bit 15 – URSEL: Register Select

This bit selects between accessing the UBRRH or the UCSRC Register. It is read aszero when reading UBRRH. The URSEL must be zero when writing the UBRRH.

• Bit 14:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bitmust be written to zero when UBRRH is written.

• Bit 11:0 – UBRR11:0: USART Baud Rate Register

This is a 12-bit register which contains the USART baud rate. The UBRRH contains thefour most significant bits, and the UBRRL contains the 8 least significant bits of theUSART baud rate. Ongoing transmissions by the transmitter and receiver will be cor-rupted if the baud rate is changed. Writing UBRRL will trigger an immediate update ofthe baud rate prescaler.

Table 67. UCPOL Bit Settings

UCPOLTransmitted Data Changed (Output of TxD Pin)

Received Data Sampled (Input on RxD Pin)

0 Rising XCK Edge Falling XCK Edge

1 Falling XCK Edge Rising XCK Edge

Bit 15 14 13 12 11 10 9 8

URSEL – – – UBRR[11:8] UBRRH

UBRR[7:0] UBRRL

7 6 5 4 3 2 1 0

Read/Write R/W R R R R/W R/W R/W R/W



0 0 0 0 0 0 0 0

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Examples of Baud Rate Setting

For standard crystal and resonator frequencies, the most commonly used baud rates forasynchronous operation can be generated by using the UBRR settings in Table 68.UBRR values which yield an actual baud rate differing less than 0.5% from the targetbaud rate, are bold in the table. Higher error ratings are acceptable, but the receiver willhave less noise resistance when the error ratings are high, especially for large serialframes (see “Asynchronous Operational Range” on page 152). The error values are cal-culated using the following equation:

Error[%]BaudRateClosest Match

BaudRate-------------------------------------------------------- 1–

100%•=

Table 68. Examples of UBRR Settings for Commonly Used Oscillator Frequencies

Baud Rate (bps)

fosc = 1.0000 MHz fosc = 1.8432 MHz fosc = 2.0000 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2%

4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2%

9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2%

14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1%

19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2%

28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5%

38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0%

57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5%

76.8k – – 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5%

115.2k – – 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5%

230.4k – – – – – – 0 0.0% – – – –

250k – – – – – – – – – – 0 0.0%

Max (1) 62.5 kbps 125 kbps 115.2 kbps 230.4 kbps 125 kbps 250 kbps

1. UBRR = 0, Error = 0.0%

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Table 69. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)

Baud Rate (bps)


U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1


2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0%

4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0%

9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0%

14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0%

19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0%

28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0%

38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0%

57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0%

76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0%

115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0%

230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0%

250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8%

0.5M – – 0 -7.8% – – 0 0.0% 0 -7.8% 1 -7.8%

1M – – – – – – – – – – 0 -7.8%

Max (1) 230.4 kbps 460.8 kbps 250 kbps 0.5 Mbps 460.8 kbps 921.6 kbps

1. UBRR = 0, Error = 0.0%

1632466E–AVR–10/02


Baud Rate (bps)


U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1


2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0%

4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0%

9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0%

14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0%

19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0%

28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0%

38.4k 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0%

57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0%

76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0%

115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0%

230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0%

250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3%

0.5M 0 0.0% 1 0.0% – – 2 -7.8% 1 -7.8% 3 -7.8%

1M – – 0 0.0% – – – – 0 -7.8% 1 -7.8%

Max (1) 0.5 Mbps 1 Mbps 691.2 kbps 1.3824 Mbps 921.6 kbps 1.8432 Mbps

1. UBRR = 0, Error = 0.0%

164 ATmega16(L) 2466E–AVR–10/02

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Baud Rate (bps)


U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1


2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0%

4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0%

9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2%

14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2%

19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2%

28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2%

38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2%

57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9%

76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 -1.4%

115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4%

230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4%

250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0%

0.5M 1 0.0% 3 0.0% – – 4 -7.8% – – 4 0.0%

1M 0 0.0% 1 0.0% – – – – – – – –

Max (1) 1 Mbps 2 Mbps 1.152 Mbps 2.304 Mbps 1.25 Mbps 2.5 Mbps

1. UBRR = 0, Error = 0.0%

1652466E–AVR–10/02

Two-wire Serial Interface

Features • Simple Yet Powerful and Flexible Communication Interface, Only Two Bus Lines Needed• Both Master and Slave Operation Supported• Device Can Operate as Transmitter or Receiver• 7-bit Address Space allows up to 128 Different Slave Addresses• Multi-master Arbitration Support• Up to 400 kHz Data Transfer Speed• Slew-rate Limited Output Drivers• Noise Suppression Circuitry Rejects Spikes on Bus Lines• Fully Programmable Slave Address with General Call Support• Address Recognition causes Wake-up when AVR is in Sleep Mode

Two-wire Serial Interface Bus Definition

The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applica-tions. The TWI protocol allows the systems designer to interconnect up to 128 differentdevices using only two bi-directional bus lines, one for clock (SCL) and one for data(SDA). The only external hardware needed to implement the bus is a single pull-upresistor for each of the TWI bus lines. All devices connected to the bus have individualaddresses, and mechanisms for resolving bus contention are inherent in the TWIprotocol.

Figure 76. TWI Bus Interconnection

TWI Terminology The following definitions are frequently encountered in this section.

Device 1 Device 2 Device 3 Device n

SDA

SCL

........ R1 R2

VCC

Table 72. TWI Terminology

Term Description

Master The device that initiates and terminates a transmission. The master also generates the SCL clock.

Slave The device addressed by a master.

Transmitter The device placing data on the bus.

Receiver The device reading data from the bus.

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Electrical Interconnection As depicted in Figure 76, both bus lines are connected to the positive supply voltagethrough pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain oropen-collector. This implements a wired-AND function which is essential to the opera-tion of the interface. A low level on a TWI bus line is generated when one or more TWIdevices output a zero. A high level is output when all TWI devices tri-state their outputs,allowing the pull-up resistors to pull the line high. Note that all AVR devices connected tothe TWI bus must be powered in order to allow any bus operation.

The number of devices that can be connected to the bus is only limited by the buscapacitance limit of 400 pF and the 7-bit slave address space. A detailed specification ofthe electrical characteristics of the TWI is given in “Two-wire Serial Interface Character-istics” on page 288. Two different sets of specifications are presented there, onerelevant for bus speeds below 100 kHz, and one valid for bus speeds up to 400 kHz.

Data Transfer and Frame Format

Transferring Bits Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line.The level of the data line must be stable when the clock line is high. The only exceptionto this rule is for generating start and stop conditions.

Figure 77. Data Validity

START and STOP Conditions The master initiates and terminates a data transmission. The transmission is initiatedwhen the master issues a START condition on the bus, and it is terminated when themaster issues a STOP condition. Between a START and a STOP condition, the bus isconsidered busy, and no other master should try to seize control of the bus. A specialcase occurs when a new START condition is issued between a START and STOP con-dition. This is referred to as a REPEATED START condition, and is used when themaster wishes to initiate a new transfer without releasing control of the bus. After aREPEATED START, the bus is considered busy until the next STOP. This is identical tothe START behavior, and therefore START is used to describe both START andREPEATED START for the remainder of this datasheet, unless otherwise noted. Asdepicted below, START and STOP conditions are signalled by changing the level of theSDA line when the SCL line is high.

SDA

SCL

Data Stable Data Stable

Data Change

1672466E–AVR–10/02

Figure 78. START, REPEATED START, and STOP Conditions

Address Packet Format All address packets transmitted on the TWI bus are nine bits long, consisting of sevenaddress bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITEbit is set, a read operation is to be performed, otherwise a write operation should be per-formed. When a slave recognizes that it is being addressed, it should acknowledge bypulling SDA low in the ninth SCL (ACK) cycle. If the addressed slave is busy, or forsome other reason can not service the master’s request, the SDA line should be lefthigh in the ACK clock cycle. The master can then transmit a STOP condition, or aREPEATED START condition to initiate a new transmission. An address packet consist-ing of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W,respectively.

The MSB of the address byte is transmitted first. Slave addresses can freely be allo-cated by the designer, but the address 0000 000 is reserved for a general call.

When a general call is issued, all slaves should respond by pulling the SDA line low inthe ACK cycle. A general call is used when a master wishes to transmit the same mes-sage to several slaves in the system. When the general call address followed by a Writebit is transmitted on the bus, all slaves set up to acknowledge the general call will pullthe SDA line low in the ack cycle. The following data packets will then be received by allthe slaves that acknowledged the general call. Note that transmitting the general calladdress followed by a Read bit is meaningless, as this would cause contention if severalslaves started transmitting different data.

All addresses of the format 1111 xxx should be reserved for future purposes.

Figure 79. Address Packet Format

Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one databyte and an acknowledge bit. During a data transfer, the master generates the clock andthe START and STOP conditions, while the receiver is responsible for acknowledgingthe reception. An Acknowledge (ACK) is signalled by the receiver pulling the SDA linelow during the ninth SCL cycle. If the receiver leaves the SDA line high, a NACK is sig-nalled. When the receiver has received the last byte, or for some reason cannot receive

SDA

SCL

START STOPREPEATED STARTSTOP START

SDA

SCL

START

1 2 7 8 9

Addr MSB Addr LSB R/W ACK

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any more bytes, it should inform the transmitter by sending a NACK after the final byte.The MSB of the data byte is transmitted first.

Figure 80. Data Packet Format

Combining Address and Data Packets into a Transmission

A transmission basically consists of a START condition, a SLA+R/W, one or more datapackets and a STOP condition. An empty message, consisting of a START followed bya STOP condition, is illegal. Note that the wired-ANDing of the SCL line can be used toimplement handshaking between the master and the slave. The slave can extend theSCL low period by pulling the SCL line low. This is useful if the clock speed set up by themaster is too fast for the slave, or the slave needs extra time for processing between thedata transmissions. The slave extending the SCL low period will not affect the SCL highperiod, which is determined by the master. As a consequence, the slave can reduce theTWI data transfer speed by prolonging the SCL duty cycle.

Figure 81 shows a typical data transmission. Note that several data bytes can be trans-mitted between the SLA+R/W and the STOP condition, depending on the softwareprotocol implemented by the application software.

Figure 81. Typical Data Transmission

Multi-master Bus Systems, Arbitration and Synchronization

The TWI protocol allows bus systems with several masters. Special concerns havebeen taken in order to ensure that transmissions will proceed as normal, even if two ormore masters initiate a transmission at the same time. Two problems arise in multi-mas-ter systems:

• An algorithm must be implemented allowing only one of the masters to complete the transmission. All other masters should cease transmission when they discover that they have lost the selection process. This selection process is called arbitration. When a contending master discovers that it has lost the arbitration process, it should immediately switch to slave mode to check whether it is being addressed by the winning master. The fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i.e., the data being transferred on the bus must not be corrupted.

1 2 7 8 9

Data MSB Data LSB ACK

AggregateSDA

SDA fromTransmitter

SDA fromreceiverR

SCL fromMaster

SLA+R/W Data ByteSTOP, REPEATED

START or NextData Byte

1 2 7 8 9

Data Byte

Data MSB Data LSB ACK

SDA

SCL

START

1 2 7 8 9

Addr MSB Addr LSB R/W ACK

SLA+R/W STOP

1692466E–AVR–10/02

• Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration process.

The wired-ANDing of the bus lines is used to solve both these problems. The serialclocks from all masters will be wired-ANDed, yielding a combined clock with a highperiod equal to the one from the master with the shortest high period. The low period ofthe combined clock is equal to the low period of the master with the longest low period.Note that all masters listen to the SCL line, effectively starting to count their SCL highand low time-out periods when the combined SCL line goes high or low, respectively.

Figure 82. SCL Synchronization between Multiple Masters

Arbitration is carried out by all masters continuously monitoring the SDA line after out-putting data. If the value read from the SDA line does not match the value the masterhad output, it has lost the arbitration. Note that a master can only lose arbitration when itoutputs a high SDA value while another master outputs a low value. The losing mastershould immediately go to slave mode, checking if it is being addressed by the winningmaster. The SDA line should be left high, but losing masters are allowed to generate aclock signal until the end of the current data or address packet. Arbitration will continueuntil only one master remains, and this may take many bits. If several masters are tryingto address the same slave, arbitration will continue into the data packet.

TA low TA high

SCL fromMaster A

SCL fromMaster B

SCL busLine

TBlow TBhigh

Masters StartCounting Low Period

Masters StartCounting High Period

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Figure 83. Arbitration between Two Masters

Note that arbitration is not allowed between:

• A REPEATED START condition and a data bit

• A STOP condition and a data bit

• A REPEATED START and a STOP condition

It is the user software’s responsibility to ensure that these illegal arbitration conditionsnever occur. This implies that in multi-master systems, all data transfers must use thesame composition of SLA+R/W and data packets. In other words: All transmissionsmust contain the same number of data packets, otherwise the result of the arbitration isundefined.

SDA fromMaster A

SDA fromMaster B

SDA Line

SynchronizedSCL Line

START Master A LosesArbitration, SDAA SDA

1712466E–AVR–10/02

Overview of the TWI Module

The TWI module is comprised of several submodules, as shown in Figure 84. All regis-ters drawn in a thick line are accessible through the AVR data bus.

Figure 84. Overview of the TWI Module

SCL and SDA Pins These pins interface the AVR TWI with the rest of the MCU system. The output driverscontain a slew-rate limiter in order to conform to the TWI specification. The input stagescontain a spike suppression unit removing spikes shorter than 50 ns. Note that the inter-nal pullups in the AVR pads can be enabled by setting the PORT bits corresponding tothe SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can insome systems eliminate the need for external ones.

Bit Rate Generator Unit This unit controls the period of SCL when operating in a Master mode. The SCL periodis controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits inthe TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Pres-caler settings, but the CPU clock frequency in the slave must be at least 16 times higherthan the SCL frequency. Note that slaves may prolong the SCL low period, therebyreducing the average TWI bus clock period. The SCL frequency is generated accordingto the following equation:

• TWBR = Value of the TWI Bit Rate Register

• TWPS = Value of the prescaler bits in the TWI Status RegisterNote: TWBR should be 10 or higher if the TWI operates in Master mode. If TWBR is lower than

10, the master may produce an incorrect output on SDA and SCL for the reminder of thebyte. The problem occurs when operating the TWI in Master mode, sending Start + SLA+ R/W to a slave (a slave does not need to be connected to the bus for the condition tohappen).

TWI Unit

Address Register(TWAR)

Address Match Unit

Address Comparator

Control Unit

Control Register(TWCR)

Status Register(TWSR)

State Machine andStatus control

SCL

Slew-rateControl

SpikeFilter

SDA

Slew-rateControl

SpikeFilter

Bit Rate Generator

Bit Rate Register(TWBR)

Prescaler

Bus Interface Unit

START / STOPControl

Arbitration detection Ack

Spike Suppression

Address/Data ShiftRegister (TWDR)

SCL frequency CPU Clock frequency

16 2(TWBR) 4TWPS⋅+

-----------------------------------------------------------=

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Bus Interface Unit This unit contains the Data and Address Shift Register (TWDR), a START/STOP Con-troller and Arbitration detection hardware. The TWDR contains the address or databytes to be transmitted, or the address or data bytes received. In addition to the 8-bitTWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to betransmitted or received. This (N)ACK Register is not directly accessible by the applica-tion software. However, when receiving, it can be set or cleared by manipulating theTWI Control Register (TWCR). When in Transmitter mode, the value of the received(N)ACK bit can be determined by the value in the TWSR.

The START/STOP Controller is responsible for generation and detection of START,REPEATED START, and STOP conditions. The START/STOP controller is able todetect START and STOP conditions even when the AVR MCU is in one of the sleepmodes, enabling the MCU to wake up if addressed by a master.

If the TWI has initiated a transmission as master, the Arbitration Detection hardwarecontinuously monitors the transmission trying to determine if arbitration is in process. Ifthe TWI has lost an arbitration, the Control Unit is informed. Correct action can then betaken and appropriate status codes generated.

Address Match Unit The Address Match unit checks if received address bytes match the 7-bit address in theTWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE)bit in the TWAR is written to one, all incoming address bits will also be comparedagainst the General Call address. Upon an address match, the Control Unit is informed,allowing correct action to be taken. The TWI may or may not acknowledge its address,depending on settings in the TWCR. The Address Match unit is able to compareaddresses even when the AVR MCU is in sleep mode, enabling the MCU to wake up ifaddressed by a master.

Control Unit The Control unit monitors the TWI bus and generates responses corresponding to set-tings in the TWI Control Register (TWCR). When an event requiring the attention of theapplication occurs on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In thenext clock cycle, the TWI Status Register (TWSR) is updated with a status code identify-ing the event. The TWSR only contains relevant status information when the TWIinterrupt flag is asserted. At all other times, the TWSR contains a special status codeindicating that no relevant status information is available. As long as the TWINT flag isset, the SCL line is held low. This allows the application software to complete its tasksbefore allowing the TWI transmission to continue.

The TWINT flag is set in the following situations:

• After the TWI has transmitted a START/REPEATED START condition

• After the TWI has transmitted SLA+R/W

• After the TWI has transmitted an address byte

• After the TWI has lost arbitration

• After the TWI has been addressed by own slave address or general call

• After the TWI has received a data byte

• After a STOP or REPEATED START has been received while still addressed as a slave

• When a bus error has occurred due to an illegal START or STOP condition

1732466E–AVR–10/02

TWI register description

TWI Bit Rate Register – TWBR

• Bits 7..0 – TWI Bit Rate Register

TWBR selects the division factor for the bit rate generator. The bit rate generator is afrequency divider which generates the SCL clock frequency in the Master modes. See“Bit Rate Generator Unit” on page 172 for calculating bit rates.

TWI Control Register – TWCR

The TWCR is used to control the operation of the TWI. It is used to enable the TWI, toinitiate a master access by applying a START condition to the bus, to generate areceiver acknowledge, to generate a stop condition, and to control halting of the buswhile the data to be written to the bus are written to the TWDR. It also indicates a writecollision if data is attempted written to TWDR while the register is inaccessible.

• Bit 7 – TWINT: TWI Interrupt Flag

This bit is set by hardware when the TWI has finished its current job and expects appli-cation software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU willjump to the TWI Interrupt Vector. While the TWINT flag is set, the SCL low period isstretched. The TWINT flag must be cleared by software by writing a logic one to it. Notethat this flag is not automatically cleared by hardware when executing the interrupt rou-tine. Also note that clearing this flag starts the operation of the TWI, so all accesses tothe TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Regis-ter (TWDR) must be complete before clearing this flag.

• Bit 6 – TWEA: TWI Enable Acknowledge Bit

The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is writ-ten to one, the ACK pulse is generated on the TWI bus if the following conditions aremet:

1. The device’s own slave address has been received.

2. A general call has been received, while the TWGCE bit in the TWAR is set.

3. A data byte has been received in Master Receiver or Slave Receiver mode.

By writing the TWEA bit to zero, the device can be virtually disconnected from the Two-wire Serial Bus temporarily. Address recognition can then be resumed by writing theTWEA bit to one again.

• Bit 5 – TWSTA: TWI START Condition Bit

The application writes the TWSTA bit to one when it desires to become a master on theTwo-wire Serial Bus. The TWI hardware checks if the bus is available, and generates aSTART condition on the bus if it is free. However, if the bus is not free, the TWI waits

Bit 7 6 5 4 3 2 1 0

TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 TWBR



Bit 7 6 5 4 3 2 1 0

TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE TWCR

Read/Write R/W R/W R/W R/W R R/W R R/W


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until a STOP condition is detected, and then generates a new START condition to claimthe bus Master status. TWSTA is cleared by the TWI hardware when the START condi-tion has been transmitted.

• Bit 4 – TWSTO: TWI STOP Condition Bit

Writing the TWSTO bit to one in Master mode will generate a STOP condition on theTwo-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bitis cleared automatically. In slave mode, setting the TWSTO bit can be used to recoverfrom an error condition. This will not generate a STOP condition, but the TWI returns toa well-defined unaddressed slave mode and releases the SCL and SDA lines to a highimpedance state.

• Bit 3 – TWWC: TWI Write Collision Flag

The TWWC bit is set when attempting to write to the TWI Data Register – TWDR whenTWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high.

• Bit 2 – TWEN: TWI Enable Bit

The TWEN bit enables TWI operation and activates the TWI interface. When TWEN iswritten to one, the TWI takes control over the I/O pins connected to the SCL and SDApins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWIis switched off and all TWI transmissions are terminated, regardless of any ongoingoperation.

• Bit 1 – Res: Reserved Bit

This bit is a reserved bit and will always read as zero.

• Bit 0 – TWIE: TWI Interrupt Enable

When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request willbe activated for as long as the TWINT flag is high.

TWI Status Register – TWSR

• Bits 7..3 – TWS: TWI Status

These five bits reflect the status of the TWI logic and the Two-wire Serial Bus. The dif-ferent status codes are described later in this section. Note that the value read fromTWSR contains both the 5-bit status value and the 2-bit prescaler value. The applicationdesigner should mask the prescaler bits to zero when checking the Status bits. Thismakes status checking independent of prescaler setting. This approach is used in thisdatasheet, unless otherwise noted.


This bit is reserved and will always read as zero.

Bit 7 6 5 4 3 2 1 0

TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 TWSR

Read/Write R R R R R R R/W R/W


1752466E–AVR–10/02

• Bits 1..0 – TWPS: TWI Prescaler Bits

These bits can be read and written, and control the bit rate prescaler. See “Bit RateGenerator Unit” on page 172 for calculating bit rates.

TWI Data Register – TWDR

In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, theTWDR contains the last byte received. It is writable while the TWI is not in the process ofshifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware.Note that the data register cannot be initialized by the user before the first interruptoccurs. The data in TWDR remains stable as long as TWINT is set. While data is shiftedout, data on the bus is simultaneously shifted in. TWDR always contains the last bytepresent on the bus, except after a wake up from a sleep mode by the TWI interrupt. Inthis case, the contents of TWDR is undefined. In the case of a lost bus arbitration, nodata is lost in the transition from Master to Slave. Handling of the ACK bit is controlledautomatically by the TWI logic, the CPU cannot access the ACK bit directly.

• Bits 7..0 – TWD: TWI Data Register

These eight bits contin the next data byte to be transmitted, or the latest data bytereceived on the Two-wire Serial Bus.

TWI (Slave) Address Register – TWAR

The TWAR should be loaded with the 7-bit slave address (in the seven most significantbits of TWAR) to which the TWI will respond when programmed as a slave transmitter orreceiver. In multimaster systems, TWAR must be set in masters which can beaddressed as slaves by other masters.

The LSB of TWAR is used to enable recognition of the general call address ($00). Thereis an associated address comparator that looks for the slave address (or general calladdress if enabled) in the received serial address. If a match is found, an interruptrequest is generated.

• Bits 7..1 – TWA: TWI (Slave) Address Register

These seven bits constitute the slave address of the TWI unit.

• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit

If set, this bit enables the recognition of a General Call given over the Two-wire SerialBus.

Bit 7 6 5 4 3 2 1 0

TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 TWDR



Bit 7 6 5 4 3 2 1 0

TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE TWAR



176 ATmega16(L) 2466E–AVR–10/02

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Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all busevents, like reception of a byte or transmission of a START condition. Because the TWIis interrupt-based, the application software is free to carry on other operations during aTWI byte transfer. Note that the TWI Interrupt Enable (TWIE) bit in TWCR together withthe Global Interrupt Enable bit in SREG allow the application to decide whether or notassertion of the TWINT flag should generate an interrupt request. If the TWIE bit iscleared, the application must poll the TWINT flag in order to detect actions on the TWIbus.

When the TWINT flag is asserted, the TWI has finished an operation and awaits applica-tion response. In this case, the TWI Status Register (TWSR) contains a value indicatingthe current state of the TWI bus. The application software can then decide how the TWIshould behave in the next TWI bus cycle by manipulating the TWCR and TWDRRegisters.

Figure 85 is a simple example of how the application can interface to the TWI hardware.In this example, a master wishes to transmit a single data byte to a slave. This descrip-tion is quite abstract, a more detailed explanation follows later in this section. A simplecode example implementing the desired behaviour is also presented.

Figure 85. Interfacing the Application to the TWI in a Typical Transmission

1. The first step in a TWI transmission is to transmit a START condition. This is done by writing a specific value into TWCR, instructing the TWI hardware to transmit a START condition. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the START condition.

2. When the START condition has been transmitted, the TWINT flag in TWCR is set, and TWSR is updated with a status code indicating that the START condition has successfully been sent.

3. The application software should now examine the value of TWSR, to make sure that the START condition was successfully transmitted. If TWSR indicates other-wise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load SLA+W into TWDR. Remember that TWDR is used both for address and data. After TWDR has been loaded with the desired SLA+W, a specific value

START SLA+W A Data A STOP

1. Applicationwrites to TWCR to

initiatetransmission of

START

2. TWINT set.Status code indicatesSTART condition sent

4. TWINT set.Status code indicates

SLA+W sent, ACKreceived

6. TWINT set.Status code indicates

data sent, ACK received

3. Check TWSR to see if START wassent.

Application loads SLA+W into TWDR,and loads appropriate control signals

into TWCR, making sure that TWINT iswritten to one

5. Check TWSR to see if SLA+W wassent and ACK received.

Application loads data into TWDR, andloads appropriate control signals intoTWCR, making sure that TWINT is

written to one

7. Check TWSR to see if data was sentand ACK received.

Application loads appropriate controlsignals to send STOP into TWCR,

making sure that TWINT is written to one

TWI bus

IndicatesTWINT set

ApplicationAction

TWIHardware

Action

1772466E–AVR–10/02

must be written to TWCR, instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the address packet.

4. When the address packet has been transmitted, the TWINT flag in TWCR is set, and TWSR is updated with a status code indicating that the address packet has successfully been sent. The status code will also reflect whether a slave acknowledged the packet or not.

5. The application software should now examine the value of TWSR, to make sure that the address packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load a data packet into TWDR. Subsequently, a specific value must be written to TWCR, instructing the TWI hardware to transmit the data packet present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any opera-tion as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the data packet.

6. When the data packet has been transmitted, the TWINT flag in TWCR is set, and TWSR is updated with a status code indicating that the data packet has success-fully been sent. The status code will also reflect whether a slave acknowledged the packet or not.

7. The application software should now examine the value of TWSR, to make sure that the data packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must write a specific value to TWCR, instructing the TWI hardware to transmit a STOP condition. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the appli-cation has cleared TWINT, the TWI will initiate transmission of the STOP condition. Note that TWINT is NOT set after a STOP condition has been sent.

Even though this example is simple, it shows the principles involved in all TWI transmis-sions. These can be summarized as follows:

• When the TWI has finished an operation and expects application response, the TWINT flag is set. The SCL line is pulled low until TWINT is cleared.

• When the TWINT flag is set, the user must update all TWI registers with the value relevant for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be transmitted in the next bus cycle.

• After all TWI register updates and other pending application software tasks have been completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a one to TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting.

In the following an assembly and C implementation of the example is given. Note thatthe code below assumes that several definitions have been made, for example by usinginclude-files.

178 ATmega16(L) 2466E–AVR–10/02

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Assembly code example C example Comments

1 ldi r16, (1<<TWINT)|(1<<TWSTA)|

(1<<TWEN)

out TWCR, r16

TWCR = (1<<TWINT)|(1<<TWSTA)|

(1<<TWEN)Send START condition

2 wait1:

in r16,TWCR

sbrs r16,TWINT

rjmp wait1

while (!(TWCR & (1<<TWINT)))

;Wait for TWINT flag set. This indicates that the START condition has been transmitted

3 in r16,TWSR

andi r16, 0xF8

cpi r16, START

brne ERROR

if ((TWSR & 0xF8) != START)

ERROR();Check value of TWI Status Register. Mask prescaler bits. If status different from START go to ERROR

ldi r16, SLA_W

out TWDR, r16

ldi r16, (1<<TWINT) | (1<<TWEN)

out TWCR, r16

TWDR = SLA_W;

TWCR = (1<<TWINT) | (1<<TWEN);Load SLA_W into TWDR Register. Clear TWINT bit in TWCR to start transmission of address

4 wait2:

in r16,TWCR

sbrs r16,TWINT

rjmp wait2


;Wait for TWINT flag set. This indicates that the SLA+W has been transmitted, and ACK/NACK has been received.

5 in r16,TWSR

andi r16, 0xF8

cpi r16, MT_SLA_ACK

brne ERROR

if ((TWSR & 0xF8) != MT_SLA_ACK)

ERROR();Check value of TWI Status Register. Mask prescaler bits. If status different from MT_SLA_ACK go to ERROR

ldi r16, DATA

out TWDR, r16

ldi r16, (1<<TWINT) | (1<<TWEN)

out TWCR, r16

TWDR = DATA;

TWCR = (1<<TWINT) | (1<<TWEN);Load DATA into TWDR Register. Clear TWINT bit in TWCR to start transmission of data

6 wait3:

in r16,TWCR

sbrs r16,TWINT

rjmp wait3


;Wait for TWINT flag set. This indicates that the DATA has been transmitted, and ACK/NACK has been received.

7 in r16,TWSR

andi r16, 0xF8

cpi r16, MT_DATA_ACK

brne ERROR

if ((TWSR & 0xF8) != MT_DATA_ACK)

ERROR();Check value of TWI Status Register. Mask prescaler bits. If status different from MT_DATA_ACK go to ERROR

ldi r16, (1<<TWINT)|(1<<TWEN)|

(1<<TWSTO)

out TWCR, r16

TWCR = (1<<TWINT)|(1<<TWEN)|

(1<<TWSTO);Transmit STOP condition

1792466E–AVR–10/02

Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter(MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Severalof these modes can be used in the same application. As an example, the TWI can useMT mode to write data into a TWI EEPROM, MR mode to read the data back from theEEPROM. If other masters are present in the system, some of these might transmit datato the TWI, and then SR mode would be used. It is the application software that decideswhich modes are legal.

The following sections describe each of these modes. Possible status codes aredescribed along with figures detailing data transmission in each of the modes. These fig-ures contain the following abbreviations:

S: START condition

Rs: REPEATED START condition

R: Read bit (high level at SDA)

W: Write bit (low level at SDA)

A: Acknowledge bit (low level at SDA)

A: Not acknowledge bit (high level at SDA)

Data: 8-bit data byte

P: STOP condition

SLA: Slave Address

In Figure 87 to Figure 93, circles are used to indicate that the TWINT flag is set. Thenumbers in the circles show the status code held in TWSR, with the prescaler bitsmasked to zero. At these points, actions must be taken by the application to continue orcomplete the TWI transfer. The TWI transfer is suspended until the TWINT flag iscleared by software.

When the TWINT flag is set, the status code in TWSR is used to determine the appropri-ate software action. For each status code, the required software action and details of thefollowing serial transfer are given in Table 73 to Table 76. Note that the prescaler bitsare masked to zero in these tables.

Master Transmitter Mode In the Master Transmitter mode, a number of data bytes are transmitted to a slavereceiver (see Figure 86). In order to enter a Master mode, a START condition must betransmitted. The format of the following address packet determines whether MasterTransmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MTmode is entered, if SLA+R is transmitted, MR mode is entered. All the status codesmentioned in this section assume that the prescaler bits are zero or are masked to zero.

180 ATmega16(L) 2466E–AVR–10/02

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Figure 86. Data Transfer in Master Transmitter Mode

A START condition is sent by writing the following value to TWCR:

TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written toone to transmit a START condition and TWINT must be written to one to clear theTWINT flag. The TWI will then test the Two-wire Serial Bus and generate a START con-dition as soon as the bus becomes free. After a START condition has been transmitted,the TWINT flag is set by hardware, and the status code in TWSR will be $08 (See Table73). In order to enter MT mode, SLA+W must be transmitted. This is done by writingSLA+W to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) tocontinue the transfer. This is accomplished by writing the following value to TWCR:

When SLA+W have been transmitted and an acknowledgement bit has been received,TWINT is set again and a number of status codes in TWSR are possible. Possible sta-tus codes in master mode are $18, $20, or $38. The appropriate action to be taken foreach of these status codes is detailed in Table 73.

When SLA+W has been successfully transmitted, a data packet should be transmitted.This is done by writing the data byte to TWDR. TWDR must only be written whenTWINT is high. If not, the access will be discarded, and the Write Collision bit (TWWC)will be set in the TWCR register. After updating TWDR, the TWINT bit should be cleared(by writing it to one) to continue the transfer. This is accomplished by writing the follow-ing value to TWCR:

This scheme is repeated until the last byte has been sent and the transfer is ended bygenerating a STOP condition or a repeated START condition. A STOP condition is gen-erated by writing the following value to TWCR:

A REPEATED START condition is generated by writing the following value to TWCR:

TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE

Value 1 X 1 0 X 1 0 X


Value 1 X 0 0 X 1 0 X


Value 1 X 0 0 X 1 0 X


Value 1 X 0 1 X 1 0 X


Value 1 X 1 0 X 1 0 X

Device 1MASTER

TRANSMITTER

Device 2SLAVE

RECEIVERDevice 3 Device n

SDA

SCL

........ R1 R2

VCC

1812466E–AVR–10/02

After a repeated START condition (state $10) the Two-wire Serial Interface can accessthe same slave again, or a new slave without transmitting a STOP condition. RepeatedSTART enables the master to switch between slaves, master transmitter mode andmaster receiver mode without losing control of the bus.

Table 73. Status Codes for Master Transmitter ModeStatus Code(TWSR)Prescaler Bitsare 0

Status of the Two-wire SerialBus and Two-wire Serial Inter-face Hardware

Application Software Response

Next Action Taken by TWI HardwareTo/from TWDR

To TWCR

STA STO TWINT TWEA

$08 A START condition has beentransmitted

Load SLA+W X 0 1 X SLA+W will be transmitted;ACK or NOT ACK will be received

$10 A repeated START conditionhas been transmitted

Load SLA+W or

Load SLA+R

X

X

0

0

1

1

X

X

SLA+W will be transmitted;ACK or NOT ACK will be receivedSLA+R will be transmitted;Logic will switch to Master Receiver mode

$18 SLA+W has been transmitted;ACK has been received

Load data byte or

No TWDR action orNo TWDR action or

No TWDR action

0

10

1

0

01

1

1

11

1

X

XX

X

Data byte will be transmitted and ACK or NOT ACK will be receivedRepeated START will be transmittedSTOP condition will be transmitted andTWSTO flag will be ResetSTOP condition followed by a START condition will be transmitted and TWSTO flag will be Reset

$20 SLA+W has been transmitted;NOT ACK has been received

Load data byte or


No TWDR action

0

10

1

0

01

1

1

11

1

X

XX

X

Data byte will be transmitted and ACK or NOT ACK will be receivedRepeated START will be transmittedSTOP condition will be transmitted andTWSTO flag will be resetSTOP condition followed by a START condition will be transmitted and TWSTO flag will be reset

$28 Data byte has been transmitted;ACK has been received

Load data byte or


No TWDR action

0

10

1

0

01

1

1

11

1

X

XX

X


$30 Data byte has been transmitted;NOT ACK has been received

Load data byte or


No TWDR action

0

10

1

0

01

1

1

11

1

X

XX

X


$38 Arbitration lost in SLA+W or databytes

No TWDR action or

No TWDR action

0

1

0

0

1

1

X

X

Two-wire Serial Bus will be released and not addressed slave mode enteredA START condition will be transmitted when the bus be-comes free

182 ATmega16(L) 2466E–AVR–10/02

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Figure 87. Formats and States in the Master Transmitter Mode

Master Receiver Mode In the Master Receiver mode, a number of data bytes are received from a slave trans-mitter (see Figure 88). In order to enter a Master mode, a START condition must betransmitted. The format of the following address packet determines whether MasterTransmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MTmode is entered, if SLA+R is transmitted, MR mode is entered. All the status codesmentioned in this section assume that the prescaler bits are zero or are masked to zero.

S SLA W A DATA A P

$08 $18 $28

R SLA W

$10

A P

$20

P

$30

A or A

$38

A

Other mastercontinues A or A

$38

Other mastercontinues

R

A

$68


$78 $B0To correspondingstates in slave mode

MT

MR

Successfulltransmissionto a slavereceiver

Next transferstarted with arepeated startcondition

Not acknowledgereceived after theslave address

Not acknowledgereceived after a databyte

Arbitration lost in slaveaddress or data byte

Arbitration lost andaddressed as slave

DATA A

n

From master to slave

From slave to master

Any number of data bytesand their associated acknowledge bits

This number (contained in TWSR) correspondsto a defined state of the Two-wire Serial Bus. Theprescaler bits are zero or masked to zero

S

1832466E–AVR–10/02

Figure 88. Data Transfer in Master Receiver Mode

A START condition is sent by writing the following value to TWCR:

TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must bewritten to one to transmit a START condition and TWINT must be set to clear the TWINTflag. The TWI will then test the Two-wire Serial Bus and generate a START condition assoon as the bus becomes free. After a START condition has been transmitted, theTWINT flag is set by hardware, and the status code in TWSR will be $08 (See Table 73).In order to enter MR mode, SLA+R must be transmitted. This is done by writing SLA+Rto TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to continuethe transfer. This is accomplished by writing the following value to TWCR:

When SLA+R have been transmitted and an acknowledgement bit has been received,TWINT is set again and a number of status codes in TWSR are possible. Possible sta-tus codes in master mode are $38, $40, or $48. The appropriate action to be taken foreach of these status codes is detailed in Table 74. Received data can be read from theTWDR register when the TWINT flag is set high by hardware. This scheme is repeateduntil the last byte has been received. After the last byte has been received, the MRshould inform the ST by sending a NACK after the last received data byte. The transferis ended by generating a STOP condition or a repeated START condition. A STOP con-dition is generated by writing the following value to TWCR:

A REPEATED START condition is generated by writing the following value to TWCR:

After a repeated START condition (state $10) the Two-wire Serial Interface can accessthe same slave again, or a new slave without transmitting a STOP condition. RepeatedSTART enables the master to switch between slaves, Master Transmitter mode andMaster Receiver mode without losing control over the bus.


Value 1 X 1 0 X 1 0 X


Value 1 X 0 0 X 1 0 X


Value 1 X 0 1 X 1 0 X


Value 1 X 1 0 X 1 0 X

Device 1MASTER

RECEIVER

Device 2SLAVE

TRANSMITTERDevice 3 Device n

SDA

SCL

........ R1 R2

VCC

184 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Table 74. Status Codes for Master Receiver Mode Status Code(TWSR) Prescaler Bitsare 0




To TWCR

STA STO TWINT TWEA

$08 A START condition has beentransmitted

Load SLA+R X 0 1 X SLA+R will be transmittedACK or NOT ACK will be received

$10 A repeated START conditionhas been transmitted

Load SLA+R or

Load SLA+W

X

X

0

0

1

1

X

X

SLA+R will be transmittedACK or NOT ACK will be receivedSLA+W will be transmittedLogic will switch to masTer Transmitter mode

$38 Arbitration lost in SLA+R or NOTACK bit

No TWDR action or

No TWDR action

0

1

0

0

1

1

X

X

Two-wire Serial Bus will be released and not addressed slave mode will be enteredA START condition will be transmitted when the busbecomes free

$40 SLA+R has been transmitted;ACK has been received

No TWDR action or

No TWDR action

0

0

0

0

1

1

0

1

Data byte will be received and NOT ACK will be returnedData byte will be received and ACK will be returned

$48 SLA+R has been transmitted;NOT ACK has been received


No TWDR action

10

1

01

1

11

1

XX

X

Repeated START will be transmittedSTOP condition will be transmitted and TWSTO flag will be resetSTOP condition followed by a START condition will be transmitted and TWSTO flag will be reset

$50 Data byte has been received;ACK has been returned

Read data byte or

Read data byte

0

0

0

0

1

1

0

1


$58 Data byte has been received;NOT ACK has been returned

Read data byte orRead data byte or

Read data byte

10

1

01

1

11

1

XX

X

Repeated START will be transmittedSTOP condition will be transmitted and TWSTO flag will be resetSTOP condition followed by a START condition will be transmitted and TWSTO flag will be reset

1852466E–AVR–10/02

Figure 89. Formats and States in the Master Receiver Mode

Slave Receiver Mode In the Slave Receiver mode, a number of data bytes are received from a master trans-mitter (see Figure 90). All the status codes mentioned in this section assume that theprescaler bits are zero or are masked to zero.

Figure 90. Data Transfer in Slave Receiver Mode

To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:

S SLA R A DATA A

$08 $40 $50

SLA R

$10

A P

$48

A or A

$38


$38


W

A

$68


$78 $B0To correspondingstates in slave mode

MR

MT

Successfullreceptionfrom a slavereceiver

Next transferstarted with arepeated startcondition

Not acknowledgereceived after theslave address

Arbitration lost in slaveaddress or data byte

Arbitration lost andaddressed as slave

DATA A

n




This number (contained in TWSR) correspondsto a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero

PDATA A

$58

A

RS

TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE

Value Device’s Own Slave Address

Device 3 Device n

SDA

SCL

........ R1 R2

VCC

Device 2MASTER

TRANSMITTER

Device 1SLAVE

RECEIVER

186 ATmega16(L) 2466E–AVR–10/02

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The upper seven bits are the address to which the Two-wire Serial Interface will respondwhen addressed by a master. If the LSB is set, the TWI will respond to the general calladdress ($00), otherwise it will ignore the general call address.

TWEN must be written to one to enable the TWI. The TWEA bit must be written to oneto enable the acknowledgement of the device’s own slave address or the general calladdress. TWSTA and TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by itsown slave address (or the general call address if enabled) followed by the data directionbit. If the direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST modeis entered. After its own slave address and the write bit have been received, the TWINTflag is set and a valid status code can be read from TWSR. The status code is used todetermine the appropriate software action. The appropriate action to be taken for eachstatus code is detailed in Table 75. The Slave Receiver mode may also be entered ifarbitration is lost while the TWI is in the Master mode (see states $68 and $78).

If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”)to SDA after the next received data byte. This can be used to indicate that the slave isnot able to receive any more bytes. While TWEA is zero, the TWI does not acknowledgeits own slave address. However, the Two-wire Serial Bus is still monitored and addressrecognition may resume at any time by setting TWEA. This implies that the TWEA bitmay be used to temporarily isolate the TWI from the Two-wire Serial Bus.

In all sleep modes other than Idle Mode, the clock system to the TWI is turned off. If theTWEA bit is set, the interface can still acknowledge its own slave address or the generalcall address by using the Two-wire Serial Bus clock as a clock source. The part will thenwake up from sleep and the TWI will hold the SCL clock low during the wake up anduntil the TWINT flag is cleared (by writing it to one). Further data reception will be car-ried out as normal, with the AVR clocks running as normal. Observe that if the AVR isset up with a long start-up time, the SCL line may be held low for a long time, blockingother data transmissions.

Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the lastbyte present on the bus when waking up from these sleep modes.


Value 0 1 0 0 0 1 0 X

1872466E–AVR–10/02

Table 75. Status Codes for Slave Receiver Mode Status Code(TWSR)Prescaler Bitsare 0

Status of the Two-wire Serial Busand Two-wire Serial InterfaceHardware



To TWCR

STA STO TWINT TWEA

$60 Own SLA+W has been received;ACK has been returned

No TWDR action or

No TWDR action

X

X

0

0

1

1

0

1


$68 Arbitration lost in SLA+R/W asmaster; own SLA+W has been received; ACK has been returned

No TWDR action or

No TWDR action

X

X

0

0

1

1

0

1


$70 General call address has been received; ACK has been returned

No TWDR action or

No TWDR action

X

X

0

0

1

1

0

1


$78 Arbitration lost in SLA+R/W asmaster; General call address hasbeen received; ACK has been returned

No TWDR action or

No TWDR action

X

X

0

0

1

1

0

1


$80 Previously addressed with ownSLA+W; data has been received;ACK has been returned

Read data byte or

Read data byte

X

X

0

0

1

1

0

1


$88 Previously addressed with ownSLA+W; data has been received;NOT ACK has been returned

Read data byte or

Read data byte or

Read data byte or

Read data byte

0

0

1

1

0

0

0

0

1

1

1

1

0

1

0

1

Switched to the not addressed Slave mode;no recognition of own SLA or GCASwitched to the not addressed Slave mode;own SLA will be recognized;GCA will be recognized if TWGCE = “1”Switched to the not addressed Slave mode;no recognition of own SLA or GCA;a START condition will be transmitted when the bus becomes freeSwitched to the not addressed Slave mode;own SLA will be recognized;GCA will be recognized if TWGCE = “1”;a START condition will be transmitted when the bus becomes free

$90 Previously addressed with general call; data has been re-ceived; ACK has been returned

Read data byte or

Read data byte

X

X

0

0

1

1

0

1


$98 Previously addressed with general call; data has been received; NOT ACK has been returned

Read data byte or

Read data byte or

Read data byte or

Read data byte

0

0

1

1

0

0

0

0

1

1

1

1

0

1

0

1


$A0 A STOP condition or repeatedSTART condition has been received while still addressed asslave

Read data byte or

Read data byte or

Read data byte or

Read data byte

0

0

1

1

0

0

0

0

1

1

1

1

0

1

0

1


188 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 91. Formats and States in the Slave Receiver Mode

Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a masterreceiver (see Figure 92). All the status codes mentioned in this section assume that theprescaler bits are zero or are masked to zero.

Figure 92. Data Transfer in Slave Transmitter Mode

To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:

S SLA W A DATA A

$60 $80

$88

A

$68

Reception of the ownslave address and one ormore data bytes. All areacknowledged

Last data byte receivedis not acknowledged

Arbitration lost as masterand addressed as slave

Reception of the general calladdress and one or more databytes

Last data byte received isnot acknowledged

n





P or SDATA A

$80 $A0

P or SA

A DATA A

$70 $90

$98

A

$78

P or SDATA A

$90 $A0

P or SA

General Call

Arbitration lost as master andaddressed as slave by general call

DATA A

TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE

Value Device’s Own Slave Address

Device 3 Device n

SDA

SCL

........ R1 R2

VCC

Device 2MASTER

RECEIVER

Device 1SLAVE

TRANSMITTER

1892466E–AVR–10/02

The upper seven bits are the address to which the Two-wire Serial Interface will respondwhen addressed by a master. If the LSB is set, the TWI will respond to the general calladdress ($00), otherwise it will ignore the general call address.

TWEN must be written to one to enable the TWI. The TWEA bit must be written to oneto enable the acknowledgement of the device’s own slave address or the general calladdress. TWSTA and TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by itsown slave address (or the general call address if enabled) followed by the data directionbit. If the direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR modeis entered. After its own slave address and the write bit have been received, the TWINTflag is set and a valid status code can be read from TWSR. The status code is used todetermine the appropriate software action. The appropriate action to be taken for eachstatus code is detailed in Table 76. The slave transmitter mode may also be entered ifarbitration is lost while the TWI is in the Master mode (see state $B0).

If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte ofthe transfer. State $C0 or state $C8 will be entered, depending on whether the masterreceiver transmits a NACK or ACK after the final byte. The TWI is switched to the notaddressed Slave mode, and will ignore the master if it continues the transfer. Thus themaster receiver receives all “1” as serial data. State $C8 is entered if the masterdemands additional data bytes (by transmitting ACK), even though the slave has trans-mitted the last byte (TWEA zero and expecting NACK from the master).

While TWEA is zero, the TWI does not respond to its own slave address. However, theTwo-wire Serial Bus is still monitored and address recognition may resume at any timeby setting TWEA. This implies that the TWEA bit may be used to temporarily isolate theTWI from the Two-wire Serial Bus.

In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If theTWEA bit is set, the interface can still acknowledge its own slave address or the generalcall address by using the Two-wire Serial Bus clock as a clock source. The part will thenwake up from sleep and the TWI will hold the SCL clock will low during the wake up anduntil the TWINT flag is cleared (by writing it to one). Further data transmission will becarried out as normal, with the AVR clocks running as normal. Observe that if the AVR isset up with a long start-up time, the SCL line may be held low for a long time, blockingother data transmissions.

Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the lastbyte present on the bus when waking up from these sleep modes.


Value 0 1 0 0 0 1 0 X

190 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Table 76. Status Codes for Slave Transmitter ModeStatus Code(TWSR)Prescaler Bitsare 0

Status of the Two-wire Serial Busand Two-wire Serial InterfaceHardware



To TWCR

STA STO TWINT TWEA

$A8 Own SLA+R has been received;ACK has been returned

Load data byte or

Load data byte

X

X

0

0

1

1

0

1

Last data byte will be transmitted and NOT ACK should be receivedData byte will be transmitted and ACK should be re-ceived

$B0 Arbitration lost in SLA+R/W asmaster; own SLA+R has been received; ACK has been returned

Load data byte or

Load data byte

X

X

0

0

1

1

0

1


$B8 Data byte in TWDR has been transmitted; ACK has been received

Load data byte or

Load data byte

X

X

0

0

1

1

0

1


$C0 Data byte in TWDR has been transmitted; NOT ACK has been received

No TWDR action or

No TWDR action or

No TWDR action or

No TWDR action

0

0

1

1

0

0

0

0

1

1

1

1

0

1

0

1


$C8 Last data byte in TWDR has beentransmitted (TWEA = “0”); ACKhas been received

No TWDR action or

No TWDR action or

No TWDR action or

No TWDR action

0

0

1

1

0

0

0

0

1

1

1

1

0

1

0

1


1912466E–AVR–10/02

Figure 93. Formats and States in the Slave Transmitter Mode

Miscellaneous States There are two status codes that do not correspond to a defined TWI state, see Table 77.

Status $F8 indicates that no relevant information is available because the TWINT flag isnot set. This occurs between other states, and when the TWI is not involved in a serialtransfer.

Status $00 indicates that a bus error has occurred during a Two-wire Serial Bus trans-fer. A bus error occurs when a START or STOP condition occurs at an illegal position inthe format frame. Examples of such illegal positions are during the serial transfer of anaddress byte, a data byte, or an acknowledge bit. When a bus error occurs, TWINT isset. To recover from a bus error, the TWSTO flag must set and TWINT must be clearedby writing a logic one to it. This causes the TWI to enter the not addressed slave modeand to clear the TWSTO flag (no other bits in TWCR are affected). The SDA and SCLlines are released, and no STOP condition is transmitted.

S SLA R A DATA A

$A8 $B8

A

$B0

Reception of the ownslave address and one ormore data bytes

Last data byte transmitted.Switched to not addressedslave (TWEA = '0')

Arbitration lost as masterand addressed as slave

n





P or SDATA

$C0

DATA A

A

$C8

P or SAll 1's

A

Table 77. Miscellaneous StatesStatus Code(TWSR)Prescaler Bitsare 0




To TWCR

STA STO TWINT TWEA

$F8 No relevant state informationavailable; TWINT = “0”

No TWDR action No TWCR action Wait or proceed current transfer

$00 Bus error due to an illegalSTART or STOP condition

No TWDR action 0 1 1 X Only the internal hardware is affected, no STOP condi-tion is sent on the bus. In all cases, the bus is released and TWSTO is cleared.

192 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Combining Several TWI Modes

In some cases, several TWI modes must be combined in order to complete the desiredaction. Consider for example reading data from a serial EEPROM. Typically, such atransfer involves the following steps:

1. The transfer must be initiated

2. The EEPROM must be instructed what location should be read

3. The reading must be performed

4. The transfer must be finished

Note that data is transmitted both from master to slave and vice versa. The master mustinstruct the slave what location it wants to read, requiring the use of the MT mode. Sub-sequently, data must be read from the slave, implying the use of the MR mode. Thus,the transfer direction must be changed. The master must keep control of the bus duringall these steps, and the steps should be carried out as an atomical operation. If this prin-ciple is violated in a multimaster system, another master can alter the data pointer in theEEPROM between steps 2 and 3, and the master will read the wrong data location.Such a change in transfer direction is accomplished by transmitting a REPEATEDSTART between the transmission of the address byte and reception of the data. After aREPEATED START, the master keeps ownership of the bus. The following figure showsthe flow in this transfer.

Figure 94. Combining Several TWI Modes to Access a Serial EEPROM

Multi-master Systems and Arbitration

If multiple masters are connected to the same bus, transmissions may be initiated simul-taneously by one or more of them. The TWI standard ensures that such situations arehandled in such a way that one of the masters will be allowed to proceed with the trans-fer, and that no data will be lost in the process. An example of an arbitration situation isdepicted below, where two masters are trying to transmit data to a slave receiver.

Figure 95. An Arbitration Example

Master Transmitter Master Receiver

S = START Rs = REPEATED START P = STOP

Transmitted from Master to Slave Transmitted from Slave to Master

S SLA+W A ADDRESS A Rs SLA+R A DATA A P

Device 1MASTER

TRANSMITTER

Device 2MASTER

TRANSMITTER

Device 3SLAVE

RECEIVERDevice n

SDA

SCL

........ R1 R2

VCC

1932466E–AVR–10/02

Several different scenarios may arise during arbitration, as described below:

• Two or more masters are performing identical communication with the same slave. In this case, neither the slave nor any of the masters will know about the bus contention.

• Two or more masters are accessing the same slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a one on SDA while another master outputs a zero will lose the arbitration. Losing masters will switch to not addressed slave mode or wait until the bus is free and transmit a new START condition, depending on application software action.

• Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters trying to output a one on SDA while another master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to slave mode to check if they are being addressed by the winning master. If addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit. If they are not being addressed, they will switch to not addressed slave mode or wait until the bus is free and transmit a new START condition, depending on application software action.

This is summarized in Figure 96. Possible status values are given in circles.

Figure 96. Possible Status Codes Caused by Arbitration

OwnAddress / General Call

received

Arbitration lost in SLA

TWI bus will be released and not addressed slave mode will be enteredA START condition will be transmitted when the bus becomes free

No

Arbitration lost in Data

Direction

Yes

Write Data byte will be received and NOT ACK will be returnedData byte will be received and ACK will be returned

Last data byte will be transmitted and NOT ACK should be receivedData byte will be transmitted and ACK should be received

ReadB0

68/78

38

SLASTART Data STOP

194 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and nega-tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage onthe negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’soutput can be set to trigger the Timer/Counter1 Input Capture function. In addition, thecomparator can trigger a separate interrupt, exclusive to the Analog Comparator. Theuser can select Interrupt triggering on comparator output rise, fall or toggle. A block dia-gram of the comparator and its surrounding logic is shown in Figure 97.

Figure 97. Analog Comparator Block Diagram(2)

Notes: 1. See Table 79 on page 197.2. Refer to Figure 1 on page 2 and Table 25 on page 55 for Analog Comparator pin

placement.


• Bit 3 – ACME: Analog Comparator Multiplexer Enable

When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA iszero), the ADC multiplexer selects the negative input to the Analog Comparator. Whenthis bit is written logic zero, AIN1 is applied to the negative input of the Analog Compar-ator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” onpage 197.

Analog Comparator Control and Status Register – ACSR

ACBG

BANDGAPREFERENCE

ADC MULTIPLEXEROUTPUT

ACMEADEN

(1)

Bit 7 6 5 4 3 2 1 0




Bit 7 6 5 4 3 2 1 0

ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR


Initial Value 0 0 N/A 0 0 0 0 0

1952466E–AVR–10/02

• Bit 7 – ACD: Analog Comparator Disable

When this bit is written logic one, the power to the Analog Comparator is switched off.This bit can be set at any time to turn off the Analog Comparator. This will reduce powerconsumption in active and Idle mode. When changing the ACD bit, the Analog Compar-ator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interruptcan occur when the bit is changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference voltage replaces the positive input to theAnalog Comparator. When this bit is cleared, AIN0 is applied to the positive input of theAnalog Comparator. See “Internal Voltage Reference” on page 39.

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected toACO. The synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt modedefined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed ifthe ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when execut-ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing alogic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Ana-log Comparator Interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, this bit enables the Input Capture function in Timer/Counter1 tobe triggered by the Analog Comparator. The comparator output is in this case directlyconnected to the Input Capture front-end logic, making the comparator utilize the noisecanceler and edge select features of the Timer/Counter1 Input Capture interrupt. Whenwritten logic zero, no connection between the Analog Comparator and the Input Capturefunction exists. To make the comparator trigger the Timer/Counter1 Input Capture inter-rupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set.

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator inter-rupt. The different settings are shown in Table 78.

Table 78. ACIS1/ACIS0 Settings

ACIS1 ACIS0 Interrupt Mode

0 0 Comparator Interrupt on Output Toggle

0 1 Reserved

1 0 Comparator Interrupt on Falling Output Edge

1 1 Comparator Interrupt on Rising Output Edge

196 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis-abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interruptcan occur when the bits are changed.

Analog Comparator Multiplexed Input

It is possible to select any of the ADC7..0 pins to replace the negative input to the Ana-log Comparator. The ADC multiplexer is used to select this input, and consequently, theADC must be switched off to utilize this feature. If the Analog Comparator MultiplexerEnable bit (ACME in SFIOR) is set and the ADC is switched off (ADEN in ADCSRA iszero), MUX2..0 in ADMUX select the input pin to replace the negative input to the Ana-log Comparator, as shown in Table 79. If ACME is cleared or ADEN is set, AIN1 isapplied to the negative input to the Analog Comparator.

Table 79. Analog Comparator Multiplexed Input

ACME ADEN MUX2..0 Analog Comparator Negative Input

0 x xxx AIN1

1 1 xxx AIN1

1 0 000 ADC0

1 0 001 ADC1

1 0 010 ADC2

1 0 011 ADC3

1 0 100 ADC4

1 0 101 ADC5

1 0 110 ADC6

1 0 111 ADC7

1972466E–AVR–10/02

Analog to Digital Converter

Features • 10-bit Resolution• 0.5 LSB Integral Non-linearity• ±2 LSB Absolute Accuracy• 65 - 260 µs Conversion Time• Up to 15 kSPS at Maximum Resolution• 8 Multiplexed Single Ended Input Channels• 7 Differential Input Channels• 2 Differential Input Channels with Optional Gain of 10x and 200x(1)

• Optional Left adjustment for ADC Result Readout• 0 - VCC ADC Input Voltage Range• Selectable 2.56V ADC Reference Voltage• Free Running or Single Conversion Mode• ADC Start Conversion by Auto Triggering on Interrupt Sources• Interrupt on ADC Conversion Complete• Sleep Mode Noise Canceler

Note: 1. The differential input channels are not tested for devices in PDIP Package. This fea-ture is only guaranteed to work for devices in TQFP and MLF Packages

The ATmega16 features a 10-bit successive approximation ADC. The ADC is con-nected to an 8-channel Analog Multiplexer which allows 8 single-ended voltage inputsconstructed from the pins of Port A. The single-ended voltage inputs refer to 0V (GND).

The device also supports 16 differential voltage input combinations. Two of the differen-tial inputs (ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gainstage, providing amplification steps of 0 dB (1x), 20 dB (10x), or 46 dB (200x) on the dif-ferential input voltage before the A/D conversion. Seven differential analog inputchannels share a common negative terminal (ADC1), while any other ADC input can beselected as the positive input terminal. If 1x or 10x gain is used, 8-bit resolution can beexpected. If 200x gain is used, 7-bit resolution can be expected.

The ADC contains a Sample and Hold circuit which ensures that the input voltage to theADC is held at a constant level during conversion. A block diagram of the ADC is shownin Figure 98.

The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ morethan ±0.3 V from VCC. See the paragraph “ADC Noise Canceler” on page 206 on how toconnect this pin.

Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The volt-age reference may be externally decoupled at the AREF pin by a capacitor for betternoise performance.

198 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 98. Analog to Digital Converter Block Schematic

Operation The ADC converts an analog input voltage to a 10-bit digital value through successiveapproximation. The minimum value represents GND and the maximum value representsthe voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V refer-ence voltage may be connected to the AREF pin by writing to the REFSn bits in theADMUX Register. The internal voltage reference may thus be decoupled by an externalcapacitor at the AREF pin to improve noise immunity.

The analog input channel and differential gain are selected by writing to the MUX bits inADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage refer-ence, can be selected as single ended inputs to the ADC. A selection of ADC input pinscan be selected as positive and negative inputs to the differential gain amplifier.

If differential channels are selected, the differential gain stage amplifies the voltage dif-ference between the selected input channel pair by the selected gain factor. This

ADC CONVERSIONCOMPLETE IRQ

8-BIT DATA BUS

15 0

ADC MULTIPLEXERSELECT (ADMUX)

ADC CTRL. & STATUSREGISTER (ADCSRA)

ADC DATA REGISTER(ADCH/ADCL)

MU

X2

AD

IE

AD

AT

E

AD

SC

AD

EN

AD

IFA

DIF

MU

X1

MU

X0

AD

PS

0

AD

PS

1

AD

PS

2

MU

X3

CONVERSION LOGIC

10-BIT DAC

+-

SAMPLE & HOLDCOMPARATOR

INTERNAL 2.56V REFERENCE

MUX DECODER

MU

X4

AVCC

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

RE

FS

0

RE

FS

1

AD

LAR

+

-

CH

AN

NE

L S

ELE

CT

ION

GA

IN S

ELE

CT

ION

AD

C[9

:0]


GAINAMPLIFIER

AREF

BANDGAPREFERENCE

PRESCALER

SINGLE ENDED / DIFFERENTIAL SELECTION

GND

POS.INPUTMUX

NEG.INPUTMUX

TRIGGERSELECT

ADTS[2:0]

INTERRUPTFLAGS

ADHSM

START

1992466E–AVR–10/02

amplified value then becomes the analog input to the ADC. If single ended channels areused, the gain amplifier is bypassed altogether.

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage refer-ence and input channel selections will not go into effect until ADEN is set. The ADCdoes not consume power when ADEN is cleared, so it is recommended to switch off theADC before entering power saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers,ADCH and ADCL. By default, the result is presented right adjusted, but can optionallybe presented left adjusted by setting the ADLAR bit in ADMUX.

If the result is left adjusted and no more than 8-bit precision is required, it is sufficient toread ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the contentof the Data Registers belongs to the same conversion. Once ADCL is read, ADC accessto data registers is blocked. This means that if ADCL has been read, and a conversioncompletes before ADCH is read, neither register is updated and the result from the con-version is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers isre-enabled.

The ADC has its own interrupt which can be triggered when a conversion completes.When ADC access to the data registers is prohibited between reading of ADCH andADCL, the interrupt will trigger even if the result is lost.

Starting a Conversion A single conversion is started by writing a logical one to the ADC Start Conversion bit,ADSC. This bit stays high as long as the conversion is in progress and will be cleared byhardware when the conversion is completed. If a different data channel is selected whilea conversion is in progress, the ADC will finish the current conversion before performingthe channel change.

Alternatively, a conversion can be triggered automatically by various sources. Auto Trig-gering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. Thetrigger source is selected by setting the ADC Trigger Select bits, ADTS in SFIOR (seedescription of the ADTS bits for a list of the trigger sources). When a positive edgeoccurs on the selected trigger signal, the ADC prescaler is reset and a conversion isstarted. This provides a method of starting conversions at fixed intervals. If the triggersignal still is set when the conversion completes, a new conversion will not be started. Ifanother positive edge occurs on the trigger signal during conversion, the edge will beignored. Note that an interrupt flag will be set even if the specific interrupt is disabled orthe global interrupt enable bit in SREG is cleared. A conversion can thus be triggeredwithout causing an interrupt. However, the interrupt flag must be cleared in order to trig-ger a new conversion at the next interrupt event.

200 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 99. ADC Auto Trigger Logic

Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversionas soon as the ongoing conversion has finished. The ADC then operates in Free Run-ning mode, constantly sampling and updating the ADC Data Register. The firstconversion must be started by writing a logical one to the ADSC bit in ADCSRA. In thismode the ADC will perform successive conversions independently of whether the ADCInterrupt Flag, ADIF is cleared or not.

If Auto Triggering is enabled, single conversions can be started by writing ADSC inADCSRA to one. ADSC can also be used to determine if a conversion is in progress.The ADSC bit will be read as one during a conversion, independently of how the conver-sion was started.

Prescaling and Conversion Timing

Figure 100. ADC Prescaler

By default, the successive approximation circuitry requires an input clock frequencybetween 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get ahigher sample rate. Alternatively, setting the ADHSM bit in SFIOR allows an increasedADC clock frequency at the expense of higher power consumption.

The ADC module contains a prescaler, which generates an acceptable ADC clock fre-quency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bitsin ADCSRA. The prescaler starts counting from the moment the ADC is switched on by

ADSC

ADIF

SOURCE 1

SOURCE n

ADTS[2:0]

CONVERSIONLOGIC

PRESCALER

START CLKADC

.

.

.

. EDGEDETECTOR

ADATE

7-BIT ADC PRESCALER

ADC CLOCK SOURCE

CK

ADPS0ADPS1ADPS2

CK

/128

CK

/2

CK

/4

CK

/8

CK

/16

CK

/32

CK

/64

ResetADENSTART

2012466E–AVR–10/02

setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADENbit is set, and is continuously reset when ADEN is low.

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the con-version starts at the following rising edge of the ADC clock cycle. See “Differential GainChannels” on page 204 for details on differential conversion timing.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC isswitched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initializethe analog circuitry.

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normalconversion and 13.5 ADC clock cycles after the start of an first conversion. When a con-version is complete, the result is written to the ADC Data Registers, and ADIF is set. Insingle conversion mode, ADSC is cleared simultaneously. The software may then setADSC again, and a new conversion will be initiated on the first rising ADC clock edge.

When Auto Triggering is used, the prescaler is reset when the trigger event occurs. Thisassures a fixed delay from the trigger event to the start of conversion. In this mode, thesample-and-hold takes place 2 ADC clock cycles after the rising edge on the triggersource signal. Three additional CPU clock cycles are used for synchronization logic.

In Free Running mode, a new conversion will be started immediately after the conver-sion completes, while ADSC remains high. For a summary of conversion times, seeTable 80.

Figure 101. ADC Timing Diagram, First Conversion (Single Conversion Mode)

MSB of Result

LSB of Result

ADC Clock

ADSC

Sample & Hold

ADIF

ADCH

ADCL

Cycle Number

ADEN

1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2

First ConversionNextConversion

3

MUX and REFSUpdate MUX and REFS

Update

ConversionComplete

202 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 102. ADC Timing Diagram, Single Conversion

Figure 103. ADC Timing Diagram, Auto Triggered Conversion

Figure 104. ADC Timing Diagram, Free Running Conversion

1 2 3 4 5 6 7 8 9 10 11 12 13

MSB of Result

LSB of Result

ADC Clock

ADSC

ADIF

ADCH

ADCL

Cycle Number 1 2

One Conversion Next Conversion

3

Sample & HoldMUX and REFSUpdate

ConversionComplete MUX and REFS

Update

1 2 3 4 5 6 7 8 9 10 11 12 13

MSB of Result

LSB of Result

ADC Clock

TriggerSource

ADIF

ADCH

ADCL

Cycle Number 1 2


ConversionComplete

Prescaler Reset

ADATE

PrescalerReset

Sample & Hold

MUX and REFS Update

11 12 13

MSB of Result

LSB of Result

ADC Clock

ADSC

ADIF

ADCH

ADCL

Cycle Number1 2


3 4

ConversionComplete

Sample & Hold

MUX and REFSUpdate

2032466E–AVR–10/02

Differential Gain Channels When using differential gain channels, certain aspects of the conversion need to betaken into consideration.

Differential conversions are synchronized to the internal clock CKADC2 equal to half theADC clock. This synchronization is done automatically by the ADC interface in such away that the sample-and-hold occurs at a specific phase of CKADC2. A conversion initi-ated by the user (i.e., all single conversions, and the first free running conversion) whenCKADC2 is low will take the same amount of time as a single ended conversion (13 ADCclock cycles from the next prescaled clock cycle). A conversion initiated by the userwhen CKADC2 is high will take 14 ADC clock cycles due to the synchronization mecha-nism. In Free Running mode, a new conversion is initiated immediately after theprevious conversion completes, and since CKADC2 is high at this time, all automaticallystarted (i.e., all but the first) free running conversions will take 14 ADC clock cycles.

The gain stage is optimized for a bandwidth of 4 kHz at all gain settings. Higher frequen-cies may be subjected to non-linear amplification. An external low-pass filter should beused if the input signal contains higher frequency components than the gain stage band-width. Note that the ADC clock frequency is independent of the gain stage bandwidthlimitation. For example, the ADC clock period may be 6 µs, allowing a channel to besampled at 12 kSPS, regardless of the bandwidth of this channel.

If differential gain channels are used and conversions are started by Auto Triggering, theADC must be switched off between conversions. When Auto Triggering is used, theADC prescaler is reset before the conversion is started. Since the gain stage is depen-dent of a stable ADC clock prior to the conversion, this conversion will not be valid. Bydisabling and then re-enabling the ADC between each conversion (writing ADEN inADCSRA to “0” then to “1”), only extended conversions are performed. The result fromthe extended conversions will be valid. See “Prescaling and Conversion Timing” onpage 201 for timing details.

Changing Channel or Reference Selection

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a tem-porary register to which the CPU has random access. This ensures that the channelsand reference selection only takes place at a safe point during the conversion. Thechannel and reference selection is continuously updated until a conversion is started.Once the conversion starts, the channel and reference selection is locked to ensure asufficient sampling time for the ADC. Continuous updating resumes in the last ADCclock cycle before the conversion completes (ADIF in ADCSRA is set). Note that theconversion starts on the following rising ADC clock edge after ADSC is written. The useris thus advised not to write new channel or reference selection values to ADMUX untilone ADC clock cycle after ADSC is written.

Table 80. ADC Conversion Time

Condition

Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles)

First conversion 14.5 25

Normal conversions, single ended 1.5 13

Auto Triggered conversions 2 13.5

Normal conversions, differential 1.5/2.5 13/14

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If Auto Triggering is used, the exact time of the triggering event can be indeterministic.Special care must be taken when updating the ADMUX Register, in order to controlwhich conversion will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. Ifthe ADMUX register is changed in this period, the user cannot tell if the next conversionis based on the old or the new settings. ADMUX can be safely updated in the followingways:

1. When ADATE or ADEN is cleared.

2. During conversion, minimum one ADC clock cycle after the trigger event.

3. After a conversion, before the interrupt flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the nextADC conversion.

Special care should be taken when changing differential channels. Once a differentialchannel has been selected, the gain stage may take as much as 125 µs to stabilize tothe new value. Thus conversions should not be started within the first 125 µs afterselecting a new differential channel. Alternatively, conversion results obtained within thisperiod should be discarded.

The same settling time should be observed for the first differential conversion afterchanging ADC reference (by changing the REFS1:0 bits in ADMUX).

The settling time and gain stage bandwidth is independent of the ADHSM bit setting.

ADC Input Channels When changing channel selections, the user should observe the following guidelines toensure that the correct channel is selected:

In Single Conversion mode, always select the channel before starting the conversion.The channel selection may be changed one ADC clock cycle after writing one to ADSC.However, the simplest method is to wait for the conversion to complete before changingthe channel selection.

In Free Running mode, always select the channel before starting the first conversion.The channel selection may be changed one ADC clock cycle after writing one to ADSC.However, the simplest method is to wait for the first conversion to complete, and thenchange the channel selection. Since the next conversion has already started automati-cally, the next result will reflect the previous channel selection. Subsequent conversionswill reflect the new channel selection.

When switching to a differential gain channel, the first conversion result may have apoor accuracy due to the required settling time for the automatic offset cancellation cir-cuitry. The user should preferably disregard the first conversion result.

ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC.Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can beselected as either AVCC, internal 2.56V reference, or external AREF pin.

AVCC is connected to the ADC through a passive switch. The internal 2.56V referenceis generated from the internal bandgap reference (VBG) through an internal amplifier. Ineither case, the external AREF pin is directly connected to the ADC, and the referencevoltage can be made more immune to noise by connecting a capacitor between theAREF pin and ground. VREF can also be measured at the AREF pin with a high impedantvoltmeter. Note that VREF is a high impedant source, and only a capacitive load shouldbe connected in a system.

2052466E–AVR–10/02

If the user has a fixed voltage source connected to the AREF pin, the user may not usethe other reference voltage options in the application, as they will be shorted to theexternal voltage. If no external voltage is applied to the AREF pin, the user may switchbetween AVCC and 2.56V as reference selection. The first ADC conversion result afterswitching reference voltage source may be inaccurate, and the user is advised to dis-card this result.

If differential channels are used, the selected reference should not be closer to AVCCthan indicated in Table 121 on page 291.

ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode toreduce noise induced from the CPU core and other I/O peripherals. The noise cancelercan be used with ADC Noise Reduction and Idle mode. To make use of this feature, thefollowing procedure should be used:

1. Make sure that the ADC is enabled and is not busy converting. Single Con-version Mode must be selected and the ADC conversion complete interrupt must be enabled.

2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a con-version once the CPU has been halted.

3. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC con-version is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed.

Note that the ADC will not be automatically turned off when entering other sleep modesthan Idle mode and ADC Noise Reduction mode. The user is advised to write zero toADEN before entering such sleep modes to avoid excessive power consumption. If theADC is enabled in such sleep modes and the user wants to perform differential conver-sions, the user is advised to switch the ADC off and on after waking up from sleep toprompt an extended conversion to get a valid result.

Analog Input Circuitry The Analog Input Circuitry for single ended channels is illustrated in Figure 105. An ana-log source applied to ADCn is subjected to the pin capacitance and input leakage of thatpin, regardless of whether that channel is selected as input for the ADC. When the chan-nel is selected, the source must drive the S/H capacitor through the series resistance(combined resistance in the input path).

The ADC is optimized for analog signals with an output impedance of approximately10 kΩ or less. If such a source is used, the sampling time will be negligible. If a sourcewith higher impedance is used, the sampling time will depend on how long time thesource needs to charge the S/H capacitor, with can vary widely. The user is recom-mended to only use low impedant sources with slowly varying signals, since thisminimizes the required charge transfer to the S/H capacitor.

If differential gain channels are used, the input circuitry looks somewhat different,although source impedances of a few hundred kΩ or less is recommended.

Signal components higher than the Nyquist frequency (fADC/2) should not be present foreither kind of channels, to avoid distortion from unpredictable signal convolution. Theuser is advised to remove high frequency components with a low-pass filter beforeapplying the signals as inputs to the ADC.

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Figure 105. Analog Input Circuitry

Analog Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect theaccuracy of analog measurements. If conversion accuracy is critical, the noise level canbe reduced by applying the following techniques:

1. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks.

2. The AVCC pin on the device should be connected to the digital VCC supply voltage via an LC network as shown in Figure 106.

3. Use the ADC noise canceler function to reduce induced noise from the CPU.

4. If any ADC port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress.

Figure 106. ADC Power Connections

ADCn

IIH

1..100 kΩCS/H= 14 pF

VCC/2

IIL

GN

D

VC

C

PA

0 (A

DC

0)

PA

1 (A

DC

1)

PA

2 (A

DC

2)

PA

3 (A

DC

3)

PA4 (ADC4)

PA5 (ADC5)

PA6 (ADC6)

PA7 (ADC7)

AREF

AVCC

GND

PC7

10µH

100n

FA

nalo

g G

roun

d P

lane

2072466E–AVR–10/02

Offset Compensation Schemes

The gain stage has a built-in offset cancellation circuitry that nulls the offset of differen-tial measurements as much as possible. The remaining offset in the analog path can bemeasured directly by selecting the same channel for both differential inputs. This offsetresidue can be then subtracted in software from the measurement results. Using thiskind of software based offset correction, offset on any channel can be reduced belowone LSB.

ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n

steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.

Several parameters describe the deviation from the ideal behavior:

• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB.

Figure 107. Offset Error

• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB

Figure 108. Gain Error

Output Code

VREF Input Voltage

Ideal ADC

Actual ADC

OffsetError

Output Code

VREF Input Voltage

Ideal ADC

Actual ADC

GainError

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• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB.

Figure 109. Integral Non-linearity (INL)

• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.

Figure 110. Differential Non-linearity (DNL)

• Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB.

• Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of Offset, Gain Error, Differential Error, Non-linearity, and Quantization Error. Ideal value: ±0.5 LSB.

Output Code

VREF Input Voltage

Ideal ADC

Actual ADC

INL

Output Code

0x3FF

0x000

0 VREF Input Voltage

DNL

1 LSB

2092466E–AVR–10/02

ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found inthe ADC Result Registers (ADCL, ADCH).

For single ended conversion, the result is

where VIN is the voltage on the selected input pin and VREF the selected voltage refer-ence (see Table 82 on page 211 and Table 83 on page 212). 0x000 represents analogground, and 0x3FF represents the selected reference voltage minus one LSB.

If differential channels are used, the result is

where VPOS is the voltage on the positive input pin, VNEG the voltage on the negativeinput pin, GAIN the selected gain factor, and VREF the selected voltage reference. Theresult is presented in two’s complement form, from 0x200 (-512d) through 0x1FF(+511d). Note that if the user wants to perform a quick polarity check of the results, it issufficient to read the MSB of the result (ADC9 in ADCH). If this bit is one, the result isnegative, and if this bit is zero, the result is positive. Figure 111 shows the decoding ofthe differential input range.

Table 81 shows the resulting output codes if the differential input channel pair (ADCn -ADCm) is selected with a gain of GAIN and a reference voltage of VREF.

Figure 111. Differential Measurement Range

ADCVIN 1024⋅

VREF--------------------------=

ADCVPOS VNEG–( ) GAIN 512⋅ ⋅

VREF------------------------------------------------------------------------=

0

Output Code

0x1FF

0x000

VREF/GAIN Differential InputVoltage (Volts)

0x3FF

0x200

- VREF/GAIN

210 ATmega16(L) 2466E–AVR–10/02

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Example:

ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result)

Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.

ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270

ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR rightadjusts the result: ADCL = 0x70, ADCH = 0x02.

ADC Multiplexer Selection Register – ADMUX

• Bit 7:6 – REFS1:0: Reference Selection Bits

These bits select the voltage reference for the ADC, as shown in Table 82. If these bitsare changed during a conversion, the change will not go in effect until this conversion iscomplete (ADIF in ADCSRA is set). The internal voltage reference options may not beused if an external reference voltage is being applied to the AREF pin.

• Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC DataRegister. Write one to ADLAR to left adjust the result. Otherwise, the result is rightadjusted. Changing the ADLAR bit will affect the ADC data register immediately, regard-

Table 81. Correlation between Input Voltage and Output Codes

VADCn Read code Corresponding Decimal Value

VADCm + VREF/GAIN 0x1FF 511

VADCm + 0.999 VREF/GAIN 0x1FF 511

VADCm + 0.998 VREF/GAIN 0x1FE 510

... ... ...

VADCm + 0.001 VREF/GAIN 0x001 1

VADCm 0x000 0

VADCm - 0.001 VREF/GAIN 0x3FF -1

... ... ...

VADCm - 0.999 VREF/GAIN 0x201 -511

VADCm - VREF/GAIN 0x200 -512

Bit 7 6 5 4 3 2 1 0

REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADMUX



Table 82. Voltage Reference Selections for ADC

REFS1 REFS0 Voltage Reference Selection

0 0 AREF, Internal Vref turned off

0 1 AVCC with external capacitor at AREF pin

1 0 Reserved

1 1 Internal 2.56V Voltage Reference with external capacitor at AREF pin

2112466E–AVR–10/02

less of any ongoing conversions. For a complete description of this bit, see “The ADCData Register – ADCL and ADCH” on page 214.

• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits

The value of these bits selects which combination of analog inputs are connected to theADC. These bits also select the gain for the differential channels. See Table 83 fordetails. If these bits are changed during a conversion, the change will not go in effectuntil this conversion is complete (ADIF in ADCSRA is set).

Table 83. Input Channel and Gain Selections

MUX4..0Single Ended Input

Positive Differential Input

Negative Differential Input Gain

00000 ADC0

00001 ADC1

00010 ADC2

00011 ADC3 N/A

00100 ADC4

00101 ADC5

00110 ADC6

00111 ADC7

01000 ADC0 ADC0 10x

01001 ADC1 ADC0 10x

01010(1) ADC0 ADC0 200x

01011(1) ADC1 ADC0 200x

01100 ADC2 ADC2 10x

01101 ADC3 ADC2 10x

01110(1) ADC2 ADC2 200x

01111(1) ADC3 ADC2 200x

10000 ADC0 ADC1 1x

10001 ADC1 ADC1 1x

10010 N/A ADC2 ADC1 1x

10011 ADC3 ADC1 1x

10100 ADC4 ADC1 1x

10101 ADC5 ADC1 1x

10110 ADC6 ADC1 1x

10111 ADC7 ADC1 1x

11000 ADC0 ADC2 1x

11001 ADC1 ADC2 1x

11010 ADC2 ADC2 1x

11011 ADC3 ADC2 1x

11100 ADC4 ADC2 1x

212 ATmega16(L) 2466E–AVR–10/02

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Note: 1. The differential input channels are not tested for devices in PDIP Package. This fea-ture is only guaranteed to work for devices in TQFP and MLF Packages

ADC Control and Status Register A – ADCSRA

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turn-ing the ADC off while a conversion is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion mode, write this bit to one to start each conversion. In Free Run-ning Mode, write this bit to one to start the first conversion. The first conversion afterADSC has been written after the ADC has been enabled, or if ADSC is written at thesame time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal13. This first conversion performs initialization of the ADC.

ADSC will read as one as long as a conversion is in progress. When the conversion iscomplete, it returns to zero. Writing zero to this bit has no effect.

• Bit 5 – ADATE: ADC Auto Trigger Enable

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will starta conversion on a positive edge of the selected trigger signal. The trigger source isselected by setting the ADC Trigger Select bits, ADTS in SFIOR.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the Data Registers are updated.The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit inSREG are set. ADIF is cleared by hardware when executing the corresponding interrupthandling vector. Alternatively, ADIF is cleared by writing a logical one to the flag.Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be dis-abled. This also applies if the SBI and CBI instructions are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Com-plete Interrupt is activated.

11101 ADC5 ADC2 1x

11110 1.22 V (VBG) N/A

11111 0 V (GND)

Table 83. Input Channel and Gain Selections (Continued)

MUX4..0Single Ended Input

Positive Differential Input

Negative Differential Input Gain

Bit 7 6 5 4 3 2 1 0

ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA



2132466E–AVR–10/02

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the XTAL frequency and the inputclock to the ADC.

The ADC Data Register – ADCL and ADCH

ADLAR = 0

ADLAR = 1

When an ADC conversion is complete, the result is found in these two registers. If differ-ential channels are used, the result is presented in two’s complement form.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Conse-quently, if the result is left adjusted and no more than 8-bit precision is required, it issufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result isread from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared(default), the result is right adjusted.

Table 84. ADC Prescaler Selections

ADPS2 ADPS1 ADPS0 Division Factor

0 0 0 2

0 0 1 2

0 1 0 4

0 1 1 8

1 0 0 16

1 0 1 32

1 1 0 64

1 1 1 128

Bit 15 14 13 12 11 10 9 8

– – – – – – ADC9 ADC8 ADCH

ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL

7 6 5 4 3 2 1 0


R R R R R R R R


0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8

ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH

ADC1 ADC0 – – – – – – ADCL

7 6 5 4 3 2 1 0


R R R R R R R R


0 0 0 0 0 0 0 0

214 ATmega16(L) 2466E–AVR–10/02

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• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC ConversionResult” on page 210.

Special FunctionIO Register – SFIOR

• Bit 7:5 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source willtrigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have noeffect. A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this willstart a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trig-ger event, even if the ADC Interrupt Flag is set.

• Bit 4 – ADHSM: ADC High Speed Mode

Writing this bit to one enables the ADC High Speed mode. This mode enables higherconversion rate at the expense of higher power consumption.

Bit 7 6 5 4 3 2 1 0




Table 85. ADC Auto Trigger Source Selections

ADTS2 ADTS1 ADTS0 Trigger Source

0 0 0 Free Running mode

0 0 1 Analog Comparator

0 1 0 External Interrupt Request 0

0 1 1 Timer/Counter0 Compare Match

1 0 0 Timer/Counter0 Overflow

1 0 1 Timer/Counter Compare Match B

1 1 0 Timer/Counter1 Overflow

1 1 1 Timer/Counter1 Capture Event

2152466E–AVR–10/02

JTAG Interface and On-chip Debug System

Features • JTAG (IEEE std. 1149.1 Compliant) Interface• Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard• Debugger Access to:

– All Internal Peripheral Units– Internal and External RAM– The Internal Register File– Program Counter– EEPROM and Flash Memories– Extensive On-chip Debug Support for Break Conditions, Including– AVR Break Instruction– Break on Change of Program Memory Flow– Single Step Break– Program Memory Breakpoints on Single Address or Address Range– Data Memory Breakpoints on Single Address or Address Range

• Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface• On-chip Debugging Supported by AVR Studio®

Overview The AVR IEEE std. 1149.1 compliant JTAG interface can be used for

• Testing PCBs by using the JTAG Boundary-scan capability

• Programming the non-volatile memories, Fuses and Lock bits

• On-chip Debugging

A brief description is given in the following sections. Detailed descriptions for Program-ming via the JTAG interface, and using the Boundary-scan Chain can be found in thesections “Programming via the JTAG Interface” on page 272 and “IEEE 1149.1 (JTAG)Boundary-scan” on page 222, respectively. The On-chip Debug support is consideredbeing private JTAG instructions, and distributed within ATMEL and to selected thirdparty vendors only.

Figure 112 shows a block diagram of the JTAG interface and the On-chip Debug sys-tem. The TAP Controller is a state machine controlled by the TCK and TMS signals. TheTAP Controller selects either the JTAG Instruction Register or one of several Data Reg-isters as the scan chain (Shift register) between the TDI input and TDO output. TheInstruction Register holds JTAG instructions controlling the behavior of a Data Register.

The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registersused for board-level testing. The JTAG Programming Interface (actually consisting ofseveral physical and virtual Data Registers) is used for JTAG Serial Programming viathe JTAG interface. The Internal Scan Chain and Break Point Scan Chain are used forOn-chip Debugging only.

Test Access Port – TAP The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology,these pins constitute the Test Access Port – TAP. These pins are:

• TMS: Test Mode Select. This pin is used for navigating through the TAP-controller state machine.

• TCK: Test Clock. JTAG operation is synchronous to TCK.

• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains).

• TDO: Test Data Out. Serial output data from Instruction register or Data Register.

216 ATmega16(L) 2466E–AVR–10/02

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The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT –which is not provided.

When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins,and the TAP controller is in reset. When programmed, the input TAP signals are inter-nally pulled high and the JTAG is enabled for Boundary-scan and programming. Thedevice is shipped with this fuse programmed.

For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin ismonitored by the debugger to be able to detect external reset sources. The debuggerbtacan also pull the RESET pin low to reset the whole system, assuming only open collec-tors on the reset line are used in the application.

Figure 112. Block Diagram

TAPCONTROLLER

TDITDOTCKTMS

FLASHMEMORY

AVR CPU

DIGITALPERIPHERAL

UNITS

JTAG / AVR CORECOMMUNICATION

INTERFACE

BREAKPOINTUNIT

FLOW CONTROLUNIT

OCD STATUSAND CONTROL

INTERNAL SCANCHAIN

MUX

INSTRUCTIONREGISTER

IDREGISTER

BYPASSREGISTER

JTAG PROGRAMMINGINTERFACE

PCInstruction

AddressData

BREAKPOINTSCAN CHAIN

ADDRESSDECODER

AN

AL

OG

PE

RIP

HE

RIA

LU

NIT

S

I/O PORT 0

I/O PORT n

BOUNDARY SCAN CHAIN

An

alo

g in

pu

tsC

on

tro

l & C

lock

lin

es

DEVICE BOUNDARY

2172466E–AVR–10/02

Figure 113. TAP Controller State Diagram

TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of theBoundary-scan circuitry, JTAG programming circuitry, or On-chip Debug system. Thestate transitions depicted in Figure 113 depend on the signal present on TMS (shownadjacent to each state transition) at the time of the rising edge at TCK. The initial stateafter a Power-On Reset is Test-Logic-Reset.

As a definition in this document, the LSB is shifted in and out first for all Shift Registers.

Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG inter-face is:

• At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift Instruction Register – Shift-IR state. While in this state, shift the four bits of the JTAG instructions into the JTAG instruction register from the TDI input at the rising edge of TCK. The TMS input must be held low during input of the 3 LSBs in order to remain in the Shift-IR state. The MSB of the instruction is shifted in when

Test-Logic-Reset

Run-Test/Idle

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-DR Scan

Capture-DR

0

1

0 1 1 1

0 0

0 0

1 1

1 0

1

1

0

1

0

0

1 0

1

1

0

1

0

0

00

11

218 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

this state is left by setting TMS high. While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out on the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected Data Register.

• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine.

• At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state. While in this state, upload the selected Data Register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be held low during input of all bits except the MSB. The MSB of the data is shifted in when this state is left by setting TMS high. While the Data Register is shifted in from the TDI pin, the parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the TDO pin.

• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register has a latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine.

As shown in the state diagram, the Run-Test/Idle state need not be entered betweenselecting JTAG instruction and using Data Registers, and some JTAG instructions mayselect certain functions to be performed in the Run-Test/Idle, making it unsuitable as anIdle state.Note: Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can

always be entered by holding TMS high for five TCK clock periods.

For detailed information on the JTAG specification, refer to the literature listed in “Bibli-ography” on page 221.

Using the Boundary-scan Chain

A complete description of the Boundary-scan capabilities are given in the section “IEEE1149.1 (JTAG) Boundary-scan” on page 222.

Using the On-chip Debug System

As shown in Figure 112, the hardware support for On-chip Debugging consists mainlyof:

• A scan chain on the interface between the internal AVR CPU and the internal peripheral units

• Break Point unit

• Communication interface between the CPU and JTAG system

All read or modify/write operations needed for implementing the Debugger are done byapplying AVR instructions via the internal AVR CPU Scan Chain. The CPU sends theresult to an I/O memory mapped location which is part of the communication interfacebetween the CPU and the JTAG system.

The Break Point Unit implements Break on Change of Program Flow, Single StepBreak, 2 Program Memory Break Points, and 2 combined Break Points. Together, the 4Break Points can be configured as either:

• 4 single Program Memory Break Points

• 3 Single Program Memory Break Point + 1 single Data Memory Break Point

• 2 single Program Memory Break Points + 2 single Data Memory Break Points

2192466E–AVR–10/02

• 2 single Program Memory Break Points + 1 Program Memory Break Point with mask (“range Break Point”)

• 2 single Program Memory Break Points + 1 Data Memory Break Point with mask (“range Break Point”)

A debugger, like the AVR Studio, may however use one or more of these resources forits internal purpose, leaving less flexibility to the end-user.

A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Spe-cific JTAG Instructions” on page 220.

The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addi-tion, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip Debug system to work. As a security feature, the On-chip Debug system is disabledwhen any Lock bits are set. Otherwise, the On-chip Debug system would have provideda back-door into a secured device.

The AVR JTAG ICE from Atmel is a powerful development tool for On-chip Debuggingof all AVR 8-bit RISC Microcontrollers with IEEE 1149.1 compliant JTAG interface. TheJTAG ICE and the AVR Studio user interface give the user complete control of the inter-nal resources of the microcontroller, helping to reduce development time by makingdebugging easier. The JTAG ICE performs real-time emulation of the micrcontrollerwhile it is running in a target system.

Please refer to the Support Tools section on the AVR pages on www.atmel.com for a fulldescription of the AVR JTEG ICE. AVR Studio can be downloaded free from Softwaresection on the same web site.

All necessary execution commands are available in AVR Studio, both on source leveland on disassembly level. The user can execute the program, single step through thecode either by tracing into or stepping over functions, step out of functions, place thecursor on a statement and execute until the statement is reached, stop the execution,and reset the execution target. In addition, the user can have an unlimited number ofcode breakpoints (using the BREAK instruction) and up to two data memory break-points, alternatively combined as a mask (range) Break Point.

On-chip Debug Specific JTAG Instructions

The On-chip Debug support is considered being private JTAG instructions, and distrib-uted within ATMEL and to selected third party vendors only. Instruction opcodes arelisted for reference.

PRIVATE0; $8 Private JTAG instruction for accessing On-chip Debug system.

PRIVATE1; $9 Private JTAG instruction for accessing On-chip Debug system.

PRIVATE2; $A Private JTAG instruction for accessing On-chip Debug system.

PRIVATE3; $B Private JTAG instruction for accessing On-chip Debug system.

220 ATmega16(L) 2466E–AVR–10/02

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On-chip Debug Related Register in I/O Memory

On-chip Debug Register – OCDR

The OCDR Register provides a communication channel from the running program in themicrocontroller to the debugger. The CPU can transfer a byte to the debugger by writingto this location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – isset to indicate to the debugger that the register has been written. When the CPU readsthe OCDR Register the 7 LSB will be from the OCDR Register, while the MSB is theIDRD bit. The debugger clears the IDRD bit when it has read the information.

In some AVR devices, this register is shared with a standard I/O location. In this case,the OCDR Register can only be accessed if the OCDEN Fuse is programmed, and thedebugger enables access to the OCDR register. In all other cases, the standard I/Olocation is accessed.

Refer to the debugger documentation for further information on how to use this register.

Using the JTAG Programming Capabilities

Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS,TDI and TDO. These are the only pins that need to be controlled/observed to performJTAG programming (in addition to power pins). It is not required to apply 12V externally.The JTAGEN fuse must be programmed and the JTD bit in the MCUSR Register mustbe cleared to enable the JTAG Test Access Port.

The JTAG programming capability supports:

• Flash programming and verifying

• EEPROM programming and verifying

• Fuse programming and verifying

• Lock bit programming and verifying

The Lock bit security is exactly as in Parallel Programming mode. If the Lock bits LB1 orLB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing achip erase. This is a security feature that ensures no back-door exists for reading out thecontent of a secured device.

The details on programming through the JTAG interface and programming specificJTAG instructions are given in the section “Programming via the JTAG Interface” onpage 272.

Bibliography For more information about general Boundary-scan, the following literature can beconsulted:

• IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE, 1993

• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley, 1992

Bit 7 6 5 4 3 2 1 0

MSB/IDRD LSB OCDR



2212466E–AVR–10/02

IEEE 1149.1 (JTAG) Boundary-scan

Features • JTAG (IEEE std. 1149.1 Compliant) Interface• Boundary-scan Capabilities According to the JTAG Standard• Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections• Supports the Optional IDCODE Instruction• Additional Public AVR_RESET Instruction to Reset the AVR

System Overview The Boundary-scan chain has the capability of driving and observing the logic levels onthe digital I/O pins, as well as the boundary between digital and analog logic for analogcircuitry having Off-chip connections. At system level, all ICs having JTAG capabilitiesare connected serially by the TDI/TDO signals to form a long Shift Register. An externalcontroller sets up the devices to drive values at their output pins, and observe the inputvalues received from other devices. The controller compares the received data with theexpected result. In this way, Boundary-scan provides a mechanism for testing intercon-nections and integrity of components on Printed Circuits Boards by using the four TAPsignals only.

The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAM-PLE/PRELOAD, and EXTEST, as well as the AVR specific public JTAG instructionAVR_RESET can be used for testing the Printed Circuit Board. Initial scanning of theData Register path will show the ID-code of the device, since IDCODE is the defaultJTAG instruction. It may be desirable to have the AVR device in Reset during Testmode. If not reset, inputs to the device may be determined by the scan operations, andthe internal software may be in an undetermined state when exiting the Test mode.Entering reset, the outputs of any Port Pin will instantly enter the high impedance state,making the HIGHZ instruction redundant. If needed, the BYPASS instruction can beissued to make the shortest possible scan chain through the device. The device can beset in the reset state either by pulling the external RESET pin low, or issuing theAVR_RESET instruction with appropriate setting of the Reset Data Register.

The EXTEST instruction is used for sampling external pins and loading output pins withdata. The data from the output latch will be driven out on the pins as soon as theEXTEST instruction is loaded into the JTAG IR-Register. Therefore, the SAMPLE/PRE-LOAD should also be used for setting initial values to the scan ring, to avoid damagingthe board when issuing the EXTEST instruction for the first time. SAMPLE/PRELOADcan also be used for taking a snapshot of the external pins during normal operation ofthe part.

The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCSRmust be cleared to enable the JTAG Test Access Port.

When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequencyhigher than the internal chip frequency is possible. The chip clock is not required to run.

Data Registers The data registers relevant for Boundary-scan operations are:

• Bypass Register

• Device Identification Register

• Reset Register

• Boundary-scan Chain

222 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Regis-ter is selected as path between TDI and TDO, the register is reset to 0 when leaving theCapture-DR controller state. The Bypass register can be used to shorten the scan chainon a system when the other devices are to be tested.

Device Identification Register Figure 114 shows the structure of the Device Identification Register.

Figure 114. The Format of the Device Identification Register

• Version

Version is a 4 bit number identifying the revision of the component. The relevant versionnumber is shown in Table 86.

• Part Number

The part number is a 16-bit code identifying the component. The JTAG Part Number forATmega16 is listed in Table 87.

• Manufacturer ID

The Manufacturer ID is a 11 bit code identifying the manufacturer. The JTAG manufac-turer ID for ATMEL is listed in Table 88.

Reset Register The Reset Register is a Test Data Register used to reset the part. Since the AVR tri-states Port Pins when reset, the Reset Register can also replace the function of theunimplemented optional JTAG instruction HIGHZ.

A high value in the Reset Register corresponds to pulling the External Reset low. Thepart is reset as long as there is a high value present in the Reset Register. Dependingon the Fuse settings for the clock options, the part will remain reset for a Reset Time-Out Period (refer to “Clock Sources” on page 23) after releasing the Reset Register. Theoutput from this Data Register is not latched, so the reset will take place immediately, asshown in Figure 115.

MSB LSB

Bit 31 28 27 12 11 1 0

Device ID Version Part Number Manufacturer ID 1

4 bits 16 bits 11 bits 1 bit

Table 86. JTAG Version Numbers

Version JTAG Version Number (Hex)

ATmega16 revision G 0x6

ATmega16 revision H 0x6

Table 87. AVR JTAG Part Number

Part Number JTAG Part Number (Hex)

ATmega16 0x9403

Table 88. Manufacturer ID

Manufacturer JTAG Man. ID (Hex)

ATMEL 0x01F

2232466E–AVR–10/02

Figure 115. Reset Register

Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels onthe digital I/O pins, as well as the boundary between digital and analog logic for analogcircuitry having Off-chip connections.

See “Boundary-scan Chain” on page 226 for a complete description.

Boundary-scan Specific JTAG Instructions

The instruction register is 4-bit wide, supporting up to 16 instructions. Listed below arethe JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZinstruction is not implemented, but all outputs with tri-state capability can be set in high-impedant state by using the AVR_RESET instruction, since the initial state for all portpins is tri-state.

As a definition in this data sheet, the LSB is shifted in and out first for all Shift Registers.

The OPCODE for each instruction is shown behind the instruction name in hex format.The text describes which Data Register is selected as path between TDI and TDO foreach instruction.

EXTEST; $0 Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register fortesting circuitry external to the AVR package. For port-pins, Pull-up Disable, OutputControl, Output Data, and Input Data are all accessible in the scan chain. For Analog cir-cuits having Off-chip connections, the interface between the analog and the digital logicis in the scan chain. The contents of the latched outputs of the Boundary-scan chain isdriven out as soon as the JTAG IR-register is loaded with the EXTEST instruction.

The active states are:

• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

• Shift-DR: The Internal Scan Chain is shifted by the TCK input.

• Update-DR: Data from the scan chain is applied to output pins.

IDCODE; $1 Optional JTAG instruction selecting the 32-bit ID register as Data Register. The ID regis-ter consists of a version number, a device number and the manufacturer code chosenby JEDEC. This is the default instruction after power-up.


• Capture-DR: Data in the IDCODE register is sampled into the Boundary-scan Chain.

• Shift-DR: The IDCODE scan chain is shifted by the TCK input.

D QFromTDI

ClockDR · AVR_RESET

To TDO

From other Internal andExternal Reset Sources

Internal Reset

224 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

SAMPLE_PRELOAD; $2 Mandatory JTAG instruction for pre-loading the output latches and talking a snap-shot ofthe input/output pins without affecting the system operation. However, the output latchesare not connected to the pins. The Boundary-scan Chain is selected as Data Register.


• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.

• Update-DR: Data from the Boundary-scan Chain is applied to the output latches. However, the output latches are not connected to the pins.

AVR_RESET; $C The AVR specific public JTAG instruction for forcing the AVR device into the Resetmode or releasing the JTAG Reset source. The TAP controller is not reset by thisinstruction. The one bit Reset Register is selected as Data Register. Note that the resetwill be active as long as there is a logic 'one' in the Reset Chain. The output from thischain is not latched.


• Shift-DR: The Reset Register is shifted by the TCK input.

BYPASS; $F Mandatory JTAG instruction selecting the Bypass Register for Data Register.


• Capture-DR: Loads a logic “0” into the Bypass Register.

• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.

Boundary-scan Related Register in I/O Memory


The MCU Control and Status Register contains control bits for general MCU functions,and provides information on which reset source caused an MCU Reset.

• Bits 7 – JTD: JTAG Interface Disable

When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disablingor enabling of the JTAG interface, a timed sequence must be followed when changingthis bit: The application software must write this bit to the desired value twice within fourcycles to change its value.

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Registerselected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, orby writing a logic zero to the flag.

Bit 7 6 5 4 3 2 1 0




2252466E–AVR–10/02

Boundary-scan Chain The Boundary-scan chain has the capability of driving and observing the logic levels onthe digital I/O pins, as well as the boundary between digital and analog logic for analogcircuitry having Off-chip connection.

Scanning the Digital Port Pins Figure 116 shows the Boundary-scan Cell for a bi-directional port pin with pull-up func-tion. The cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn– function, and a bi-directional pin cell that combines the three signals Output Control –OCxn, Output Data – ODxn, and Input Data – IDxn, into only a two-stage Shift Register.The port and pin indexes are not used in the following description.

The Boundary-scan logic is not included in the figures in the Data Sheet. Figure 117shows a simple digital Port Pin as described in the section “I/O Ports” on page 47. TheBoundary-scan details from Figure 116 replaces the dashed box in Figure 117.

When no alternate port function is present, the Input Data – ID – corresponds to thePINxn register value (but ID has no synchronizer), Output Data corresponds to thePORT register, Output Control corresponds to the Data Direction – DD Register, and thePull-up Enable – PUExn – corresponds to logic expression PUD · DDxn · PORTxn.

Digital alternate port functions are connected outside the dotted box in Figure 117 tomake the scan chain read the actual pin value. For Analog function, there is a directconnection from the external pin to the analog circuit, and a scan chain is inserted onthe interface between the digital logic and the analog circuitry.

Figure 116. Boundary-scan Cell for Bidirectional Port Pin with Pull-up Function.

D Q D Q

G

0

10

1

D Q D Q

G

0

10

1

0

1

0

1D Q D Q

G

0

1

Port Pin (PXn)

VccEXTESTTo Next CellShiftDR

Output Control (OC)

Pullup Enable (PUE)

Output Data (OD)

Input Data (ID)

From Last Cell UpdateDRClockDR

FF2 LD2

FF1 LD1

LD0FF0

226 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 117. General Port Pin Schematic Diagram(1)

Note: 1. See Boundary-scan descriptin for details.

Boundary-scan and the Two-wire Interface

The 2 Two-wire Interface pins SCL and SDA have one additional control signal in thescan-chain; Two-wire Interface Enable – TWIEN. As shown in Figure 118, the TWIENsignal enables a tri-state buffer with slew-rate control in parallel with the ordinary digitalport pins. A general scan cell as shown in Figure 122 is attached to the TWIEN signal.Notes: 1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordi-

nary scan support for digital port pins suffice for connectivity tests. The only reasonfor having TWIEN in the scan path, is to be able to disconnect the slew-rate controlbuffer when doing boundary-scan.

2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this willlead to drive contention.

CLK

RPx

RRx

WPx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WPx: WRITE PORTxRRx: READ PORTx REGISTERRPx: READ PORTx PIN

PUD: PULLUP DISABLE

CLK : I/O CLOCK

RDx: READ DDRx

D

L

Q

Q

RESET

RESET

Q

QD

Q

Q D

CLR

PORTxn

Q

Q D

CLR

DDxn

PINxn

DAT

A B

US

SLEEP

SLEEP: SLEEP CONTROL

Pxn

I/O

I/O

PUExn

OCxn

ODxn

IDxn

PUExn: PULLUP ENABLE for pin PxnOCxn: OUTPUT CONTROL for pin PxnODxn: OUTPUT DATA to pin PxnIDxn: INPUT DATA from pin Pxn

2272466E–AVR–10/02

Figure 118. Additional Scan Signal for the Two-wire Interface

Scanning the RESET Pin The RESET pin accepts 5V active low logic for standard reset operation, and 12V activehigh logic for High Voltage Parallel Programming. An observe-only cell as shown in Fig-ure 119 is inserted both for the 5V reset signal; RSTT, and the 12V reset signal;RSTHV.

Figure 119. Observe-only Cell

Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RCOscillator, External RC, External Clock, (High Frequency) Crystal Oscillator, Low Fre-quency Crystal Oscillator, and Ceramic Resonator.

Figure 120 shows how each Oscillator with external connection is supported in the scanchain. The Enable signal is supported with a general boundary-scan cell, while theOscillator/Clock output is attached to an observe-only cell. In addition to the main clock,the Timer Oscillator is scanned in the same way. The output from the internal RC Oscil-lator is not scanned, as this Oscillator does not have external connections.

Pxn

PUExn

ODxn

IDxn

TWIEN

OCxn

Slew-rate Limited

SRC

0

1D Q

FromPrevious

Cell

ClockDR

ShiftDR

ToNextCell

From System Pin To System Logic

FF1

228 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 120. Boundary-scan Cells for Oscillators and Clock Options

Table 89 summaries the scan registers for the external clock pin XTAL1, Oscillators withXTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator.

Notes: 1. Do not enable more than one clock source as main clock at a time.2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift

between the Internal Oscillator and the JTAG TCK clock. If possible, scanning anexternal clock is preferred.

3. The clock configuration is programmed by fuses. As a fuse is not changed run-time,the clock configuration is considered fixed for a given application. The user is advisedto scan the same clock option as to be used in the final system. The enable signalsare supported in the scan chain because the system logic can disable clock optionsin sleep modes, thereby disconnecting the Oscillator pins from the scan path if notprovided. The INTCAP fuses are not supported in the scan-chain, so the boundaryscan chain can not make a XTAL Oscillator requiring internal capacitors to run unlessthe fuse is correctly programmed.

Scanning the Analog Comparator

The relevant Comparator signals regarding Boundary-scan are shown in Figure 121.The Boundary-scan cell from Figure 122 is attached to each of these signals. The sig-nals are described in Table 90.

The Comparator need not be used for pure connectivity testing, since all analog inputsare shared with a digital port pin as well.

Table 89. Scan Signals for the Oscillators(1)(2)(3)

Enable Signal Scanned Clock Line Clock Option Scanned Clock Line when not Used

EXTCLKEN EXTCLK (XTAL1) External Clock 0

OSCON OSCCK External CrystalExternal Ceramic Resonator

0

RCOSCEN RCCK External RC 1

OSC32EN OSC32CK Low Freq. External Crystal 0

TOSKON TOSCK 32 kHz Timer Oscillator 0

0

1D Q

FromPrevious

Cell

ClockDR

ShiftDR

ToNextCell

To

Sys

tem

Log

ic

FF10

1D Q D Q

G

0

1

FromPrevious

Cell

ClockDR UpdateDR

ShiftDR

ToNextCell EXTEST

Fro

m D

igita

l Log

ic

XTAL1/TOSC1 XTAL2/TOSC2

Oscillator

ENABLE OUTPUT

2292466E–AVR–10/02

Figure 121. Analog Comparator

Figure 122. General Boundary-scan Cell used for Signals for Comparator and ADC

ACBG

BANDGAPREFERENCE


ACME

AC_IDLE

ACO

ADCEN

0

1D Q D Q

G

0

1

FromPrevious

Cell

ClockDR UpdateDR

ShiftDR

ToNextCell EXTEST

To Analog Circuitry/To Digital Logic

From Digital Logic/From Analog Ciruitry

230 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Scanning the ADC

Figure 123 shows a block diagram of the ADC with all relevant control and observe signals. The Boundary-scan cell fromFigure 122 is attached to each of these signals. The ADC need not be used for pure connectivity testing, since all analoginputs are shared with a digital port pin as well.

Figure 123. Analog to Digital Converter

The signals are described briefly in Table 91.

Table 90. Boundary-scan Signals for the Analog Comparator

Signal Name

Direction as Seen from the Comparator Description

Recommended Input when Not in Use

Output Values when Recommended Inputs are Used

AC_IDLE Input Turns off Analogcomparator when true

1 Depends upon µC code being executed

ACO Output Analog ComparatorOutput

Will become input to µC code being executed

0

ACME Input Uses output signal fromADC mux when true


ACBG Input Bandgap Referenceenable


10-bit DAC +

-

AREF

PRECH

DACOUT

COMP

MUXEN_7ADC_7

MUXEN_6ADC_6

MUXEN_5ADC_5

MUXEN_4ADC_4

MUXEN_3ADC_3

MUXEN_2ADC_2

MUXEN_1ADC_1

MUXEN_0ADC_0

NEGSEL_2ADC_2

NEGSEL_1ADC_1

NEGSEL_0ADC_0

EXTCH

+

-

+

-10x 20x

G10 G20

STACLK

AMPEN

2.56Vref

IREFEN

AREF

VCCREN

DAC_9..0

ADCEN

HOLD

PRECH

GNDEN

PASSEN

ACTEN

CO

MP

SCTESTADCBGEN

To Comparator

1.22Vref AREF

ADHSMADHSM

2312466E–AVR–10/02

Table 91. Boundary-scan Signals for the ADC

Signal Name

Direction as Seenfrom the ADC Description


Output Values when Recommended Inputs are used, and CPU is not Using the ADC

COMP Output Comparator Output 0 0

ACLK Input Clock signal to gain stages implemented as Switch-cap filters

0 0

ACTEN Input Enable path from gain stages to the comparator

0 0

ADHSM Input Increases speed of comparator at the sacrifice of higher power consumption

0 0

ADCBGEN Input Enable Band-gap reference as negative input to comparator

0 0

ADCEN Input Power-on signal to the ADC 0 0

AMPEN Input Power-on signal to the gain stages 0 0

DAC_9 Input Bit 9 of digital value to DAC 1 1










EXTCH Input Connect ADC channels 0 - 3 to by-pass path around gain stages

1 1

G10 Input Enable 10x gain 0 0

G20 Input Enable 20x gain 0 0

GNDEN Input Ground the negative input to comparator when true

0 0

HOLD Input Sample&Hold signal. Sample analog signal when low. Hold signal when high. If gain stages are used, this signal must go active when ACLK is high.

1 1

IREFEN Input Enables Band-gap reference as AREF signal to DAC

0 0

MUXEN_7 Input Input Mux bit 7 0 0



232 ATmega16(L) 2466E–AVR–10/02

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Note: Incorrect setting of the switches in Figure 123 will make signal contention and may damage the part. There are several inputchoices to the S&H circuitry on the negative input of the output comparator in Figure 123. Make sure only one path is selectedfrom either one ADC pin, Bandgap reference source, or Ground.






NEGSEL_2 Input Input Mux for negative input for differential signal, bit 2

0 0


0 0


0 0

PASSEN Input Enable pass-gate of gain stages. 1 1

PRECH Input Precharge output latch of comparator. (Active low)

1 1

SCTEST Input Switch-cap TEST enable. Output from x10 gain stage send out to Port Pin having ADC_4

0 0

ST Input Output of gain stages will settle faster if this signal is high first two ACLK periods after AMPEN goes high.

0 0

VCCREN Input Selects Vcc as the ACC reference voltage.

0 0

Table 91. Boundary-scan Signals for the ADC (Continued)

Signal Name

Direction as Seenfrom the ADC Description


Output Values when Recommended Inputs are used, and CPU is not Using the ADC

2332466E–AVR–10/02

If the ADC is not to be used during scan, the recommended input values from Table 91should be used. The user is recommended not to use the Differential Gain stages dur-ing scan. Switch-cap based gain stages require fast operation and accurate timingwhich is difficult to obtain when used in a scan chain. Details concerning operations ofthe differential gain stage is therefore not provided. For the same reason, the ADC HighSpeed mode (ADHSM) bit does not make any sense during Boundary-scan operation.

The AVR ADC is based on the analog circuitry shown in Figure 123 with a successiveapproximation algorithm implemented in the digital logic. When used in Boundary-scan,the problem is usually to ensure that an applied analog voltage is measured within somelimits. This can easily be done without running a successive approximation algorithm:apply the lower limit on the digital DAC[9:0] lines, make sure the output from the com-parator is low, then apply the upper limit on the digital DAC[9:0] lines, and verify theoutput from the comparator to be high.

The ADC need not be used for pure connectivity testing, since all analog inputs areshared with a digital port pin as well.

When using the ADC, remember the following:

• The Port Pin for the ADC channel in use must be configured to be an input with pull-up disabled to avoid signal contention.

• In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when enabling the ADC. The user is advised to wait at least 200 ns after enabling the ADC before controlling/observing any ADC signal, or perform a dummy conversion before using the first result.

• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low (Sample mode).

As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3when the power supply is 5.0V and AREF is externally connected to VCC.

The recommended values from Table 91 are used unless other values are given in thealgorithm in Table 92. Only the DAC and Port Pin values of the Scan-chain are shown.The column “Actions” describes what JTAG instruction to be used before filling theBoundary-scan register with the succeeding columns. The verification should be doneon the data scanned out when scanning in the data on the same row in the table.

The lower limit is: 1024 1.5V 0,95 5V⁄⋅ ⋅ 291 0x123= = The upper limit is: 1024 1.5V 1.05 5V⁄⋅ ⋅ 323 0x143= =

234 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clockfrequency. As the algorithm keeps HOLD high for five steps, the TCK clock frequencyhas to be at least five times the number of scan bits divided by the maximum hold time,thold,max.

Table 92. Algorithm for Using the ADC

Step Actions ADCEN DAC MUXEN HOLD PRECHPA3.Data

PA3.Control

PA3.Pullup_ Enable

1 SAMPLE_PRELOAD

1 0x200 0x08 1 1 0 0 0

2 EXTEST 1 0x200 0x08 0 1 0 0 0

3 1 0x200 0x08 1 1 0 0 0

4 1 0x123 0x08 1 1 0 0 0

5 1 0x123 0x08 1 0 0 0 0

6 Verify the COMP bit scanned out to be 0

1 0x200 0x08 1 1 0 0 0

7 1 0x200 0x08 0 1 0 0 0

8 1 0x200 0x08 1 1 0 0 0

9 1 0x143 0x08 1 1 0 0 0

10 1 0x143 0x08 1 0 0 0 0

11 Verify the COMP bit scanned out to be 1

1 0x200 0x08 1 1 0 0 0

2352466E–AVR–10/02

ATmega16 Boundary-scan Order

Table 93 shows the scan order between TDI and TDO when the Boundary-scan chain isselected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scannedout. The scan order follows the pin-out order as far as possible. Therefore, the bits ofPort A is scanned in the opposite bit order of the other ports. Exceptions from the rulesare the Scan chains for the analog circuits, which constitute the most significant bits ofthe scan chain regardless of which physical pin they are connected to. In Figure 116,PXn. Data corresponds to FF0, PXn. Control corresponds to FF1, and PXn.Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is not in the scan chain,since these pins constitute the TAP pins when the JTAG is enabled.

Table 93. ATmega16 Boundary-scan Order

Bit Number Signal Name Module

140 AC_IDLE Comparator

139 ACO

138 ACME

137 ACBG

136 COMP ADC

135 PRIVATE_SIGNAL1(Note:)

134 ACLK

133 ACTEN

132 ADHSM

131 ADCBGEN

130 ADCEN

129 AMPEN

128 DAC_9

127 DAC_8

126 DAC_7

125 DAC_6

124 DAC_5

123 DAC_4

122 DAC_3

121 DAC_2

120 DAC_1

119 DAC_0

118 EXTCH

117 G10

116 G20

115 GNDEN

114 HOLD

113 IREFEN

236 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

112 MUXEN_7 ADC

111 MUXEN_6

110 MUXEN_5

109 MUXEN_4

108 MUXEN_3

107 MUXEN_2

106 MUXEN_1

105 MUXEN_0

104 NEGSEL_2

103 NEGSEL_1

102 NEGSEL_0

101 PASSEN

100 PRECH

99 SCTEST

98 ST

97 VCCREN

96 PB0.Data Port B

95 PB0.Control

94 PB0.Pullup_Enable

93 PB1.Data

92 PB1.Control


90 PB2.Data

89 PB2.Control


87 PB3.Data

86 PB3.Control


84 PB4.Data

83 PB4.Control


Table 93. ATmega16 Boundary-scan Order (Continued)


2372466E–AVR–10/02

81 PB5.Data Port B

80 PB5.Control


78 PB6.Data

77 PB6.Control


75 PB7.Data

74 PB7.Control


72 RSTT Reset Logic (Observe-Only)71 RSTHV

70 EXTCLKEN Enable signals for main clock/Oscillators

69 OSCON

68 RCOSCEN

67 OSC32EN

66 EXTCLK (XTAL1) Clock input and Oscillators for the main clock(Observe-Only)65 OSCCK

64 RCCK

63 OSC32CK

62 TWIEN TWI

61 PD0.Data Port D

60 PD0.Control

59 PD0.Pullup_Enable

58 PD1.Data

57 PD1.Control


55 PD2.Data

54 PD2.Control


52 PD3.Data

51 PD3.Control


49 PD4.Data

48 PD4.Control




238 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

46 PD5.Data Port D

45 PD5.Control


43 PD6.Data

42 PD6.Control


40 PD7.Data

39 PD7.Control


37 PC0.Data Port C

36 PC0.Control

35 PC0.Pullup_Enable

34 PC1.Data

33 PC1.Control


31 PC6.Data

30 PC6.Control


28 PC7.Data

27 PC7.Control


25 TOSC 32 kHz Timer Oscillator

24 TOSCON

23 PA7.Data Port A

22 PA7.Control

21 PA7.Pullup_Enable

20 PA6.Data

19 PA6.Control


17 PA5.Data

16 PA5.Control


14 PA4.Data

13 PA4.Control




2392466E–AVR–10/02

Note: PRIVATE_SIGNAL1 should always be scanned in as zero.

Boundary-scan Description Language Files

Boundary-scan Description Language (BSDL) files describe Boundary-scan capabledevices in a standard format used by automated test-generation software. The orderand function of bits in the Boundary-scan data register are included in this description. ABSDL file for ATmega16 is available.

11 PA3.Data Port A

10 PA3.Control

9 PA3.Pullup_Enable

8 PA2.Data

7 PA2.Control

6 PA2.Pullup_Enable

5 PA1.Data

4 PA1.Control

3 PA1.Pullup_Enable

2 PA0.Data

1 PA0.Control

0 PA0.Pullup_Enable



240 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Boot Loader Support – Read-While-Write Self-Programming

The Boot Loader Support provides a real Read-While-Write Self-Programming mecha-nism for downloading and uploading program code by the MCU itself. This featureallows flexible application software updates controlled by the MCU using a Flash-resi-dent Boot Loader program. The Boot Loader program can use any available datainterface and associated protocol to read code and write (program) that code into theFlash memory, or read the code from the Program memory. The program code withinthe Boot Loader section has the capability to write into the entire Flash, including theBoot Loader memory. The Boot Loader can thus even modify itself, and it can alsoerase itself from the code if the feature is not needed anymore. The size of the BootLoader memory is configurable with Fuses and the Boot Loader has two separate setsof Boot Lock bits which can be set independently. This gives the user a unique flexibilityto select different levels of protection.

Features • Read-While-Write Self-Programming• Flexible Boot Memory size• High Security (Separate Boot Lock Bits for a Flexible Protection)• Separate Fuse to Select Reset Vector• Optimized Page(1) Size• Code Efficient Algorithm• Efficient Read-Modify-Write Support

Note: 1. A page is a section in the flash consisting of several bytes (see Table 110 on page 258) used during programming. The page organization does not affect normal operation.

Application and Boot Loader Flash Sections

The Flash memory is organized in two main sections, the Application section and theBoot Loader section (see Figure 125). The size of the different sections is configured bythe BOOTSZ Fuses as shown in Table 99 on page 252 and Figure 125. These two sec-tions can have different level of protection since they have different sets of Lock bits.

Application Section The Application section is the section of the Flash that is used for storing the applicationcode. The protection level for the application section can be selected by the ApplicationBoot Lock bits (Boot Lock bits 0), see Table 95 on page 244. The Application sectioncan never store any Boot Loader code since the SPM instruction is disabled when exe-cuted from the Application section.

BLS – Boot Loader Section While the Application section is used for storing the application code, the The BootLoader software must be located in the BLS since the SPM instruction can initiate a pro-gramming when executing from the BLS only. The SPM instruction can access theentire Flash, including the BLS itself. The protection level for the Boot Loader sectioncan be selected by the Boot Loader Lock bits (Boot Lock bits 1), see Table 96 on page244.

Read-While-Write and no Read-While-Write Flash Sections

Whether the CPU supports Read-While-Write or if the CPU is halted during a BootLoader software update is dependent on which address that is being programmed. Inaddition to the two sections that are configurable by the BOOTSZ Fuses as describedabove, the Flash is also divided into two fixed sections, the Read-While-Write (RWW)section and the No Read-While-Write (NRWW) section. The limit between the RWW-and NRWW sections is given in Table 100 on page 252 and Figure 125 on page 243.The main difference between the two sections is:

• When erasing or writing a page located inside the RWW section, the NRWW section can be read during the operation.

• When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire operation.

2412466E–AVR–10/02

Note that the user software can never read any code that is located inside the RWWsection during a Boot Loader software operation. The syntax “Read-While-Write sec-tion” refers to which section that is being programmed (erased or written), not whichsection that actually is being read during a Boot Loader software update.

RWW – Read-While-Write Section

If a Boot Loader software update is programming a page inside the RWW section, it ispossible to read code from the Flash, but only code that is located in the NRWW sec-tion. During an on-going programming, the software must ensure that the RWW sectionnever is being read. If the user software is trying to read code that is located inside theRWW section (i.e., by a call/jmp/lpm or an interrupt) during programming, the softwaremight end up in an unknown state. To avoid this, the interrupts should either be disabledor moved to the Boot Loader section. The Boot Loader section is always located in theNRWW section. The RWW Section Busy bit (RWWSB) in the Store Program MemoryControl Register (SPMCR) will be read as logical one as long as the RWW section isblocked for reading. After a programming is completed, the RWWSB must be cleared bysoftware before reading code located in the RWW section. See “Store Program MemoryControl Register – SPMCR” on page 245. for details on how to clear RWWSB.

NRWW – No Read-While-Write Section

The code located in the NRWW section can be read when the Boot Loader software isupdating a page in the RWW section. When the Boot Loader code updates the NRWWsection, the CPU is halted during the entire page erase or page write operation.

Figure 124. Read-While-Write vs. No Read-While-Write

Table 94. Read-While-Write Features

Which Section does the Z-pointer Address during the

Programming?

Which Section can be Read during

Programming?Is the CPU

Halted?

Read-While-Write

Supported?

RWW section NRWW section No Yes

NRWW section None Yes No

Read-While-Write(RWW) Section

No Read-While-Write (NRWW) Section

Z-pointerAddresses RWWSection

Z-pointerAddresses NRWWSection

CPU is Haltedduring the Operation

Code Located in NRWW SectionCan be Read duringthe Operation

242 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 125. Memory Sections(1)

Note: 1. The parameters in the figure above are given in Table 99 on page 252.

Boot Loader Lock Bits If no Boot Loader capability is needed, the entire Flash is available for application code.The Boot Loader has two separate sets of Boot Lock bits which can be set indepen-dently. This gives the user a unique flexibility to select different levels of protection.

The user can select:

• To protect the entire Flash from a software update by the MCU

• To protect only the Boot Loader Flash section from a software update by the MCU

• To protect only the Application Flash section from a software update by the MCU

• Allow software update in the entire Flash

See Table 95 and Table 96 for further details. The Boot Lock bits can be set in softwareand in Serial or Parallel Programming mode, but they can be cleared by a Chip Erasecommand only. The general Write Lock (Lock Bit mode 2) does not control the program-ming of the Flash memory by SPM instruction. Similarly, the general Read/Write Lock(Lock Bit mode 3) does not control reading nor writing by LPM/SPM, if it is attempted.

$0000

Flashend

Program MemoryBOOTSZ = '11'


Boot Loader Flash SectionFlashend


$0000




Boot Loader Flash Section

$0000

Flashend


Flashend

End RWW

Start NRWW

Application flash Section



End RWW

Start NRWW

End RWW

Start NRWW

$0000

End RWW, End Application

Start NRWW, Start Boot Loader

Application Flash SectionApplication Flash Section


Rea

d-W

hile

-Writ

e S

ectio

nN

o R

ead-

Whi

le-W

rite

Sec

tion

Rea

d-W

hile

-Writ

e S

ectio

nN

o R

ead-

Whi

le-W

rite

Sec

tion

Rea

d-W

hile

-Writ

e S

ectio

nN

o R

ead-

Whi

le-W

rite

Sec

tion

Rea

d-W

hile

-Writ

e S

ectio

nN

o R

ead-

Whi

le-W

rite

Sec

tion

End Application

Start Boot Loader

End Application

Start Boot Loader

End Application

Start Boot Loader

2432466E–AVR–10/02

Note: 1. “1” means unprogrammed, “0” means programmed


Entering the Boot Loader Program

Entering the Boot Loader takes place by a jump or call from the application program.This may be initiated by a trigger such as a command received via USART, or SPI inter-face. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector ispointing to the Boot Flash start address after a reset. In this case, the Boot Loader isstarted after a reset. After the application code is loaded, the program can start execut-ing the application code. Note that the fuses cannot be changed by the MCU itself. Thismeans that once the Boot Reset Fuse is programmed, the Reset Vector will alwayspoint to the Boot Loader Reset and the fuse can only be changed through the serial orparallel programming interface.

Table 95. Boot Lock Bit0 Protection Modes (Application Section)(1)

BLB0 Mode BLB02 BLB01 Protection

1 1 1No restrictions for SPM or LPM accessing the Application section.

2 1 0 SPM is not allowed to write to the Application section.

3 0 0

SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If interrupt vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.

4 0 1

LPM executing from the Boot Loader section is not allowed to read from the Application section. If interrupt vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.

Table 96. Boot Lock Bit1 Protection Modes (Boot Loader Section)(1)

BLB1 mode BLB12 BLB11 Protection

1 1 1No restrictions for SPM or LPM accessing the Boot Loader section.

2 1 0 SPM is not allowed to write to the Boot Loader section.

3 0 0

SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If interrupt vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.

4 0 1

LPM executing from the Application section is not allowed to read from the Boot Loader section. If interrupt vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.

244 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)


Store Program Memory Control Register – SPMCR

The Store Program Memory Control Register contains the control bits needed to controlthe Boot Loader operations.

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), theSPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as longas the SPMEN bit in the SPMCR Register is cleared.

• Bit 6 – RWWSB: Read-While-Write Section Busy

When a self-programming (Page Erase or Page Write) operation to the RWW section isinitiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, theRWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bitis written to one after a Self-Programming operation is completed. Alternatively theRWWSB bit will automatically be cleared if a page load operation is initiated.


This bit is a reserved bit in the ATmega16 and always read as zero.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

When programming (Page Erase or Page Write) to the RWW section, the RWW sectionis blocked for reading (the RWWSB will be set by hardware). To re-enable the RWWsection, the user software must wait until the programming is completed (SPMEN will becleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, thenext SPM instruction within four clock cycles re-enables the RWW section. The RWWsection cannot be re-enabled while the Flash is busy with a page erase or a page write(SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flashload operation will abort and the data loaded will be lost.

• Bit 3 – BLBSET: Boot Lock Bit Set

If this bit is written to one at the same time as SPMEN, the next SPM instruction withinfour clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 andthe address in the Z-pointer are ignored. The BLBSET bit will automatically be clearedupon completion of the Lock bit set, or if no SPM instruction is executed within four clockcycles.

An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCRRegister, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See “Reading the Fuse and Lock Bits from Soft-ware” on page 249 for details.

Table 97. Boot Reset Fuse(1)

BOOTRST Reset Address

1 Reset Vector = Application reset (address $0000)

0 Reset Vector = Boot Loader reset (see Table 99 on page 252)

Bit 7 6 5 4 3 2 1 0

SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN SPMCR

Read/Write R/W R R R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

2452466E–AVR–10/02

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SPMEN, the next SPM instruction withinfour clock cycles executes Page Write, with the data stored in the temporary buffer. Thepage address is taken from the high part of the Z-pointer. The data in R1 and R0 areignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPMinstruction is executed within four clock cycles. The CPU is halted during the entire pagewrite operation if the NRWW section is addressed.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SPMEN, the next SPM instruction withinfour clock cycles executes Page Erase. The page address is taken from the high part ofthe Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear uponcompletion of a page erase, or if no SPM instruction is executed within four clock cycles.The CPU is halted during the entire page write operation if the NRWW section isaddressed.

• Bit 0 – SPMEN: Store Program Memory Enable

This bit enables the SPM instruction for the next four clock cycles. If written to onetogether with either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPMinstruction will have a special meaning, see description above. If only SPMEN is written,the following SPM instruction will store the value in R1:R0 in the temporary page bufferaddressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit willauto-clear upon completion of an SPM instruction, or if no SPM instruction is executedwithin four clock cycles. During page erase and page write, the SPMEN bit remains highuntil the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in thelower five bits will have no effect.

Addressing the Flash during Self-Programming

The Z-pointer is used to address the SPM commands.

Since the Flash is organized in pages (see Table 110 on page 258), the programcounter can be treated as having two different sections. One section, consisting of theleast significant bits, is addressing the words within a page, while the most significantbits are addressing the pages. This is shown in Figure 126. Note that the Page Eraseand Page Write operations are addressed independently. Therefore it is of major impor-tance that the Boot Loader software addresses the same page in both the Page Eraseand Page Write operation. Once a programming operation is initiated, the address islatched and the Z-pointer can be used for other operations.

The only SPM operation that does not use the Z-pointer is Setting the Boot Loader Lockbits. The content of the Z-pointer is ignored and will have no effect on the operation. TheLPM instruction does also use the Z pointer to store the address. Since this instructionaddresses the Flash byte by byte, also the LSB (bit Z0) of the Z-pointer is used.

Bit 15 14 13 12 11 10 9 8

ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8

ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0

7 6 5 4 3 2 1 0

246 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 126. Addressing the Flash during SPM(1)

Note: 1. The different variables used in Figure 126 are listed in Table 101 on page 252.

Self-Programming the Flash

The program memory is updated in a page by page fashion. Before programming apage with the data stored in the temporary page buffer, the page must be erased. Thetemporary page buffer is filled one word at a time using SPM and the buffer can be filledeither before the page erase command or between a page erase and a page writeoperation:

Alternative 1, fill the buffer before a Page Erase

• Fill temporary page buffer

• Perform a Page Erase

• Perform a Page Write

Alternative 2, fill the buffer after Page Erase

• Perform a Page Erase

• Fill temporary page buffer

• Perform a Page Write

If only a part of the page needs to be changed, the rest of the page must be stored (forexample in the temporary page buffer) before the erase, and then be rewritten. Whenusing alternative 1, the Boot Loader provides an effective Read-Modify-Write featurewhich allows the user software to first read the page, do the necessary changes, andthen write back the modified data. If alternative 2 is used, it is not possible to read theold data while loading since the page is already erased. The temporary page buffer canbe accessed in a random sequence. It is essential that the page address used in boththe page erase and page write operation is addressing the same page. See “SimpleAssembly Code Example for a Boot Loader” on page 250 for an assembly codeexample.

PROGRAM MEMORY

0115

Z - REGISTER

BIT

0

ZPAGEMSB

WORD ADDRESSWITHIN A PAGE

PAGE ADDRESSWITHIN THE FLASH

ZPCMSB

INSTRUCTION WORD

PAGE PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

PAGE

PCWORDPCPAGE

PCMSB PAGEMSBPROGRAMCOUNTER

2472466E–AVR–10/02

Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “X0000011” toSPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1and R0 is ignored. The page address must be written to PCPAGE in the Z-register.Other bits in the Z-pointer must be written zero during this operation.

• Page Erase to the RWW section: The NRWW section can be read during the page erase.

• Page Erase to the NRWW section: The CPU is halted during the operation.

Filling the Temporary Buffer (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write“00000001” to SPMCR and execute SPM within four clock cycles after writing SPMCR.The content of PCWORD in the Z-register is used to address the data in the temporarybuffer. The temporary buffer will auto-erase after a page write operation or by writing theRWWSRE bit in SPMCR. It is also erased after a system reset. Note that it is not possi-ble to write more than one time to each address without erasing the temporary buffer.

Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “X0000101” toSPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written zero during this operation.

• Page Write to the RWW section: The NRWW section can be read during the Page Write.

• Page Write to the NRWW section: The CPU is halted during the operation.

Using the SPM Interrupt If the SPM interrupt is enabled, the SPM interrupt will generate a constant interruptwhen the SPMEN bit in SPMCR is cleared. This means that the interrupt can be usedinstead of polling the SPMCR Register in software. When using the SPM interrupt, theInterrupt Vectors should be moved to the BLS section to avoid that an interrupt isaccessing the RWW section when it is blocked for reading. How to move the interruptsis described in “Interrupts” on page 42.

Consideration while Updating BLS

Special care must be taken if the user allows the Boot Loader section to be updated byleaving Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself cancorrupt the entire Boot Loader, and further software updates might be impossible. If it isnot necessary to change the Boot Loader software itself, it is recommended to programthe Boot Lock bit11 to protect the Boot Loader software from any internal softwarechanges.

Prevent Reading the RWW Section during Self-Programming

During Self-Programming (either Page Erase or Page Write), the RWW section isalways blocked for reading. The user software itself must prevent that this section isaddressed during the Self-Programming operation. The RWWSB in the SPMCR will beset as long as the RWW section is busy. During self-programming the Interrupt Vectortable should be moved to the BLS as described in “Interrupts” on page 42, or the inter-rupts must be disabled. Before addressing the RWW section after the programming iscompleted, the user software must clear the RWWSB by writing the RWWSRE. See“Simple Assembly Code Example for a Boot Loader” on page 250 for an example.

Setting the Boot Loader Lock Bits by SPM

To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” toSPMCR and execute SPM within four clock cycles after writing SPMCR. The onlyaccessible Lock bits are the Boot Lock bits that may prevent the Application and BootLoader section from any software update by the MCU.

Bit 7 6 5 4 3 2 1 0

R0 1 1 BLB12 BLB11 BLB02 BLB01 1 1

248 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

See Table 95 and Table 96 for how the different settings of the Boot Loader bits affectthe Flash access.

If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmedif an SPM instruction is executed within four cycles after BLBSET and SPMEN are set inSPMCR. The Z-pointer is don’t care during this operation, but for future compatibility it isrecommended to load the Z-pointer with $0001 (same as used for reading the Lockbits). For future compatibility It is also recommended to set bits 7, 6, 1, and 0 in R0 to “1”when writing the Lock bits. When programming the Lock bits the entire Flash can beread during the operation.

EEPROM Write Prevents Writing to SPMCR

Note that an EEPROM write operation will block all software programming to Flash.Reading the Fuses and Lock bits from software will also be prevented during theEEPROM write operation. It is recommended that the user checks the status bit (EEWE)in the EECR register and verifies that the bit is cleared before writing to the SPMCRregister.

Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,load the Z-pointer with $0001 and set the BLBSET and SPMEN bits in SPMCR. Whenan LPM instruction is executed within three CPU cycles after the BLBSET and SPMENbits are set in SPMCR, the value of the Lock bits will be loaded in the destination regis-ter. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lockbits or if no LPM instruction is executed within three CPU cycles or no SPM instruction isexecuted within four CPU cycles. When BLBSET and SPMEN are cleared, LPM willwork as described in the Instruction set Manual.

The algorithm for reading the Fuse Low bits is similar to the one described above forreading the Lock bits. To read the Fuse Low bits, load the Z-pointer with $0000 and setthe BLBSET and SPMEN bits in SPMCR. When an LPM instruction is executed withinthree cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of theFuse Low bits (FLB) will be loaded in the destination register as shown below. Refer toTable 105 on page 256 for a detailed description and mapping of the Fuse Low bits.

Similarly, when reading the Fuse High bits, load $0003 in the Z-pointer. When an LPMinstruction is executed within three cycles after the BLBSET and SPMEN bits are set inthe SPMCR, the value of the Fuse High bits (FHB) will be loaded in the destination reg-ister as shown below. Refer to Table 104 on page 255 for detailed description andmapping of the Fuse High bits.

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits thatare unprogrammed, will be read as one.

Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply volt-age is too low for the CPU and the Flash to operate properly. These issues are the sameas for board level systems using the Flash, and the same design solutions should beapplied.

A Flash program corruption can be caused by two situations when the voltage is too low.First, a regular write sequence to the Flash requires a minimum voltage to operate

Bit 7 6 5 4 3 2 1 0

Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1

Bit 7 6 5 4 3 2 1 0

Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0

Bit 7 6 5 4 3 2 1 0

Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0

2492466E–AVR–10/02

correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supplyvoltage for executing instructions is too low.

Flash corruption can easily be avoided by following these design recommendations (oneis sufficient):

1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent any Boot Loader software updates.

2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC Reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

3. Keep the AVR core in Power-down Sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effec-tively protecting the SPMCR register and thus the Flash from unintentional writes.

Programming Time for Flash when using SPM

The Calibrated RC Oscillator is used to time Flash accesses. Table 98 shows the typicalprogramming time for Flash accesses from the CPU.

Simple Assembly Code Example for a Boot Loader

;-the routine writes one page of data from RAM to Flash; the first data location in RAM is pointed to by the Y pointer; the first data location in Flash is pointed to by the Z pointer;-error handling is not included;-the routine must be placed inside the boot space; (at least the Do_spm sub routine). Only code inside NRWW section can; be read during self-programming (page erase and page write).;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20); storing and restoring of registers is not included in the routine; register usage can be optimized at the expense of code size;-It is assumed that either the interrupt table is moved to the Boot; loader section or that the interrupts are disabled.

.equ PAGESIZEB = PAGESIZE*2 ; PAGESIZEB is page size in BYTES, not; words

.org SMALLBOOTSTARTWrite_page:; page eraseldi spmcrval, (1<<PGERS) | (1<<SPMEN)call Do_spm

; re-enable the RWW sectionldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)call Do_spm

; transfer data from RAM to Flash page bufferldi looplo, low(PAGESIZEB) ;init loop variableldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

Wrloop:ld r0, Y+ld r1, Y+ldi spmcrval, (1<<SPMEN)

Table 98. SPM Programming Time.

Symbol Min Programming Time Max Programming Time

Flash write (Page Erase, Page Write, and write Lock bits by SPM)

3.7 ms 4.5 ms

250 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

call Do_spmadiw ZH:ZL, 2sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256brne Wrloop

; execute page writesubi ZL, low(PAGESIZEB) ;restore pointersbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256ldi spmcrval, (1<<PGWRT) | (1<<SPMEN)call Do_spm

; re-enable the RWW sectionldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)call Do_spm

; read back and check, optionalldi looplo, low(PAGESIZEB) ;init loop variableldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256subi YL, low(PAGESIZEB) ;restore pointersbci YH, high(PAGESIZEB)

Rdloop:lpm r0, Z+ld r1, Y+cpse r0, r1jmp Errorsbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256brne Rdloop

; return to RWW section; verify that RWW section is safe to read

Return:in temp1, SPMCRsbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not

; ready yetret; re-enable the RWW sectionldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)call Do_spmrjmp Return

Do_spm:; check for previous SPM complete

Wait_spm:in temp1, SPMCRsbrc temp1, SPMENrjmp Wait_spm; input: spmcrval determines SPM action; disable interrupts if enabled, store statusin temp2, SREGcli; check that no EEPROM write access is present

Wait_ee:sbic EECR, EEWErjmp Wait_ee; SPM timed sequenceout SPMCR, spmcrvalspm; restore SREG (to enable interrupts if originally enabled)out SREG, temp2ret

2512466E–AVR–10/02

ATmega16 Boot Loader Parameters

In Table 99 through Table 101, the parameters used in the description of the self pro-gramming are given.

Note: 1. The different BOOTSZ Fuse configurations are shown in Figure 125

Note: 1. For details about these two section, see “NRWW – No Read-While-Write Section” onpage 242 and “RWW – Read-While-Write Section” on page 242

Note: 1. Z15:Z14: always ignoredZ0: should be zero for all SPM commands, byte select for the LPM instruction.

Table 99. Boot Size Configuration(1)

BOOTSZ1 BOOTSZ0Boot Size Pages



End Application section

Boot Reset Address (start Boot Loader Section)

1 1128 words

2$0000 - $1F7F

$1F80 - $1FFF

$1F7F $1F80

1 0256 words

4$0000 - $1EFF

$1F00 - $1FFF

$1EFF $1F00

0 1512 words

8$0000 - $1DFF

$1E00 - $1FFF

$1DFF $1E00

0 01024 words

16$0000 - $1BFF

$1C00 - $1FFF

$1BFF $1C00

Table 100. Read-While-Write Limit(1)

Section Pages Address

Read-While-Write section (RWW) 112 $0000 - $1BFF

No Read-While-Write section (NRWW) 16 $1C00 - $1FFF

Table 101. Explanation of Different Variables used in Figure 126 and the Mapping tothe Z-pointer

VariableCorresponding

Z-value(1) Description

PCMSB12 Most significant bit in the Program Counter.

(The Program Counter is 13 bits PC[12:0])

PAGEMSB5 Most significant bit which is used to address the

words within one page (64 words in a page requires 6 bits PC [5:0]).

ZPCMSBZ13 Bit in Z-register that is mapped to PCMSB.

Because Z0 is not used, the ZPCMSB equals PCMSB + 1.

ZPAGEMSBZ6 Bit in Z-register that is mapped to PAGEMSB.

Because Z0 is not used, the ZPAGEMSB equals PAGEMSB + 1.

PCPAGEPC[12:6] Z13:Z7 Program Counter page address: Page select,

for Page Erase and Page Write

PCWORDPC[5:0] Z6:Z1 Program Counter word address: Word select,

for filling temporary buffer (must be zero during page write operation)

252 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

See “Addressing the Flash during Self-Programming” on page 246 for details aboutthe use of Z-pointer during Self-Programming.

2532466E–AVR–10/02

Memory Programming

Program And Data Memory Lock Bits

The ATmega16 provides six Lock bits which can be left unprogrammed (“1”) or can beprogrammed (“0”) to obtain the additional features listed in Table 103. The Lock bits canonly be erased to “1” with the Chip Erase command.


Table 102. Lock Bit Byte(1)

Lock Bit Byte Bit No. Description Default Value

7 – 1 (unprogrammed)

6 – 1 (unprogrammed)

BLB12 5 Boot Lock bit 1 (unprogrammed)




LB2 1 Lock bit 1 (unprogrammed)

LB1 0 Lock bit 1 (unprogrammed)

Table 103. Lock Bit Protection Modes

Memory Lock Bits(2) Protection Type

LB Mode LB2 LB1

1 1 1 No memory lock features enabled.

2 1 0

Further programming of the Flash and EEPROM is disabled in Parallel and SPI/JTAG Serial Programming mode. The Fuse bits are locked in both Serial and Parallel Programming mode.(1)

3 0 0

Further programming and verification of the Flash and EEPROM is disabled in Parallel and SPI/JTAG Serial Programming mode. The Fuse bits are locked in both Serial and Parallel Programming mode.(1)

BLB0 Mode BLB02 BLB01

1 1 1No restrictions for SPM or LPM accessing the Application section.

2 1 0 SPM is not allowed to write to the Application section.

3 0 0

SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If interrupt vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.

4 0 1

LPM executing from the Boot Loader section is not allowed to read from the Application section. If interrupt vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.

BLB1 Mode BLB12 BLB11

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ATmega16(L)

Notes: 1. Program the fuse bits before programming the Lock bits.2. “1” means unprogrammed, “0” means programmed

Fuse Bits The ATmega16 has two fuse bytes. Table 104 and Table 105 describe briefly the func-tionality of all the fuses and how they are mapped into the fuse bytes. Note that thefuses are read as logical zero, “0”, if they are programmed.

Notes: 1. The SPIEN Fuse is not accessible in SPI Serial Programming mode.2. The CKOPT Fuse functionality depends on the setting of the CKSEL bits. See See

“Clock Sources” on page 23. for details.3. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 99 on

page 252.4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of

Lock bits and the JTAGEN Fuse. A programmed OCDEN Fuse enables some partsof the clock system to be running in all sleep modes. This may increase the powerconsumption.

1 1 1No restrictions for SPM or LPM accessing the Boot Loader section.

2 1 0 SPM is not allowed to write to the Boot Loader section.

3 0 0

SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If interrupt vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.

4 0 1

LPM executing from the Application section is not allowed to read from the Boot Loader section. If interrupt vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.

Table 103. Lock Bit Protection Modes (Continued)

Memory Lock Bits(2) Protection Type

Table 104. Fuse High Byte

Fuse High Byte

Bit No. Description Default Value

OCDEN(4) 7 Enable OCD 1 (unprogrammed, OCD disabled)

JTAGEN 6 Enable JTAG 0 (programmed, JTAG enabled)

SPIEN(1) 5Enable SPI Serial Program and Data Downloading

0 (programmed, SPI prog. enabled)

CKOPT(2) 4 Oscillator options 1 (unprogrammed)

EESAVE 3EEPROM memory is preserved through the Chip Erase

1 (unprogrammed, EEPROM not preserved)

BOOTSZ1 2Select Boot Size (see Table 99 for details) 0 (programmed)(3)

BOOTSZ0 1Select Boot Size (see Table 99 for details) 0 (programmed)(3)

BOOTRST 0 Select reset vector 1 (unprogrammed)

2552466E–AVR–10/02

Notes: 1. The default value of SUT1..0 results in maximum start-up time. SeeTable 10 on page28 for details.

2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 1MHz. SeeTable 2 on page 23 for details.

The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits arelocked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming theLock bits.

Latching of Fuses The Fuse values are latched when the device enters programming mode and changesof the Fuse values will have no effect until the part leaves Programming mode. Thisdoes not apply to the EESAVE Fuse which will take effect once it is programmed. Thefuses are also latched on Power-up in Normal mode.

Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.This code can be read in both serial and parallel mode, also when the device is locked.The three bytes reside in a separate address space.

For the ATmega16 the signature bytes are:

1. $000: $1E (indicates manufactured by Atmel)

2. $001: $94 (indicates 16KB Flash memory)

3. $002: $03 (indicates ATmega16 device when $001 is $94)

Calibration Byte The ATmega16 has a byte calibration value for the internal RC Oscillator. This byteresides in the high byte of address $000 in the signature address space. During reset,this byte is automatically written into the OSCCAL register to ensure correct frequencyof the calibrated RC Oscillator.

Table 105. Fuse Low Byte

Fuse Low Byte

Bit No. Description Default Value

BODLEVEL 7 Brown-out Detector trigger level 1 (unprogrammed)

BODEN 6 Brown-out Detector enable 1 (unprogrammed, BOD disabled)

SUT1 5 Select start-up time 1 (unprogrammed)(1)

SUT0 4 Select start-up time 0 (programmed)(1)

CKSEL3 3 Select Clock source 0 (programmed)(2)



CKSEL0 0 Select Clock source 1 (unprogrammed)(2)

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ATmega16(L)

Parallel Programming Parameters, Pin Mapping, and Commands

This section describes how to parallel program and verify Flash Program memory,EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega16. Pulses areassumed to be at least 250 ns unless otherwise noted.

Signal Names In this section, some pins of the ATmega16 are referenced by signal names describingtheir functionality during parallel programming, see Figure 127 and Table 106. Pins notdescribed in the following table are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a posi-tive pulse. The bit coding is shown in Table 108.

When pulsing WR or OE, the command loaded determines the action executed. The dif-ferent Commands are shown in Table 109.

Figure 127. Parallel Programming

Table 106. Pin Name Mapping

Signal Name in Programming Mode Pin Name I/O Function

RDY/BSY PD1 O0: Device is busy programming, 1: Device is ready for new command

OE PD2 I Output Enable (Active low)

WR PD3 I Write Pulse (Active low)

BS1 PD4 IByte Select 1 (“0” selects low byte, “1” selects high byte)

XA0 PD5 I XTAL Action Bit 0

XA1 PD6 I XTAL Action Bit 1

VCC

+5V

GND

XTAL1

PD1

PD2

PD3

PD4

PD5

PD6

PB7 - PB0 DATA

RESET

PD7

+12 V

BS1

XA0

XA1

OE

RDY/BSY

PAGEL

PA0

WR

BS2

AVCC

+5V

2572466E–AVR–10/02

PAGEL PD7 I Program Memory and EEPROM data Page Load

BS2 PA0 IByte Select 2 (“0” selects low byte, “1” selects 2’nd high byte)

DATA PB7-0 I/O Bidirectional Data bus (Output when OE is low)

Table 107. Pin Values used to Enter Programming Mode

Pin Symbol Value

PAGEL Prog_enable[3] 0

XA1 Prog_enable[2] 0

XA0 Prog_enable[1] 0

BS1 Prog_enable[0] 0

Table 108. XA1 and XA0 Coding

XA1 XA0 Action when XTAL1 is Pulsed

0 0Load Flash or EEPROM Address (High or low address byte determined by BS1)

0 1 Load Data (High or Low data byte for Flash determined by BS1)

1 0 Load Command

1 1 No Action, Idle

Table 109. Command Byte Bit Coding

Command Byte Command Executed

1000 0000 Chip Erase

0100 0000 Write Fuse Bits

0010 0000 Write Lock Bits

0001 0000 Write Flash

0001 0001 Write EEPROM

0000 1000 Read Signature Bytes and Calibration byte

0000 0100 Read Fuse and Lock bits

0000 0010 Read Flash

0000 0011 Read EEPROM

Table 110. No. of Words in a Page and no. of Pages in the Flash

Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB

8K words (16K bytes) 64 words PC[5:0] 128 PC[12:6] 12

Table 106. Pin Name Mapping (Continued)

Signal Name in Programming Mode Pin Name I/O Function

258 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Parallel Programming

Enter Programming Mode The following algorithm puts the device in Parallel Programming mode:

1. Apply 4.5 - 5.5V between VCC and GND, and wait at least 100 µs.

2. Set RESET to “0” and toggle XTAL1 at least 6 times

3. Set the Prog_enable pins listed in Table 107 on page 258 to “0000” and wait at least 100 ns.

4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V has been applied to RESET, will cause the device to fail entering Pro-gramming mode.

Note, if External Crystal or External RC configuration is selected, it may not be possibleto apply qualified XTAL1 pulses. In such cases, the following algorithm should befollowed:

1. Set Prog_enable pins listed in Table 107 on page 258 to “0000”.

2. Apply 4.5 - 5.5V between VCC and GND simultanously as 11.5 - 12.5V is applied to RESET.

3. Wait 100 µs.

4. Re-program the fuses to ensure that External Clock is selected as clock source (CKSEL3:0 = 0b0000) If Lock bits are programmed, a Chip Erase command must be executed before changing the fuses.

5. Exit Programming mode by power the device down or by bringing RESET pin to 0b0.

6. Entering Programming mode with the original algorithm, as described above.

Considerations for Efficient Programming

The loaded command and address are retained in the device during programming. Forefficient programming, the following should be considered.

• The command needs only be loaded once when writing or reading multiple memory locations.

• Skip writing the data value $FF, that is the contents of the entire EEPROM (unless the EESAVE fuse is programmed) and Flash after a Chip Erase.

• Address high byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading.

Table 111. No. of Words in a Page and no. of Pages in the EEPROM

EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB

512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8

2592466E–AVR–10/02

Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lockbits are not reset until the program memory has been completely erased. The Fuse bitsare not changed. A Chip Erase must be performed before the Flash and/or theEEPROM are reprogrammed.

Note: 1. The EEPRPOM memory is preserved during chip erase if the EESAVE Fuse isprogrammed.

Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.

6. Wait until RDY/BSY goes high before loading a new command.

Programming the Flash The Flash is organized in pages, see Table 110 on page 258. When programming theFlash, the program data is latched into a page buffer. This allows one page of programdata to be programmed simultaneously. The following procedure describes how to pro-gram the entire Flash memory:

A. Load Command “Write Flash”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “0001 0000”. This is the command for Write Flash.

4. Give XTAL1 a positive pulse. This loads the command.

B. Load Address Low byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “0”. This selects low address.

3. Set DATA = Address low byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the address low byte.

C. Load Data Low Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data low byte ($00 - $FF).

3. Give XTAL1 a positive pulse. This loads the data byte.

D. Load Data High Byte

1. Set BS1 to “1”. This selects high data byte.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data high byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the data byte.

E. Latch Data

1. Set BS1 to “1”. This selects high data byte.

2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 129 for signal waveforms)

F. Repeat B through E until the entire buffer is filled or until all data within the page isloaded.

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ATmega16(L)

While the lower bits in the address are mapped to words within the page, the higher bitsaddress the pages within the FLASH. This is illustrated in Figure 128 on page 261. Notethat if less than 8 bits are required to address words in the page (pagesize < 256), themost significant bit(s) in the address low byte are used to address the page when per-forming a page write.

G. Load Address High byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “1”. This selects high address.

3. Set DATA = Address high byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the address high byte.

H. Program Page

1. Set BS1 = “0”

2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSYgoes low.

3. Wait until RDY/BSY goes high. (See Figure 129 for signal waveforms)

I. Repeat B through H until the entire Flash is programmed or until all data has beenprogrammed.

J. End Page Programming

1. 1. Set XA1, XA0 to “10”. This enables command loading.

2. Set DATA to “0000 0000”. This is the command for No Operation.

3. Give XTAL1 a positive pulse. This loads the command, and the internal write sig-nals are reset.

Figure 128. Addressing the Flash which is Organized in Pages

Note: 1. PCPAGE and PCWORD are listed in Table 110 on page 258.

PROGRAM MEMORY

WORD ADDRESSWITHIN A PAGE

PAGE ADDRESSWITHIN THE FLASH

INSTRUCTION WORD

PAGE PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

PAGE

PCWORDPCPAGE

PCMSB PAGEMSBPROGRAMCOUNTER

2612466E–AVR–10/02

Figure 129. Programming the Flash Waveforms(1)

Note: 1. “XX” is don’t care. The letters refer to the programming description above.

RDY/BSY

WR

OE

RESET +12V

PAGEL

BS2

$10 ADDR. LOW ADDR. HIGHDATADATA LOW DATA HIGH ADDR. LOW DATA LOW DATA HIGH

XA1

XA0

BS1

XTAL1

XX XX XX

A B C D E B C D E G H

F

262 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Programming the EEPROM The EEPROM is organized in pages, see Table 111 on page 259. When programmingthe EEPROM, the program data is latched into a page buffer. This allows one page ofdata to be programmed simultaneously. The programming algorithm for the EEPROMdata memory is as follows (refer to “Programming the Flash” on page 260 for details onCommand, Address and Data loading):

1. A: Load Command “0001 0001”.

2. G: Load Address High Byte ($00 - $FF)

3. B: Load Address Low Byte ($00 - $FF)

4. C: Load Data ($00 - $FF)

5. E: Latch data (give PAGEL a positive pulse)

K: Repeat 3 through 5 until the entire buffer is filled

L: Program EEPROM page

1. Set BS1 to “0”.

2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low.

3. Wait until to RDY/BSY goes high before programming the next page. (See Fig-ure 130 for signal waveforms)

Figure 130. Programming the EEPROM Waveforms

Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming theFlash” on page 260 for details on Command and Address loading):

1. A: Load Command “0000 0010”.



4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.

RDY/BSY

WR

OE

RESET +12V

PAGEL

BS2

0x11 ADDR. HIGHDATA

ADDR. LOW DATA ADDR. LOW DATA XX

XA1

XA0

BS1

XTAL1

XX

A G B C E B C E L

K

2632466E–AVR–10/02

5. Set BS1 to “1”. The Flash word high byte can now be read at DATA.

6. Set OE to “1”.

Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming theFlash” on page 260 for details on Command and Address loading):

1. A: Load Command “0000 0011”.



4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.


Programming the Fuse Low Bits

The algorithm for programming the Fuse Low bits is as follows (refer to “Programmingthe Flash” on page 260 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “0” and BS2 to “0”.

4. Give WR a negative pulse and wait for RDY/BSY to go high.

Programming the Fuse High Bits

The algorithm for programming the Fuse high bits is as follows (refer to “Programmingthe Flash” on page 260 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “1” and BS2 to “0”. This selects high data byte.


5. Set BS1 to “0”. This selects low data byte.

Figure 131. Programming the Fuses

RDY/BSY

WR

OE

RESET +12V

PAGEL

$40DATA

DATA XX

XA1

XA0

BS1

XTAL1

A C

$40 DATA XX

A C

Write Fuse Low byte Write Fuse high byte

BS2

264 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming theFlash” on page 260 for details on Command and Data loading):

1. A: Load Command “0010 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit.


The Lock bits can only be cleared by executing Chip Erase.

Reading the Fuse and Lock Bits

The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programmingthe Flash” on page 260 for details on Command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed).

3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be read at DATA (“0” means programmed).

4. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read at DATA (“0” means programmed).


Figure 132. Mapping between BS1, BS2 and the Fuse- and Lock Bits during Read

Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming theFlash” on page 260 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte ($00 - $02).

3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.


Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to “Programming theFlash” on page 260 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte, $00.

3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.


Fuse Low Byte

Lock Bits 0

1

BS2

Fuse High Byte

0

1

BS1

DATA

2652466E–AVR–10/02

Parallel Programming Characteristics

Figure 133. Parallel Programming Timing, Including some General TimingRequirements

Figure 134. Parallel Programming Timing, Loading Sequence with TimingRequirements(1)

Note: 1. The timing requirements shown in Figure 133 (i.e., tDVXH, tXHXL, and tXLDX) also applyto loading operation.

Data & Contol(DATA, XA0/1, BS1, BS2)

XTAL1tXHXL

tWL WH

tDVXH tXLDX

tPLWL

tWLRH

WR

RDY/BSY

PAGEL tPHPL

tPLBXtBVPH

tXLWL

tWLBXt BVWL

WLRL

XTAL1

PAGEL

tPLXHXLXHt tXLPH

ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)DATA

BS1

XA0

XA1

LOAD ADDRESS(LOW BYTE)

LOAD DATA (LOW BYTE)

LOAD DATA(HIGH BYTE)

LOAD DATA LOAD ADDRESS(LOW BYTE)

266 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 135. Parallel Programming Timing, Reading Sequence (within the Same Page)with Timing Requirements(1)

Note: 1. The timing requirements shown in Figure 133 (i.e., tDVXH, tXHXL, and tXLDX) also applyto reading operation.

Table 112. Parallel Programming Characteristics, VCC = 5 V ± 10%


VPP Programming Enable Voltage 11.5 12.5 V

IPP Programming Enable Current 250 µA

tDVXH Data and Control Valid before XTAL1 High 67 ns

tXLXH XTAL1 Low to XTAL1 High 200 ns

tXHXL XTAL1 Pulse Width High 150 ns

tXLDX Data and Control Hold after XTAL1 Low 67 ns

tXLWL XTAL1 Low to WR Low 0 ns

tXLPH XTAL1 Low to PAGEL high 0 ns

tPLXH PAGEL low to XTAL1 high 150 ns

tBVPH BS1 Valid before PAGEL High 67 ns

tPHPL PAGEL Pulse Width High 150 ns

tPLBX BS1 Hold after PAGEL Low 67 ns

tWLBX BS2/1 Hold after WR Low 67 ns

tPLWL PAGEL Low to WR Low 67 ns

tBVWL BS1 Valid to WR Low 67 ns

tWLWH WR Pulse Width Low 150 ns

tWLRL WR Low to RDY/BSY Low 0 1 µs

tWLRH WR Low to RDY/BSY High(1) 3.7 4.5 ms

tWLRH_CE WR Low to RDY/BSY High for Chip Erase(2) 7.5 9 ms

tXLOL XTAL1 Low to OE Low 0 ns

XTAL1

OE

ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)DATA

BS1

XA0

XA1


READ DATA (LOW BYTE)

READ DATA(HIGH BYTE)


tBVDV

tOLDV

tXLOL

tOHDZ

2672466E–AVR–10/02

Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lockbits commands.

2. tWLRH_CE is valid for the Chip Erase command.

SPI Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPIbus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI(input), and MISO (output). After RESET is set low, the Programming Enable instructionneeds to be executed first before program/erase operations can be executed. NOTE, inTable 113 on page 268, the pin mapping for SPI programming is listed. Not all parts usethe SPI pins dedicated for the internal SPI interface.

SPI Serial Programming Pin Mapping

Figure 136. SPI Serial Programming and Verify(1)

Notes: 1. If the device is clocked by the Internal Oscillator, it is no need to connect a clocksource to the XTAL1 pin.

2. VCC -0.3V < AVCC < VCC +0.3V, however, AVCC should always be within 2.7 - 5.5V

When programming the EEPROM, an auto-erase cycle is built into the self-timed pro-gramming operation (in the serial mode ONLY) and there is no need to first execute the

tBVDV BS1 Valid to DATA valid 0 250 ns

tOLDV OE Low to DATA Valid 250 ns

tOHDZ OE High to DATA Tri-stated 250 ns

Table 112. Parallel Programming Characteristics, VCC = 5 V ± 10% (Continued)


Table 113. Pin Mapping SPI Serial Programming

Symbol Pins I/O Description

MOSI PB5 I Serial Data in

MISO PB6 O Serial Data out

SCK PB7 I Serial Clock

VCC

GND

XTAL1

SCK

MISO

MOSI

RESET

PB5

PB6

PB7

+2.7 - 5.5V

VCC

+2.7 - 5.5V(2)

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Chip Erase instruction. The Chip Erase operation turns the content of every memorylocation in both the Program and EEPROM arrays into $FF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and highperiods for the serial clock (SCK) input are defined as follows:

Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz

High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz

SPI Serial Programming Algorithm

When writing serial data to the ATmega16, data is clocked on the rising edge of SCK.

When reading data from the ATmega16, data is clocked on the falling edge of SCK. SeeFigure 137 for timing details.

To program and verify the ATmega16 in the SPI Serial Programming mode, the follow-ing sequence is recommended (See four byte instruction formats in Table 115):

1. Power-up sequence:Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”.

2. Wait for at least 20 ms and enable SPI Serial Programming by sending the Pro-gramming Enable serial instruction to pin MOSI.

3. The SPI Serial Programming instructions will not work if the communication is out of synchronization. When in sync. the second byte ($53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give RESET a positive pulse and issue a new Program-ming Enable command.

4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 114). Accessing the SPI Serial Programming interface before the Flash write operation completes can result in incorrect programming.

5. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 114). In a chip erased device, no $FFs in the data file(s) need to be programmed.

6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO.

7. At the end of the programming session, RESET can be set high to commence normal operation.

8. Power-off sequence (if needed):Set RESET to “1”.Turn VCC power off.

2692466E–AVR–10/02

Data Polling Flash When a page is being programmed into the Flash, reading an address location withinthe page being programmed will give the value $FF. At the time the device is ready for anew page, the programmed value will read correctly. This is used to determine when thenext page can be written. Note that the entire page is written simultaneously and anyaddress within the page can be used for polling. Data polling of the Flash will not workfor the value $FF, so when programming this value, the user will have to wait for at leasttWD_FLASH before programming the next page. As a chip erased device contains $FF inall locations, programming of addresses that are meant to contain $FF, can be skipped.See Table 114 for tWD_FLASH value

Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading theaddress location being programmed will give the value $FF. At the time the device isready for a new byte, the programmed value will read correctly. This is used to deter-mine when the next byte can be written. This will not work for the value $FF, but the usershould have the following in mind: As a chip erased device contains $FF in all locations,programming of addresses that are meant to contain $FF, can be skipped. This doesnot apply if the EEPROM is re-programmed without chip erasing the device. In thiscase, data polling cannot be used for the value $FF, and the user will have to wait atleast tWD_EEPROM before programming the next byte. See Table 114 for tWD_EEPROMvalue.

Figure 137. SPI Serial Programming Waveforms

Table 114. Minimum Wait Delay before Writing the Next Flash or EEPROM Location

Symbol Minimum Wait Delay

tWD_FLASH 4.5 ms

tWD_EEPROM 9.0 ms

tWD_ERASE 9.0 ms

MSB

MSB

LSB

LSB

SERIAL CLOCK INPUT(SCK)

SERIAL DATA INPUT (MOSI)

(MISO)

SAMPLE

SERIAL DATA OUTPUT

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Note: a = address high bitsb = address low bitsH = 0 – Low byte, 1 – High Byteo = data outi = data inx = don’t care

Table 115. SPI Serial Programming Instruction Set

Instruction

Instruction Format

OperationByte 1 Byte 2 Byte 3 Byte4

Programming Enable1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable SPI Serial Programming after

RESET goes low.

Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.

Read Program Memory0010 H000 000a aaaa bbbb bbbb oooo oooo Read H (high or low) data o from

Program memory at word address a:b.

Load Program Memory Page

0100 H000 00xx xxxx xxbb bbbb iiii iiii Write H (high or low) data i to Program Memory page at word address b. Data low byte must be loaded before Data high byte is applied within the same address.

Write Program Memory Page0100 1100 000a aaaa bbxx xxxx xxxx xxxx Write Program Memory Page at

address a:b.

Read EEPROM Memory1010 0000 00xx xxxa bbbb bbbb oooo oooo Read data o from EEPROM memory at

address a:b.

Write EEPROM Memory1100 0000 00xx xxxa bbbb bbbb iiii iiii Write data i to EEPROM memory at

address a:b.

Read Lock Bits0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0” = programmed, “1”

= unprogrammed. See Table 102 on page 254 for details.

Write Lock Bits1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = “0” to

program Lock bits. See Table 102 on page 254 for details.

Read Signature Byte 0011 0000 00xx xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b.

Write Fuse Bits1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to

unprogram. See Table 105 on page 256 for details.

Write Fuse High Bits1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to

unprogram. See Table 104 on page 255 for details.

Read Fuse Bits0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = programmed, “1”

= unprogrammed. See Table 105 on page 256 for details.

Read Fuse High Bits0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse high bits. “0” = pro-

grammed, “1” = unprogrammed. See Table 104 on page 255 for details.

Read Calibration Byte 0011 1000 00xx xxxx 0000 0000 oooo oooo Read Calibration Byte

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SPI Serial Programming Characteristics

For characteristics of the SPI module, see “SPI Timing Characteristics” on page 289.

Programming via the JTAG Interface

Programming through the JTAG interface requires control of the four JTAG specificpins: TCK, TMS, TDI and TDO. Control of the reset and clock pins is not required.

To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. Thedevice is default shipped with the fuse programmed. In addition, the JTD bit in MCUCSRmust be cleared. Alternatively, if the JTD bit is set, the External Reset can be forced low.Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are availablefor programming. This provides a means of using the JTAG pins as normal port pins inrunning mode while still allowing In-System Programming via the JTAG interface. Notethat this technique can not be used when using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedicated for this purpose.

As a definition in this data sheet, the LSB is shifted in and out first of all Shift Registers.

Programming Specific JTAG Instructions

The instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instruc-tions useful for Programming are listed below.

The OPCODE for each instruction is shown behind the instruction name in hex format.The text describes which Data Register is selected as path between TDI and TDO foreach instruction.

The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It canalso be used as an idle state between JTAG sequences. The state machine sequencefor changing the instruction word is shown in Figure 138.

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Figure 138. State Machine Sequence for Changing the Instruction Word

AVR_RESET ($C) The AVR specific public JTAG instruction for setting the AVR device in the Reset modeor taking the device out from the Reset Mode. The TAP controller is not reset by thisinstruction. The one bit Reset Register is selected as Data Register. Note that the Resetwill be active as long as there is a logic “one” in the Reset Chain. The output from thischain is not latched.


• Shift-DR: The Reset Register is shifted by the TCK input.

PROG_ENABLE ($4) The AVR specific public JTAG instruction for enabling programming via the JTAG port.The 16-bit Programming Enable register is selected as Data Register. The active statesare the following:

• Shift-DR: The programming enable signature is shifted into the Data Register.

• Update-DR: The programming enable signature is compared to the correct value, and Programming mode is entered if the signature is valid.

Test-Logic-Reset

Run-Test/Idle

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-DR Scan

Capture-DR

0

1

0 1 1 1

0 0

0 0

1 1

1 0

1

1

0

1

0

0

1 0

1

1

0

1

0

0

00

11

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PROG_COMMANDS ($5) The AVR specific public JTAG instruction for entering programming commands via theJTAG port. The 15-bit Programming Command Register is selected as Data Register.The active states are the following:

• Capture-DR: The result of the previous command is loaded into the Data Register.

• Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command.

• Update-DR: The programming command is applied to the Flash inputs

• Run-Test/Idle: One clock cycle is generated, executing the applied command (not always required, see Table 116 below).

PROG_PAGELOAD ($6) The AVR specific public JTAG instruction to directly load the Flash data page via theJTAG port. The 1024 bit Virtual Flash Page Load Register is selected as Data Register.This is a virtual scan chain with length equal to the number of bits in one Flash page.Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Update-DR stateis not used to transfer data from the Shift Register. The data are automatically trans-ferred to the Flash page buffer byte by byte in the Shift-DR state by an internal statemachine. This is the only active state:

• Shift-DR: Flash page data are shifted in from TDI by the TCK input, and automatically loaded into the Flash page one byte at a time.

PROG_PAGEREAD ($7) The AVR specific public JTAG instruction to read one full Flash data page via the JTAGport. The 1032 bit Virtual Flash Page Read Register is selected as Data Register. This isa virtual scan chain with length equal to the number of bits in one Flash page plus 8.Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Capture-DRstate is not used to transfer data to the Shift Register. The data are automatically trans-ferred from the Flash page buffer byte by byte in the Shift-DR state by an internal statemachine. This is the only active state:

• Shift-DR: Flash data are automatically read one byte at a time and shifted out on TDO by the TCK input. The TDI input is ignored.

Note: The JTAG instructions PROG_PAGELOAD and PROG_PAGEREAD can only be used ifthe AVR devce is the first decive in JTAG scan chain. If the AVR cannot be the firstdevice in the scan chain, the byte-wise programming algorithm must be used.

Data Registers The Data Registers are selected by the JTAG instruction registers described in section“Programming Specific JTAG Instructions” on page 272. The data registers relevant forprogramming operations are:

• Reset Register

• Programming Enable Register

• Programming Command Register

• Virtual Flash Page Load Register

• Virtual Flash Page Read Register

Reset Register The Reset Register is a Test Data Register used to reset the part during programming. Itis required to reset the part before entering programming mode.

A high value in the Reset Register corresponds to pulling the external Reset low. Thepart is reset as long as there is a high value present in the Reset Register. Dependingon the Fuse settings for the clock options, the part will remain reset for a Reset Time-outPeriod (refer to “Clock Sources” on page 23) after releasing the Reset Register. Theoutput from this Data Register is not latched, so the reset will take place immediately, asshown in Figure 115 on page 224.

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Programming Enable Register The Programming Enable Register is a 16-bit register. The contents of this register iscompared to the programming enable signature, binary code 1010_0011_0111_0000.When the contents of the register is equal to the programming enable signature, pro-gramming via the JTAG port is enabled. The register is reset to 0 on Power-on Reset,and should always be reset when leaving Programming mode.

Figure 139. Programming Enable Register

Programming Command Register

The Programming Command Register is a 15-bit register. This register is used to seri-ally shift in programming commands, and to serially shift out the result of the previouscommand, if any. The JTAG Programming Instruction Set is shown in Table 116. Thestate sequence when shifting in the programming commands is illustrated in Figure 141.

TDI

TDO

DATA

= D Q

ClockDR & PROG_ENABLE

Programming Enable$A370

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Figure 140. Programming Command Register

TDI

TDO

STROBES

ADDRESS/DATA

FlashEEPROM

FusesLock Bits

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Table 116. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 – Low byte, 1 – High Byte, o = data out, i = data in, x = don’t care

Instruction TDI sequence TDO sequence Notes

1a. Chip erase 0100011_10000000

0110001_100000000110011_100000000110011_10000000

xxxxxxx_xxxxxxxx

xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxx

1b. Poll for chip erase complete 0110011_10000000 xxxxxox_xxxxxxxx (2)

2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx

2b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)

2c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

2d. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx

2e. Load Data High Byte 0010111_iiiiiiii xxxxxxx_xxxxxxxx

2f. Latch Data 0110111_000000001110111_00000000

0110111_00000000

xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxx

xxxxxxx_xxxxxxxx

(1)

2g. Write Flash Page 0110111_00000000

0110101_000000000110111_000000000110111_00000000

xxxxxxx_xxxxxxxx


(1)

2h. Poll for Page Write complete 0110111_00000000 xxxxxox_xxxxxxxx (2)

3a. Enter Flash Read 0100011_00000010 xxxxxxx_xxxxxxxx



3d. Read Data Low and High Byte 0110010_000000000110110_000000000110111_00000000

xxxxxxx_xxxxxxxxxxxxxxx_ooooooooxxxxxxx_oooooooo

low bytehigh byte

4a. Enter EEPROM Write 0100011_00010001 xxxxxxx_xxxxxxxx



4d. Load Data Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx

4e. Latch Data 0110111_000000001110111_000000000110111_00000000


(1)

4f. Write EEPROM Page 0110011_000000000110001_00000000

0110011_000000000110011_00000000



(1)

4g. Poll for Page Write complete 0110011_00000000 xxxxxox_xxxxxxxx (2)

5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx


2772466E–AVR–10/02


5d. Read Data Byte 0110011_bbbbbbbb0110010_000000000110011_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_xxxxxxxxxxxxxxx_oooooooo

6a. Enter Fuse Write 0100011_01000000 xxxxxxx_xxxxxxxx

6b. Load Data Low Byte(6) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)

6c. Write Fuse High byte 0110111_000000000110101_00000000

0110111_000000000110111_00000000



(1)

6d. Poll for Fuse Write complete 0110111_00000000 xxxxxox_xxxxxxxx (2)

6e. Load Data Low Byte(7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)

6f. Write Fuse Low byte 0110011_000000000110001_00000000

0110011_000000000110011_00000000



(1)

6g. Poll for Fuse Write complete 0110011_00000000 xxxxxox_xxxxxxxx (2)

7a. Enter Lock Bit Write 0100011_00100000 xxxxxxx_xxxxxxxx

7b. Load Data Byte(8) 0010011_11iiiiii xxxxxxx_xxxxxxxx (4)

7c. Write Lock Bits 0110011_000000000110001_000000000110011_00000000

0110011_00000000


xxxxxxx_xxxxxxxx

(1)

7d. Poll for Lock Bit Write complete 0110011_00000000 xxxxxox_xxxxxxxx (2)

8a. Enter Fuse/Lock Bit Read 0100011_00000100 xxxxxxx_xxxxxxxx

8b. Read Fuse High Byte(6) 0111110_000000000111111_00000000


8c. Read Fuse Low Byte(7) 0110010_000000000110011_00000000


8d. Read Lock Bits(8) 0110110_000000000110111_00000000

xxxxxxx_xxxxxxxxxxxxxxx_xxoooooo

(5)

8e. Read Fuses and Lock Bits 0111110_000000000110010_000000000110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxxxxxxxxx_ooooooooxxxxxxx_ooooooooxxxxxxx_oooooooo

(5)fuse high bytefuse low byte

lock bits

9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx

9b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

9c. Read Signature Byte 0110010_000000000110011_00000000


Table 116. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 – Low byte, 1 – High Byte, o = data out, i = data in, x = don’t care


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Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which isnormally the case).

2. Repeat until o = “1”.3. Set bits to “0” to program the corresponding fuse, “1” to unprogram the fuse.4. Set bits to “0” to program the corresponding lock bit, “1” to leave the lock bit unchanged.5. “0” = programmed, “1” = unprogrammed.6. The bit mapping for fuses high byte is listed in Table 104 on page 2557. The bit mapping for fuses low byte is listed in Table 105 on page 2568. The bit mapping for Lock bits byte is listed in Table 102 on page 2549. Address bits exceeding PCMSB and EEAMSB (Table 110 and Table 111) are don’t care

10a. Enter Calibration Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx

10b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

10c. Read Calibration Byte 0110110_000000000110111_00000000


11a. Load No Operation Command 0100011_000000000110011_00000000


Table 116. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 – Low byte, 1 – High Byte, o = data out, i = data in, x = don’t care


2792466E–AVR–10/02

Figure 141. State Machine Sequence for Changing/Reading the Data Word

Virtual Flash Page Load Register

The Virtual Flash Page Load Register is a virtual scan chain with length equal to thenumber of bits in one Flash page. Internally the Shift Register is 8-bit, and the data areautomatically transferred to the Flash page buffer byte by byte. Shift in all instructionwords in the page, starting with the LSB of the first instruction in the page and endingwith the MSB of the last instruction in the page. This provides an efficient way to load theentire Flash page buffer before executing Page Write.

Test-Logic-Reset

Run-Test/Idle

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-DR Scan

Capture-DR

0

1

0 1 1 1

0 0

0 0

1 1

1 0

1

1

0

1

0

0

1 0

1

1

0

1

0

0

00

11

280 ATmega16(L) 2466E–AVR–10/02

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Figure 142. Virtual Flash Page Load Register

Virtual Flash Page Read Register

The Virtual Flash Page Read Register is a virtual scan chain with length equal to thenumber of bits in one Flash page plus 8. Internally the Shift Register is 8-bit, and thedata are automatically transferred from the Flash data page byte by byte. The first 8cycles are used to transfer the first byte to the internal Shift Register, and the bits thatare shifted out during these 8 cycles should be ignored. Following this initialization, dataare shifted out starting with the LSB of the first instruction in the page and ending withthe MSB of the last instruction in the page. This provides an efficient way to read one fullFlash page to verify programming.

Figure 143. Virtual Flash Page Read Register

TDI

TDO

DATA

FlashEEPROM

FusesLock Bits

STROBES

ADDRESS

StateMachine

TDI

TDO

DATA

FlashEEPROM

FusesLock Bits

STROBES

ADDRESS

StateMachine

2812466E–AVR–10/02

Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 116.

Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register.

2. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Pro-gramming Enable Register.

Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS.

2. Disable all programming instructions by usning no operation instruction 11a.

3. Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the pro-gramming Enable Register.

4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.

Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS.

2. Start chip erase using programming instruction 1a.

3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 112 on page 267).

Programming the Flash 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash write using programming instruction 2a.

3. Load address high byte using programming instruction 2b.

4. Load address low byte using programming instruction 2c.

5. Load data using programming instructions 2d, 2e and 2f.

6. Repeat steps 4 and 5 for all instruction words in the page.

7. Write the page using programming instruction 2g.

8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH (refer to Table 112 on page 267).

9. Repeat steps 3 to 7 until all data have been programmed.

A more efficient data transfer can be achieved using the PROG_PAGELOADinstruction:

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash write using programming instruction 2a.

3. Load the page address using programming instructions 2b and 2c. PCWORD (refer to Table 110 on page 258) is used to address within one page and must be written as 0.

4. Enter JTAG instruction PROG_PAGELOAD.

5. Load the entire page by shifting in all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page.


7. Write the page using programming instruction 2g.

8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH (refer to Table 112 on page 267).


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Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash read using programming instruction 3a.

3. Load address using programming instructions 3b and 3c.

4. Read data using programming instruction 3d.

5. Repeat steps 3 and 4 until all data have been read.

A more efficient data transfer can be achieved using the PROG_PAGEREADinstruction:


2. Enable Flash read using programming instruction 3a.

3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to Table 110 on page 258) is used to address within one page and must be written as 0.

4. Enter JTAG instruction PROG_PAGEREAD.

5. Read the entire page by shifting out all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. Remember that the first 8 bits shifted out should be ignored.


7. Repeat steps 3 to 6 until all data have been read.

Programming the EEPROM 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable EEPROM write using programming instruction 4a.

3. Load address high byte using programming instruction 4b.

4. Load address low byte using programming instruction 4c.

5. Load data using programming instructions 4d and 4e.

6. Repeat steps 4 and 5 for all data bytes in the page.

7. Write the data using programming instruction 4f.

8. Poll for EEPROM write complete using programming instruction 4g, or wait for tWLRH (refer to Table 112 on page 267).


Note that the PROG_PAGELOAD instruction can not be used when programming theEEPROM

Reading the EEPROM 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable EEPROM read using programming instruction 5a.

3. Load address using programming instructions 5b and 5c.

4. Read data using programming instruction 5d.

5. Repeat steps 3 and 4 until all data have been read.

Note that the PROG_PAGEREAD instruction can not be used when reading theEEPROM

Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Fuse write using programming instruction 6a.

3. Load data high byte using programming instructions 6b. A bit value of “0” will program the corresponding fuse, a “1” will unprogram the fuse.

4. Write Fuse High byte using programming instruction 6c.

2832466E–AVR–10/02

5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to Table 112 on page 267).

6. Load data low byte using programming instructions 6e. A “0” will program the fuse, a “1” will unprogram the fuse.

7. Write Fuse low byte using programming instruction 6f.

8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 112 on page 267).

Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Lock bit write using programming instruction 7a.

3. Load data using programming instructions 7b. A bit value of “0” will program the corresponding Lock bit, a “1” will leave the Lock bit unchanged.

4. Write Lock bits using programming instruction 7c.

5. Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH (refer to Table 112 on page 267).

Reading the Fuses and Lock Bits


2. Enable Fuse/Lock bit read using programming instruction 8a.

3. To read all Fuses and Lock bits, use programming instruction 8e.To only read Fuse high byte, use programming instruction 8b.To only read Fuse low byte, use programming instruction 8c.To only read Lock bits, use programming instruction 8d.

Reading the Signature Bytes 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Signature byte read using programming instruction 9a.

3. Load address $00 using programming instruction 9b.

4. Read first signature byte using programming instruction 9c.

5. Repeat steps 3 and 4 with address $01 and address $02 to read the second and third signature bytes, respectively.

Reading the Calibration Byte 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Calibration byte read using programming instruction 10a.

3. Load address $00 using programming instruction 10b.

4. Read the calibration byte using programming instruction 10c.

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Electrical Characteristics

Absolute Maximum Ratings*Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Storage Temperature..................................... -65°C to +150°C

Voltage on any Pin except RESETwith respect to Ground ................................-1.0V to VCC+0.5V

Voltage on RESET with respect to Ground......-1.0V to +13.0V

Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current VCC and GND Pins................................ 200.0 mA

DC Characteristics

TA = -40°C to 85°C, VCC = 2.7V to 5.5V (Unless Otherwise Noted)


VIL Input Low Voltage Except XTAL1 pin -0.5 0.2 VCC(1) V

VIL1 Input Low VoltageXTAL1 pin, External Clock Selected

-0.5 0.1 VCC(1) V

VIH Input High VoltageExcept XTAL1 and RESET pins

0.6 VCC(2) VCC +0.5 V

VIH1 Input High VoltageXTAL1 pin, External Clock Selected

0.7 VCC(2) VCC +0.5 V

VIH2 Input High Voltage RESET pin 0.9 VCC(2) VCC +0.5 V

VOLOutput Low Voltage(3)

(Ports A,B,C,D)IOL = 20 mA, VCC = 5VIOL = 10 mA, VCC = 3V

0.70.5

VV

VOHOutput High Voltage(4)

(Ports A,B,C,D)IOH = -20 mA, VCC = 5VIOH = -10 mA, VCC = 3V

4.02.2

VV

IILInput LeakageCurrent I/O Pin

Vcc = 5.5V, pin low(absolute value)

1 µA

IIHInput LeakageCurrent I/O Pin

Vcc = 5.5V, pin high(absolute value)

1 µA

RRST Reset Pull-up Resistor 20 100 kΩ

Rpu I/O Pin Pull-up Resistor 20 100 kΩ

2852466E–AVR–10/02

Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low2. “Min” means the lowest value where the pin is guaranteed to be read as high3. Although each I/O port can sink more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state

conditions (non-transient), the following must be observed:PDIP Package:1] The sum of all IOL, for all ports, should not exceed 400 mA.2] The sum of all IOL, for port A0 - A7, should not exceed 200 mA.3] The sum of all IOL, for ports B0 - B7,C0 - C7, D0 - D7 and XTAL2, should not exceed 300 mA.TQFP and MLF Package:1] The sum of all IOL, for all ports, should not exceed 400 mA.2] The sum of all IOL, for ports A0 - A7, should not exceed 200 mA.3] The sum of all IOL, for ports B0 - B4, should not exceed 200 mA.4] The sum of all IOL, for ports B3 - B7, XTAL2, D0 - D2, should not exceed 200 mA.5] The sum of all IOL, for ports D3 - D7, should not exceed 200 mA.6] The sum of all IOL, for ports C0 - C7, should not exceed 200 mA.If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greaterthan the listed test condition.

4. Although each I/O port can source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady stateconditions (non-transient), the following must be observed:PDIP Package:1] The sum of all IOH, for all ports, should not exceed 400 mA.2] The sum of all IOH, for port A0 - A7, should not exceed 200 mA.3] The sum of all IOH, for ports B0 - B7,C0 - C7, D0 - D7 and XTAL2, should not exceed 300 mA.TQFP and MLF Package:1] The sum of all IOH, for all ports, should not exceed 400 mA.2] The sum of all IOH, for ports A0 - A7, should not exceed 200 mA.3] The sum of all IOH, for ports B0 - B4, should not exceed 200 mA.

ICC

Power Supply Current

Active 1 MHz VCC = 3V

(ATmega16L)1.1 mA

Active 4 MHz, VCC = 3V

(ATmega16L)3.8 5 mA

Active 8 MHz, VCC = 5V

(ATmega16)12 15 mA

Idle 1 MHz VCC = 3V

(ATmega16L)0.35 mA

Idle 4 MHz, VCC = 3V

(ATmega16L)1.2 2 mA

Idle 8 MHz, VCC = 5V

(ATmega16)5.5 8 mA

Power-down Mode(5)WDT enabled, VCC = 3V < 25 40 µA

WDT disabled, VCC = 3V < 10 15 µA

VACIOAnalog Comparator Input Offset Voltage

VCC = 5VVin = VCC/2

40 mV

IACLKAnalog Comparator Input Leakage Current

VCC = 5VVin = VCC/2

-50 50 nA

tACIDAnalog Comparator Propagation Delay

VCC = 2.7VVCC = 4.0V

750500

ns

DC Characteristics (Continued)

TA = -40°C to 85°C, VCC = 2.7V to 5.5V (Unless Otherwise Noted)


286 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

4] The sum of all IOH, for ports B3 - B7, XTAL2, D0 - D2, should not exceed 200 mA.5] The sum of all IOH, for ports D3 - D7, should not exceed 200 mA.6] The sum of all IOH, for ports C0 - C7, should not exceed 200 mA.If IOH exceeds the test condition, VOH may exceed therelated specification. Pins are not guaranteed to source current greater than the listed test condition.

5. Minimum VCC for Power-down is 2.5V.

External Clock Drive Waveforms

Figure 144. External Clock Drive Waveforms

External Clock Drive

Notes: 1. R should be in the range 3 kΩ - 100 kΩ, and C should be at least 20 pF.2. The frequency will vary with package type and board layout.

VIL1

VIH1

Table 117. External Clock Drive

Symbol Parameter

VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V

UnitsMin Max Min Max

1/tCLCL Oscillator Frequency 0 8 0 16 MHz

tCLCL Clock Period 125 62.5 ns

tCHCX High Time 50 25 ns

tCLCX Low Time 50 25 ns

tCLCH Rise Time 1.6 0.5 µs

tCHCL Fall Time 1.6 0.5 µs

Table 118. External RC Oscillator, Typical Frequencies (VCC = 5)

R [kΩ](1) C [pF] f(2)

100 47 87 kHz

33 22 650 kHz

10 22 2.0 MHz

2872466E–AVR–10/02

Two-wire Serial Interface CharacteristicsTable 119 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega16 Two-wire SerialInterface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 145.

Notes: 1. In ATmega16, this parameter is characterized and not 100% tested.2. Required only for fSCL > 100 kHz.3. Cb = capacitance of one bus line in pF.4. fCK = CPU clock frequency

Table 119. Two-wire Serial Bus Requirements

Symbol Parameter Condition Min Max Units

VIL Input Low-voltage -0.5 0.3 VCC V

VIH Input High-voltage 0.7 VCC VCC + 0.5 V

Vhys(1) Hysteresis of Schmitt Trigger Inputs 0.05 VCC

(2) – V

VOL(1) Output Low-voltage 3 mA sink current 0 0.4 V

tr(1) Rise Time for both SDA and SCL 20 + 0.1Cb

(3)(2) 300 ns

tof(1) Output Fall Time from VIHmin to VILmax 10 pF < Cb < 400 pF(3) 20 + 0.1Cb

(3)(2) 250 ns

tSP(1) Spikes Suppressed by Input Filter 0 50(2) ns

Ii Input Current each I/O Pin 0.1VCC < Vi < 0.9VCC -10 10 µA

Ci(1) Capacitance for each I/O Pin – 10 pF

fSCL SCL Clock Frequency fCK(4) > max(16fSCL, 250kHz)(5) 0 400 kHz

Rp Value of Pull-up resistor

fSCL ≤ 100 kHz

fSCL > 100 kHz

tHD;STA Hold Time (repeated) START Condition fSCL ≤ 100 kHz 4.0 – µs

fSCL > 100 kHz 0.6 – µs

tLOW Low Period of the SCL Clock fSCL ≤ 100 kHz(6) 4.7 – µs

fSCL > 100 kHz(7) 1.3 – µs

tHIGH High period of the SCL clock fSCL ≤ 100 kHz 4.0 – µs

fSCL > 100 kHz 0.6 – µs

tSU;STA

Set-up time for a repeated START condition

fSCL ≤ 100 kHz 4.7 – µs

fSCL > 100 kHz 0.6 – µs

tHD;DAT Data hold time fSCL ≤ 100 kHz 0 3.45 µs

fSCL > 100 kHz 0 0.9 µs

tSU;DAT Data setup time fSCL ≤ 100 kHz 250 – ns

fSCL > 100 kHz 100 – ns

tSU;STO Setup time for STOP condition fSCL ≤ 100 kHz 4.0 – µs

fSCL > 100 kHz 0.6 – µs

tBUF Bus free time between a STOP and START condition

fSCL ≤ 100 kHz 4.7 – µs

fSCL > 100 kHz 1.3 – µs

VCC 0,4V–

3mA---------------------------- 1000ns

Cb------------------- Ω

VCC 0,4V–

3mA---------------------------- 300ns

Cb---------------- Ω

288 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

5. This requirement applies to all ATmega16 Two-wire Serial Interface operation. Otherdevices connected to the Two-wire Serial Bus need only obey the general fSCLrequirement.

6. The actual low period generated by the ATmega16 Two-wire Serial Interface is (1/fSCL- 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to bestrictly met at fSCL = 100 kHz.

7. The actual low period generated by the ATmega16 Two-wire Serial Interface is (1/fSCL- 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308 kHz whenfCK = 8 MHz. Still, ATmega16 devices connected to the bus may communicate at fullspeed (400 kHz) with other ATmega16 devices, as well as any other device with aproper tLOW acceptance margin.

Figure 145. Two-wire Serial Bus Timing

SPI Timing Characteristics

See Figure 146 and Figure 147 for details.

tSU;STA

tLOW

tHIGH

tLOW

tof

tHD;STA tHD;DAT tSU;DATtSU;STO

tBUF

SCL

SDA

tr

Table 120. SPI Timing Parameters

Description Mode Min Typ Max

1 SCK period Master See Table 58

ns

2 SCK high/low Master 50% duty cycle

3 Rise/Fall time Master 3.6

4 Setup Master 10

5 Hold Master 10

6 Out to SCK Master 0.5 • tSCK

7 SCK to out Master 10

8 SCK to out high Master 10

9 SS low to out Slave 15

10 SCK period Slave 4 • tck

11 SCK high/low Slave 2 • tck

12 Rise/Fall time Slave 1.6 µs

13 Setup Slave 10

ns

14 Hold Slave 10

15 SCK to out Slave 15

16 SCK to SS high Slave 20

17 SS high to tri-state Slave 10

18 SS low to SCK Slave 2 • tck

2892466E–AVR–10/02

Figure 146. SPI Interface Timing Requirements (Master Mode)

Figure 147. SPI Interface Timing Requirements (Slave Mode)

MOSI(Data Output)

SCK(CPOL = 1)

MISO(Data Input)

SCK(CPOL = 0)

SS

MSB LSB

LSBMSB

...

...

6 1

2 2

34 5

87

MISO(Data Output)

SCK(CPOL = 1)

MOSI(Data Input)

SCK(CPOL = 0)

SS

MSB LSB

LSBMSB

...

...

10

11 11

1213 14

1715

9

X

16

18

290 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

ADC Characteristics – Preliminary Data

Table 121. ADC Characteristics


Resolution

Single Ended Conversion 10 Bits

Differential Conversion Gain = 1x or 20x

8 Bits

Differential ConversionGain = 200x

7 Bits

Absolute Accuracy (Including INL, DNL, Quantization Error, Gain, and Offset Error).

Single Ended ConversionVREF = 4V, VCC = 4VADC clock = 200 kHz

1.5 2.5 LSB

Single Ended ConversionVREF = 4V, VCC = 4VADC clock = 1 MHz

3 4 LSB

Single Ended ConversionVREF = 4V, VCC = 4VADC clock = 200 kHzNoise Reduction mode

1.5 LSB

Single Ended ConversionVREF = 4V, VCC = 4VADC clock = 1 MHzNoise Reduction mode

3 LSB

Integral Non-linearity (INL)Single Ended ConversionVREF = 4V, VCC = 4VADC clock = 200 kHz

1 LSB

Differential Non-linearity (DNL)Single Ended ConversionVREF = 4V, VCC = 4VADC clock = 200 kHz

0.5 LSB

Gain ErrorSingle Ended ConversionVREF = 4V, VCC = 4VADC clock = 200 kHz

1 LSB

Offset ErrorSingle Ended ConversionVREF = 4V, VCC = 4VADC clock = 200 kHz

LSB

Conversion Time Free Running Conversion 13 260 µs

Clock Frequency 0.05 1 MHz

AVCC Analog Supply Voltage VCC - 0.3(1) VCC + 0.3(2) V

VREF Reference VoltageSingle Ended Conversion 2.0 AVCC V

Differential Conversion 2.0 AVCC - 0.2 V

VIN

Input voltageSingle ended channels GND VREF V

Differential channels 0 VREF V

Input bandwidthSingle ended channels 38.5 kHz

Differential channels 4 kHz

2912466E–AVR–10/02

Notes: 1. Minimum for AVCC is 2.7V.2. Maximum for AVCC is 5.5V.

VINT Internal Voltage Reference 2.3 2.56 2.7 V

RREF Reference Input Resistance 32 kΩ

RAIN Analog Input Resistance 100 MΩ

Table 121. ADC Characteristics (Continued)


292 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

ATmega16 Typical Characteristics – Preliminary DataThe following charts show typical behavior. These figures are not tested during manu-facturing. All current consumption measurements are performed with all I/O pinsconfigured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source.

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage,operating frequency, loading of I/O pins, switching rate of I/O pins, code executed andambient temperature. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) asCL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switch-ing frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaran-teed to function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with WatchdogTimer enabled and Power-down mode with Watchdog Timer disabled represents the dif-ferential current drawn by the Watchdog Timer.

2932466E–AVR–10/02

Figure 148. RC Oscillator Frequency vs. Temperature (the devices are calibrated to1 MHz at Vcc = 5V, T=25c)

Figure 149. RC Oscillator Frequency vs. Operating Voltage (the devices are calibratedto 1 MHz at Vcc = 5V, T=25c)

CALIBRATED 1MHz RC OSCILLATOR FREQUENCY

FR

c(M

Hz)

Ta(˚C)

vs. TEMPERATURE

V = 2.7Vcc

V = 5.5Vcc

V = 5.0Vcc

V = 4.5Vcc

V = 4.0Vcc

V = 3.6Vcc

V = 3.3Vcc

V = 3.0Vcc

0.92

0.93

0.94

0.95

0.96

0.97

0.98

0.99

1

1.01

1.02

1.03

-40 -20 0 20 40 60 80


FR

c(M

Hz)

Vcc(V)

T = 85˚CA

T = 45˚CA

T = 70˚CA

vs. OPERATING VOLTAGE

0.92

0.93

0.94

0.95

0.96

0.97

0.98

0.99

1

1.01

1.02

1.03

2.5 3 3.5 4 4.5 5 5.5

T = -40˚CA

T = 25˚CA

T = -10˚CA

294 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)




FR

c(M

Hz)

Ta(˚C)

vs. TEMPERATURE

V = 2.7Vcc

V = 5.5Vcc

V = 5.0Vcc

V = 4.5Vcc

V = 4.0Vcc

V = 3.6Vcc

V = 3.3Vcc

V = 3.0Vcc

1.8

1.85

1.9

1.95

2

2.05

2.1

-40 -20 0 20 40 60 80


FR

c(M

Hz)

Vcc(V)

T = 85˚CA

T = 45˚CA

T = 70˚CA


T = 25˚CA

T = -10˚CA

1.8

1.85

1.9

1.95

2

2.05

2.1

2.5 3 3.5 4 4.5 5 5.5

T = -40˚CA

2952466E–AVR–10/02




FR

c(M

Hz)

Ta(˚C)

vs. TEMPERATURE

V = 2.7Vcc

V = 5.5Vcc

V = 5.0Vcc

V = 4.5Vcc

V = 4.0Vcc

V = 3.6Vcc

V = 3.3Vcc

V = 3.0Vcc

3.6

3.65

3.7

3.75

3.8

3.85

3.9

3.95

4

4.05

4.1

-40 -20 0 20 40 60 80


FR

c(M

Hz)

Vcc(V)

T = 45˚CA

T = 70˚CA


T = 25˚CA

T = -10˚CA

3.6

3.65

3.7

3.75

3.8

3.85

3.9

3.95

4

4.05

4.1

2.5 3 3.5 4 4.5 5 5.5

T = -40˚CA

T = 85˚CA

296 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Figure 154. RC Oscillator Frequency vs. Temperature (the devices are calibrated to 8MHz at Vcc = 5V, T=25c)



FR

c(M

Hz)

Ta(˚C)

vs. TEMPERATURE

V = 2.7Vcc

V = 5.5Vcc

V = 5.0Vcc

V = 4.5Vcc

V = 4.0Vcc

V = 3.6Vcc

V = 3.3Vcc

V = 3.0Vcc

6.7

6.9

7.1

7.3

7.5

7.7

7.9

8.1

8.3

8.5

-40 -20 0 20 40 60 80


FR

c(M

Hz)

Vcc(V)

T = 45˚CA

T = 70˚CA


T = 25˚CA

T = -10˚CA

T = -40˚CA

T = 85˚CA

6.7

6.9

7.1

7.3

7.5

7.7

7.9

8.1

8.3

8.5

2.5 3 3.5 4 4.5 5 5.5

2972466E–AVR–10/02

Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

$3F ($5F) SREG I T H S V N Z C 7

$3E ($5E) SPH – – – – – SP10 SP9 SP8 10

$3D ($5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 10

$3C ($5C) OCR0 Timer/Counter0 Output Compare Register 80

$3B ($5B) GICR INT1 INT0 INT2 – – – IVSEL IVCE 45, 65

$3A ($5A) GIFR INTF1 INTF0 INTF2 – – – – – 66

$39 ($59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 80, 109, 126

$38 ($58) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 80, 110, 127

$37 ($57) SPMCR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN 245

$36 ($56) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 174

$35 ($55) MCUCR SM2 SE SM1 SM0 ISC11 ISC10 ISC01 ISC00 30, 64

$34 ($54) MCUCSR JTD ISC2 – JTRF WDRF BORF EXTRF PORF 38, 65, 225

$33 ($53) TCCR0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 77

$32 ($52) TCNT0 Timer/Counter0 (8 Bits) 79

$31(1) ($51)(1) OSCCAL Oscillator Calibration Register 28

OCDR On-Chip Debug Register 221

$30 ($50) SFIOR ADTS2 ADTS1 ADTS0 ADHSM ACME PUD PSR2 PSR10 54,82,128,195,215

$2F ($4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 104

$2E ($4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 107

$2D ($4D) TCNT1H Timer/Counter1 – Counter Register High Byte 108

$2C ($4C) TCNT1L Timer/Counter1 – Counter Register Low Byte 108

$2B ($4B) OCR1AH Timer/Counter1 – Output Compare Register A High Byte 108

$2A ($4A) OCR1AL Timer/Counter1 – Output Compare Register A Low Byte 108

$29 ($49) OCR1BH Timer/Counter1 – Output Compare Register B High Byte 108

$28 ($48) OCR1BL Timer/Counter1 – Output Compare Register B Low Byte 108

$27 ($47) ICR1H Timer/Counter1 – Input Capture Register High Byte 109

$26 ($46) ICR1L Timer/Counter1 – Input Capture Register Low Byte 109

$25 ($45) TCCR2 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 121

$24 ($44) TCNT2 Timer/Counter2 (8 Bits) 123

$23 ($43) OCR2 Timer/Counter2 Output Compare Register 124

$22 ($42) ASSR – – – – AS2 TCN2UB OCR2UB TCR2UB 124

$21 ($41) WDTCR – – – WDTOE WDE WDP2 WDP1 WDP0 40

$20(2) ($40)(2) UBRRH URSEL – – – UBRR[11:8] 161

UCSRC URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 159

$1F ($3F) EEARH – – – – – – – EEAR8 17

$1E ($3E) EEARL EEPROM Address Register Low Byte 17

$1D ($3D) EEDR EEPROM Data Register 17

$1C ($3C) EECR – – – – EERIE EEMWE EEWE EERE 17

$1B ($3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 62

$1A ($3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 62

$19 ($39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 62

$18 ($38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 62

$17 ($37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 62

$16 ($36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 63

$15 ($35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 63

$14 ($34) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 63

$13 ($33) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 63

$12 ($32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 63

$11 ($31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 63

$10 ($30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 63

$0F ($2F) SPDR SPI Data Register 135

$0E ($2E) SPSR SPIF WCOL – – – – – SPI2X 134

$0D ($2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 133

$0C ($2C) UDR USART I/O Data Register 156

$0B ($2B) UCSRA RXC TXC UDRE FE DOR PE U2X MPCM 157

$0A ($2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 158

$09 ($29) UBRRL USART Baud Rate Register Low Byte 161

$08 ($28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 195

$07 ($27) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 211

$06 ($26) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 213

$05 ($25) ADCH ADC Data Register High Byte 214

$04 ($24) ADCL ADC Data Register Low Byte 214

$03 ($23) TWDR Two-wire Serial Interface Data Register 176

$02 ($22) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 176

298 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Notes: 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debug-ger specific documentation for details on how to use the OCDR Register.

2. Refer to the USART description for details on how to access UBRRH and UCSRC.3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.4. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructionswork with registers $00 to $1F only.

$01 ($21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 175

$00 ($20) TWBR Two-wire Serial Interface Bit Rate Register 174

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

2992466E–AVR–10/02

Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2

SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1

OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← $FF − Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← $00 − Rd Z,C,N,V,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FF - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← $FF None 1

MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2

MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2

MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2

FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC ← Z None 2

JMP k Direct Jump PC ← k None 3

RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3

ICALL Indirect Call to (Z) PC ← Z None 3

CALL k Direct Subroutine Call PC ← k None 4

RET Subroutine Return PC ← STACK None 4

RETI Interrupt Return PC ← STACK I 4

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1 / 2 / 3

CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1

CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1

CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1 / 2 / 3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3

SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1 / 2 / 3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1 / 2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1 / 2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1 / 2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1 / 2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1 / 2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1 / 2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1 / 2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1 / 2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1 / 2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1 / 2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1 / 2

BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1 / 2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1 / 2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1 / 2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1 / 2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1 / 2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1 / 2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1 / 2

300 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1 / 2

BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1 / 2

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd ← Rr None 1

MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1

LDI Rd, K Load Immediate Rd ← K None 1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2

LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2

LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 2

LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2

LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd ← (k) None 2

ST X, Rr Store Indirect (X) ← Rr None 2

ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2

ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2

ST Y, Rr Store Indirect (Y) ← Rr None 2

ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2

ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2

STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr Store Indirect (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2

STS k, Rr Store Direct to SRAM (k) ← Rr None 2

LPM Load Program Memory R0 ← (Z) None 3

LPM Rd, Z Load Program Memory Rd ← (Z) None 3

LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3

SPM Store Program Memory (Z) ← R1:R0 None -

IN Rd, P In Port Rd ← P None 1

OUT P, Rr Out Port P ← Rr None 1

PUSH Rr Push Register on Stack STACK ← Rr None 2

POP Rd Pop Register from Stack Rd ← STACK None 2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2

CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1

ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← T None 1

SEC Set Carry C ← 1 C 1

CLC Clear Carry C ← 0 C 1

SEN Set Negative Flag N ← 1 N 1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Zero Flag Z ← 1 Z 1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1 I 1

CLI Global Interrupt Disable I ← 0 I 1

SES Set Signed Test Flag S ← 1 S 1

CLS Clear Signed Test Flag S ← 0 S 1

SEV Set Twos Complement Overflow. V ← 1 V 1

CLV Clear Twos Complement Overflow V ← 0 V 1SET Set T in SREG T ← 1 T 1CLT Clear T in SREG T ← 0 T 1SEH Set Half Carry Flag in SREG H ← 1 H 1


3012466E–AVR–10/02

CLH Clear Half Carry Flag in SREG H ← 0 H 1MCU CONTROL INSTRUCTIONSNOP No Operation None 1SLEEP Sleep (see specific descr. for Sleep function) None 1WDR Watchdog Reset (see specific descr. for WDR/timer) None 1BREAK Break For On-Chip Debug Only None N/A


302 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Ordering InformationSpeed (MHz) Power Supply Ordering Code Package Operation Range

8 2.7 - 5.5V ATmega16L-8ACATmega16L-8PCATmega16L-8MC

44A40P644M1

Commercial(0oC to 70oC)

ATmega16L-8AIATmega16L-8PIATmega16L-8MI

44A40P644M1

Industrial(-40oC to 85oC)

16 4.5 - 5.5V ATmega16-16ACATmega16-16PCATmega16-16MI

44A40P644M1

Commercial(0oC to 70oC)

ATmega16-16AIATmega16-16PIATmega16-16MC

44A40P644M1

Industrial(-40oC to 85oC)

Package Type

44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40P6 40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44M1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Micro Lead Frame Package (MLF)

3032466E–AVR–10/02

Packaging Information

44A

1.20(0.047) MAX

10.10(0.394) 9.90(0.386)

SQ

12.25(0.482)11.75(0.462)

SQ

0.75(0.030)0.45(0.018)

0.15(0.006)0.05(0.002)

0.20(0.008)0.09(0.004)

0˚~7˚

0.80(0.0315) BSC

PIN 1 ID

0.45(0.018)0.30(0.012)

PIN 1

*Controlling dimension: millimeter

44-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP), 10x10mm body, 2.0mm footprint, 0.8mm pitch.Dimension in Millimeters and (Inches)*JEDEC STANDARD MS-026 ACB

REV. A 04/11/2001

304 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

40P6

52.71(2.075)51.94(2.045) PIN

1

13.97(0.550)13.46(0.530)

0.38(0.015)MIN

0.56(0.022)0.38(0.015)

REF

15.88(0.625)15.24(0.600)

1.65(0.065)1.27(0.050)

17.78(0.700)MAX

0.38(0.015)0.20(0.008)

2.54(0.100)BSC

3.56(0.140)3.05(0.120)

SEATINGPLANE

4.83(0.190)MAX

48.26(1.900) REF

0º ~ 15º

40-lead, Plastic Dual InlinePackage (PDIP), 0.600" wideDimension in Millimeters and (Inches)*JEDEC STANDARD MS-011 AC

*Controlling dimension: Inches

REV. A 04/11/2001

3052466E–AVR–10/02

44M1

2325 Orchard Parkway San Jose, CA 95131

TITLE44M1, 44-pad ,7 x 7 x 1.0 mm body, lead pitch 0.50mm

Micro lead frame package (MLF)

DRAWING NO. REV BR

08/29/01

44M1

E

D2

E2

L

eb

A

A1

SE

AT

ING

PL

AN

E

TOP VIEW

BOTTOM VIEW

SIDE VIEW

Marked pin#1 identifier

PIN #1 CORNER

(*Unit of Measure = mm)COMMON DIMENSIONS

A3

SYMBOL MIN NOM MAX NOTE

E2 5.00 5.20 5.40

D2

L 0.35 0.55 0.75

b

A

5.00 5.20 5.40

0.80 0.90 1.00

0.00 0.02 0.05

0.18 0.23 0.30

0.25 REF

7.00 BSCD

A1

E 7.00 BSC

e 0.50 BSC

A3

NOTE 1. JEDEC STANDARD MO-220, Fig 1 (Saw Singulation), VKKD-1

D

306 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Erratas The revision letter in this section refers to the revision of the ATmega16 device.

ATmega16(L) Rev. G. There are no errata for this revision of ATmega16.

ATmega16(L) Rev. H. There are no errata for this revision of ATmega16.

3072466E–AVR–10/02

Data Sheet Change Log for ATmega16

This document contains a log on the changes made to the data sheet for ATmega16.

Changes from Rev. 2466B-09/01 to Rev. 2466C-03/02

All page numbers refers to this document.

1. Updated typical EEPROM programming time, Table 1 on page 18.

2. Updated typical start-up time in the following tables:

Table 3 on page 23, Table 5 on page 25, Table 6 on page 26, Table 8 on page 27,Table 9 on page 27, and Table 10 on page 28.

3. Updated Table 17 on page 40 with typical WDT Time-out.

4. Added Some Preliminary Test Limits and Characterization Data.

Removed some of the TBD’s in the following tables and pages:

Table 15 on page 35, Table 16 on page 39, Table 116 on page 272 (table removedin document review #D), “Electrical Characteristics” on page 285, Table 118 onpage 287, Table 120 on page 289, and Table 121 on page 291.

5. Updated TWI Chapter.

Added the note at the end of the “Bit Rate Generator Unit” on page 172.

6. Corrected description of ADSC bit in “ADC Control and Status Register A –ADCSRA” on page 213.

7. Improved description on how to do a polarity check of the ADC diff results in“ADC Conversion Result” on page 210.

8. Added JTAG version number for rev. H in Table 86 on page 223.

9. Added not regarding OCDEN Fuse below Table 104 on page 255.

10. Updated Programming Figures:

Figure 127 on page 257 and Figure 136 on page 268 are updated to also reflect thatAVCC must be connected during Programming mode. Figure 131 on page 264added to illustrate how to program the fuses.

11. Added a note regarding usage of the “PROG_PAGELOAD ($6)” on page 274and “PROG_PAGEREAD ($7)” on page 274.

12. Removed alternative algortihm for leaving JTAG Programming mode.

See “Leaving Programming Mode” on page 282.

13. Added Calibrated RC Oscillator characterization curves in section “ATmega16Typical Characteristics – Preliminary Data” on page 293.

14. Corrected ordering code for MLF package (16MHz) in “Ordering Information”on page 303.

15. Corrected Table 89, “Scan Signals for the Oscillators(1)(2)(3),” on page 229.

308 ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Changes from Rev. 2466C-03/02 to Rev. 2466D-09/02

1. Changed all Flash write/erase cycles from 1,000 to 10,000.

2. Updated the following tables: Table 4 on page 24, Table 15 on page 35, Table42 on page 79, Table 45 on page 105, Table 46 on page 105, Table 59 on page135, Table 67 on page 161, Table 89 on page 229, Table 101 on page 252, “DCCharacteristics” on page 285, Table 118 on page 287, Table 120 on page 289,and Table 121 on page 291.

3. Updated “Erratas” on page 307.

Changes from Rev. 2466D-09/02 to Rev. 2466E-10/02

All page numbers refer to this document.

1. DC Characteristics on pages 285-286 have been updated.

3092466E–AVR–10/02

ATmega16(L)

Table of Contents Features................................................................................................. 1

Pin Configurations................................................................................ 2

Disclaimer.............................................................................................. 2

Overview................................................................................................ 3Block Diagram ...................................................................................................... 3Pin Descriptions.................................................................................................... 4

About Code Examples.......................................................................... 5

AVR CPU Core ...................................................................................... 6Introduction ........................................................................................................... 6Architectural Overview.......................................................................................... 6ALU – Arithmetic Logic Unit.................................................................................. 7Status Register ..................................................................................................... 7General Purpose Register File ............................................................................. 8Stack Pointer ...................................................................................................... 10Instruction Execution Timing............................................................................... 11Reset and Interrupt Handling.............................................................................. 11

AVR ATmega16 Memories ................................................................. 14In-System Reprogrammable Flash Program Memory ........................................ 14SRAM Data Memory........................................................................................... 15EEPROM Data Memory...................................................................................... 16I/O Memory ......................................................................................................... 21

System Clock and Clock Options ..................................................... 22Clock Systems and their Distribution .................................................................. 22Clock Sources..................................................................................................... 23Crystal Oscillator................................................................................................. 23Low-frequency Crystal Oscillator ........................................................................ 26External RC Oscillator ........................................................................................ 26Calibrated Internal RC Oscillator ........................................................................ 27External Clock..................................................................................................... 29Timer/Counter Oscillator..................................................................................... 29

Power Management and Sleep Modes.............................................. 30Idle Mode ............................................................................................................ 31ADC Noise Reduction Mode............................................................................... 31Power-down Mode.............................................................................................. 31Power-save Mode............................................................................................... 31Standby Mode..................................................................................................... 32Extended Standby Mode .................................................................................... 32Minimizing Power Consumption ......................................................................... 33

i2466E–AVR–10/02

System Control and Reset ................................................................. 34Internal Voltage Reference ................................................................................. 39Watchdog Timer ................................................................................................. 39

Interrupts ............................................................................................. 42Interrupt Vectors in ATmega16........................................................................... 42

I/O Ports............................................................................................... 47Introduction ......................................................................................................... 47Ports as General Digital I/O ................................................................................ 48Alternate Port Functions ..................................................................................... 52Register Description for I/O Ports ....................................................................... 62

External Interrupts.............................................................................. 64

8-bit Timer/Counter0 with PWM......................................................... 67Overview............................................................................................................. 67Timer/Counter Clock Sources............................................................................. 68Counter Unit........................................................................................................ 68Output Compare Unit.......................................................................................... 69Compare Match Output Unit ............................................................................... 70Modes of Operation ............................................................................................ 71Timer/Counter Timing Diagrams......................................................................... 758-bit Timer/Counter Register Description ........................................................... 77

Timer/Counter0 and Timer/Counter1 Prescalers ............................. 81

16-bit Timer/Counter1......................................................................... 83Overview............................................................................................................. 83Accessing 16-bit Registers ................................................................................. 86Timer/Counter Clock Sources............................................................................. 88Counter Unit........................................................................................................ 88Input Capture Unit............................................................................................... 90Output Compare Units ........................................................................................ 91Compare Match Output Unit ............................................................................... 93Modes of Operation ............................................................................................ 94Timer/Counter Timing Diagrams....................................................................... 10216-bit Timer/Counter Register Description ....................................................... 104

8-bit Timer/Counter2 with PWM and Asynchronous Operation ... 111Overview........................................................................................................... 111Timer/Counter Clock Sources........................................................................... 112Counter Unit...................................................................................................... 112Output Compare Unit........................................................................................ 113Compare Match Output Unit ............................................................................. 114Modes of Operation .......................................................................................... 115

ii ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Timer/Counter Timing Diagrams....................................................................... 1198-bit Timer/Counter Register Description ......................................................... 121Asynchronous Operation of the Timer/Counter ................................................ 124Timer/Counter Prescaler................................................................................... 127

Serial Peripheral Interface – SPI...................................................... 129SS Pin Functionality.......................................................................................... 132Data Modes ...................................................................................................... 135

USART ............................................................................................... 137Overview........................................................................................................... 137Clock Generation .............................................................................................. 138Frame Formats ................................................................................................. 141USART Initialization.......................................................................................... 143Data Transmission – The USART Transmitter ................................................. 144Data Reception – The USART Receiver .......................................................... 147Asynchronous Data Reception ......................................................................... 150Multi-processor Communication Mode ............................................................. 154Accessing UBRRH/ UCSRC Registers............................................................. 155USART Register Description ............................................................................ 156Examples of Baud Rate Setting........................................................................ 162

Two-wire Serial Interface ................................................................. 166Features............................................................................................................ 166Two-wire Serial Interface Bus Definition........................................................... 166Data Transfer and Frame Format ..................................................................... 167Multi-master Bus Systems, Arbitration and Synchronization ............................ 169Overview of the TWI Module ............................................................................ 172TWI register description.................................................................................... 174Using the TWI ................................................................................................... 177Transmission Modes......................................................................................... 180Multi-master Systems and Arbitration............................................................... 193

Analog Comparator .......................................................................... 195Analog Comparator Multiplexed Input .............................................................. 197

Analog to Digital Converter ............................................................. 198Features............................................................................................................ 198Operation .......................................................................................................... 199Starting a Conversion ....................................................................................... 200Prescaling and Conversion Timing ................................................................... 201Changing Channel or Reference Selection ...................................................... 204ADC Noise Canceler......................................................................................... 206ADC Conversion Result.................................................................................... 210

iii2466E–AVR–10/02

JTAG Interface and On-chip Debug System .................................. 216Features............................................................................................................ 216Overview........................................................................................................... 216Test Access Port – TAP.................................................................................... 216TAP Controller .................................................................................................. 218Using the Boundary-scan Chain ....................................................................... 219Using the On-chip Debug System .................................................................... 219On-chip Debug Specific JTAG Instructions ...................................................... 220On-chip Debug Related Register in I/O Memory .............................................. 221Using the JTAG Programming Capabilities ...................................................... 221Bibliography ...................................................................................................... 221

IEEE 1149.1 (JTAG) Boundary-scan ............................................... 222Features............................................................................................................ 222System Overview.............................................................................................. 222Data Registers .................................................................................................. 222Boundary-scan Specific JTAG Instructions ...................................................... 224Boundary-scan Chain ....................................................................................... 226ATmega16 Boundary-scan Order..................................................................... 236Boundary-scan Description Language Files ..................................................... 240

Boot Loader Support – Read-While-Write Self-Programming...... 241Features............................................................................................................ 241Application and Boot Loader Flash Sections .................................................... 241Read-While-Write and no Read-While-Write Flash Sections ........................... 241Boot Loader Lock Bits....................................................................................... 243Entering the Boot Loader Program................................................................... 244Addressing the Flash during Self-Programming ............................................... 246Self-Programming the Flash ............................................................................. 247

Memory Programming...................................................................... 254Program And Data Memory Lock Bits .............................................................. 254Fuse Bits........................................................................................................... 255Signature Bytes ................................................................................................ 256Calibration Byte ................................................................................................ 256Parallel Programming Parameters, Pin Mapping, and Commands .................. 257Parallel Programming ....................................................................................... 259SPI Serial Downloading .................................................................................... 268SPI Serial Programming Pin Mapping .............................................................. 268Programming via the JTAG Interface ............................................................... 272

Electrical Characteristics................................................................. 285Absolute Maximum Ratings*............................................................................. 285DC Characteristics............................................................................................ 285External Clock Drive Waveforms ...................................................................... 287External Clock Drive ......................................................................................... 287

iv ATmega16(L) 2466E–AVR–10/02

ATmega16(L)

Two-wire Serial Interface Characteristics ......................................................... 288SPI Timing Characteristics ............................................................................... 289

ADC Characteristics – Preliminary Data......................................... 291

ATmega16 Typical Characteristics – Preliminary Data................. 293

Register Summary ............................................................................ 298

Instruction Set Summary ................................................................. 300

Ordering Information........................................................................ 303

Packaging Information ..................................................................... 30444A ................................................................................................................... 30440P6 ................................................................................................................. 30544M1................................................................................................................. 306

Erratas ............................................................................................... 307ATmega16(L) Rev. G........................................................................................ 307ATmega16(L) Rev. H........................................................................................ 307

Data Sheet Change Log for ATmega16 .......................................... 308Changes from Rev. 2466B-09/01 to Rev. 2466C-03/02 ................................... 308Changes from Rev. 2466C-03/02 to Rev. 2466D-09/02................................... 309

Table of Contents .................................................................................. i

v2466E–AVR–10/02

Printed on recycled paper.

© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warrantywhich is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errorswhich may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and doesnot make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are grantedby the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as criticalcomponents in life support devices or systems.

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2466E–AVR–10/02 0M

ATMEL®, AVR®, and AVR Studio® are the registered trademarks of Atmel.

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Revision 1.0 MultiMediaCard/RS-MultiMediaCard Product Manual

© 2004 SanDisk Corporation i 5/13/2004

SanDisk® Corporation general policy does not recommend the use of its products in life support applications where in a failure or malfunction of the product may directly threaten life or injury. Per SanDisk Terms and Conditions of Sale, the user of SanDisk products in life support applications assumes all risk of such use and indemnifies SanDisk against all damages. See “Disclaimer of Liability.”

This document is for information use only and is subject to change without prior notice. SanDisk Corporation assumes no responsibility for any errors that may appear in this document, nor for incidental or consequential damages resulting from the furnishing, performance or use of this material. No part of this document may be reproduced, transmitted, transcribed, stored in a retrievable manner or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without the prior written consent of an officer of SanDisk Corporation.

All parts of the SanDisk documentation are protected by copyright law and all rights are reserved.

SanDisk and the SanDisk logo are registered trademarks of SanDisk Corporation. CompactFlash is a U.S. registered trademark of SanDisk Corporation.

Product names mentioned herein are for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

© 2004 SanDisk Corporation. All rights reserved.

SanDisk products are covered or licensed under one or more of the following U.S. Patent Nos. 5,070,032; 5,095,344; 5,168,465; 5,172,338; 5,198,380; 5,200,959; 5,268,318; 5,268,870; 5,272,669; 5,418,752; 5,602,987. Other U.S. and foreign patents awarded and pending.

Lit. No. 80-36-00320 Rev.1.0 05/04 Printed in U.S.A.

Revision History April 2004 Revision 0.1—Initial release April 2004 Revision 0.2—Minor edits and addition of RS-MMC physical dimensions May 2004 Revision 1.0—Added document number and updated to v1.0 release

Table of Contents Revision 1.0 MultiMediaCard/RS-MultiMediaCard Product Manual

© 2004 SanDisk Corporation ii 05/13/04

TABLE OF CONTENTS 1. Introduction...................................................................................................1-1

1.1 General Description................................................................................1-1 1.2 Features...................................................................................................1-2 1.3 Document Scope.....................................................................................1-2 1.4 Product Models.......................................................................................1-2 1.5 MultiMediaCard Standard ......................................................................1-2 1.6 Functional Description............................................................................1-3 1.7 Flash Independent Technology ...............................................................1-3 1.8 Defect and Error Management................................................................1-3 1.9 Endurance ...............................................................................................1-4 1.10 Automatic Sleep Mode .........................................................................1-4 1.11 Hot Insertion ..........................................................................................1-4 1.12 MultiMediaCard Mode ..........................................................................1-4 1.13 SPI Mode ...............................................................................................1-9

2. Product Specifications...................................................................................2-1 2.1 Overview ................................................................................................2-1 2.2 System Environmental Specifications ....................................................2-1 2.3 System Power Requirements ..................................................................2-2 2.4 System Performance ...............................................................................2-2 2.5 System Reliability and Maintenance ......................................................2-2 2.6 Physical Specifications ...........................................................................2-3 2.7 Capacity Specifications ..........................................................................2-4

3. Interface Description.....................................................................................3-1 3.1 Physical Description ...............................................................................3-1 3.2 MultiMediaCard/RS-MultiMediaCard Bus Topology ............................3-2 3.3 SPI Bus Topology ...................................................................................3-3 3.4 Electrical Interface..................................................................................3-4 3.5 MultiMediaCard/RS-MultiMediaCard Registers....................................3-9 3.6 File System Format...............................................................................3-21

4. MultiMediaCard Protocol Description..........................................................4-1

4.1 Card Identification Mode........................................................................4-2 4.2 Data Transfer Mode ................................................................................4-4 4.3 Clock Control .......................................................................................4-11 4.4 Cyclic Redundancy Codes....................................................................4-11 4.5 Error Conditions ...................................................................................4-13 4.6 Commands............................................................................................4-14 4.7 Card State Transition ............................................................................4-19 4.8 Timing Diagrams ..................................................................................4-22 4.9 Data Read .............................................................................................4-24 4.10Data Write.............................................................................................4-25 4.11Timing Values .......................................................................................4-27

5. SPI Mode.......................................................................................................5-1 5.1 SPI Interface Concept .............................................................................5-1 5.2 SPI Bus Topology ...................................................................................5-1 5.3 Card Registers in SPI Mode ...................................................................5-3 5.4 SPI Bus Protocol.....................................................................................5-3 5.5 Mode Selection .......................................................................................5-3 5.6 Bus Transfer Protection ..........................................................................5-4 5.7 Data Read ...............................................................................................5-4

Table of Contents Revision 1.0 MultiMediaCard/RS-MultiMediaCard Product Manual

© 2004 SanDisk Corporation iii 05/13/04

5.8 Data Write...............................................................................................5-5 5.9 Erase and Write Protect Management.....................................................5-7 5.10 Read CSD/CID Registers ......................................................................5-7 5.11 Reset Sequence ......................................................................................5-7 5.12 Clock Control ........................................................................................5-8 5.13 Error Conditions ....................................................................................5-8 5.14 Read Ahead in Multiple Block Operation..............................................5-9 5.15 Memory Array Partitioning....................................................................5-9 5.16 Card Lock/Unlock Operation.................................................................5-9 5.17 SPI Command Set..................................................................................5-9 5.18 Responses ............................................................................................5-13 5.19 Data Tokens .........................................................................................5-15 5.20 Data Token Error .................................................................................5-16 5.21 Clearing Status Bits .............................................................................5-16 5.22 Card Registers......................................................................................5-18 5.23 SPI Bus Timing Diagrams ...................................................................5-18 5.24 Timing Values ......................................................................................5-21 5.25 SPI Electrical Interface ........................................................................5-21 5.26 SPI Bus Operation Conditions.............................................................5-21 5.27 SPI Bus Timing....................................................................................5-21 Appendix A Ordering Information...............................................................A-1 Appendix B SanDisk Worldwide Sales Offices........................................... B-1 Appendix C Limited Warranty..................................................................... C-1 Appendix D Disclaimer of Liability ............................................................D-1

Chapter 1 – Introduction Revision 1.0 MultiMediaCard/RS-MultiMediaCard Product Manual

© 2004 SanDisk Corporation 1-1 05/13/04

1 Introduction

1.1 General Description

The SanDisk MultiMediaCard and Reduced-Size MultiMediaCard (RS-MMC) are very small, removable flash storage devices, designed specifically for storage applications that put a premium on small form factor, low power and low cost. Flash is the ideal storage medium for portable, battery-powered devices. It features low power consumption and is non-volatile, requiring no power to maintain the stored data. It also has a wide operating range for temperature, shock and vibration.

The MultiMediaCard and RS-MultiMediaCard are well suited to meet the needs of small, low power, electronic devices. With form factors of 32 mm x 24 mm and 1.4 mm thick for the MultiMediaCard and 18 mm x 24 mm x1.4 mm for the RS-MultiMediaCard, these cards can be used in a wide variety of portable devices like mobile phones, and voice recorders.

To support this wide range of applications, the MultiMediaCard Protocol, a simple seven- pin serial interface, is designed for maximum scalability and configurability. All device and interface configuration data (such as maximum frequency, card identification, etc.) are stored on the card.

The SanDisk MultiMediaCard/RS-MultiMediaCard interface allows for easy integration into any design, regardless of microprocessor used. For compatibility with existing controllers, the card offers, in addition to the card interface, an alternate communication protocol, which is based on the Serial Peripheral Interface (SPI) standard.

The MultiMediaCard/RS-MultiMediaCard provides up to 256 million bytes of memory using SanDisk Flash memory chips, which were designed by SanDisk especially for use in mass storage applications. In addition to the mass storage specific flash memory chip, the MultiMediaCard/RS-MultiMediaCard includes an on-card intelligent controller which manages interface protocols and data storage and retrieval, as well as Error Correction Code (ECC) algorithms, defect handling and diagnostics, power management and clock control.

Figure 1-1 MultiMediaCard/RS-MultiMediaCard Block Diagram

SanDiskFlash Cards

SanDiskSingle ChipController Control

Data In/OutMMC/SPI BusInterface

SanDisk MultiMediaCard/RS-MultiMediaCard



1.2 Features

The SanDisk MultiMediaCard/RS-MultiMediaCard features include: MultiMediaCard Protocol compatible

SPI Mode supported

Targeted for portable and stationary applications

Voltage range

Basic communication: 2.7 to 3.6 V

Memory access: 2.7 to 3.6 V

Maximum data rate with up to 10 cards

Correction of memory field errors

Built-in write protection features (permanent and temporary)

Pre-erase mechanism

Variable clock rate 0 - 20 Mhz

Multiple cards stackable on a single physical bus

1.3 Document Scope

This document describes the key features and specifications of the SanDisk MultiMediaCard (full-size) and RS-MultiMediaCard (reduced-size), as well as the information required to interface this product to a host system. Retail card specifications are not covered in this manual.

1.4 Product Models

The SanDisk MultiMediaCard and RS-MultiMediaCard is available in a variety of capacities as shown in Table 2-6, Chapter 2: Product Specifications. The MultiMediaCard is available in full-size and reduced-size (RS-MMC) form factors.

1.5 MultiMediaCard Standard

MultiMediaCards and RS-MultiMediaCards are fully compatible with the MultiMediaCard standard specification listed below:

The MultiMediaCard System Specification, Version 3.3

This specification may be obtained from: MultiMediaCard Association 19672 Stevens Creek Blvd., Suite 404 Cupertino, CA 95014-2465 USA Phone: 408-253-0441 Fax: 408-253-8811 Email: [email protected] http://www.mmca.org



1.6 Functional Description

The MultiMediaCard and RS-MultiMediaCard contain a high level, intelligent subsystem as shown by the block diagram in Figure 1-1. This intelligent (microprocessor) subsystem provides many capabilities not found in other types of memory cards. These capabilities include: • Host independence from details of erasing and programming flash memory • Sophisticated system for managing defects (analogous to systems found in magnetic

disk drives) • Sophisticated system for error recovery including a powerful error correction code • Power management for low power operation

1.7 Flash-Independent Technology

The 512-byte sector size of the MultiMediaCard and RS-MultiMediaCard is the same as that in an IDE magnetic disk drive. To write or read a sector (or multiple sectors), the host computer software simply issues a read or write command to the card. This command contains the address. The host software then waits for the command to complete. The host software does not get involved in the details of how the flash memory is erased, programmed or read. This is extremely important as flash devices are expected to get more and more complex in the future. Because the MultiMediaCard and RS-MultiMediaCard uses an intelligent on-board controller, the host system software will not require changing as new flash memory evolves. In other words, systems that support the SanDisk MultiMediaCard/RS-MultiMediaCard today will be able to access future cards built with new flash technology without having to update or change host software.

1.8 Defect and Error Management

The SanDisk MultiMediaCard and RS-MultiMediaCard contain a sophisticated defect and error management system. This system is analogous to the systems found in magnetic disk drives and in many cases offers enhancements. For example, disk drives do not typically perform a read after write to confirm the data is written correctly because of the performance penalty that would be incurred. MultiMediaCards and RS-MultiMediaCards do a read after write under margin conditions to verify that the data is written correctly. In the rare case that a bit is found to be defective, the cards replace it with a spare bit within the sector header. If necessary, the card will replace the entire sector with a spare sector. This is completely transparent to the host and does not consume any user data space.

The card’s soft error rate specification is much better than the magnetic disk drive specification. In the extremely rare case a read error does occur, a SanDisk MultiMediaCard/RS-MultiMediaCard possesses innovative algorithms to recover the data. This is similar to using retries on a disk drive but is much more sophisticated.

The last line of defense is to employ a powerful ECC to correct the data. If ECC is used to recover data, defective bits are replaced with spare bits to ensure they do not cause any future problems. These defect and error management systems coupled with the solid-state construction give SanDisk MultiMediaCards and RS-MultiMediaCards unparalleled reliability.



1.9 Endurance

The SanDisk MultiMediaCard and RS-MultiMediaCard have a typical endurance specification for each sector of 100,000 writes (reading a logical sector is unlimited). This far exceeds what is required in nearly all card applications. For example, very heavy use of the MultiMediaCard/RS-MultiMediaCard in cellular phones, personal communicators, pagers and voice recorders will use only a fraction of the total endurance over the device’s typical lifetime. That means it would take over 34 years to wear out an area of the card on which a file of any size (from 512 bytes to maximum capacity) was rewritten 3 times per hour, 8 hours a day, 365 days per year. However, for the vast majority of users employing typical applications, the endurance limit is not of any practical concern.

1.10 Automatic Sleep Mode

A unique feature of the SanDisk MultiMediaCard/RS-MultiMediaCard is automatic entrance and exit from sleep mode. Upon completion of an operation, the card enters the sleep mode to conserve power if subsequent commands are not received within five milliseconds. The host does not have to take any action for this to occur. In most systems, the MultiMediaCard/RS-MultiMediaCard are in sleep mode except when the host is accessing them, thus conserving power.

When the host is ready to access the card in sleep mode, any command issued to it will cause the exit from sleep and respond.

1.11 Hot Insertion

Support for hot insertion will be required on the host but will be supported through the connector. Connector manufacturers will provide connectors that have power pins long enough to be powered before contact is made with the other pins. This approach is similar to that used in PCMCIA and MMCA devices to allow for hot insertion and applies to MultiMediaCard and SPI modes.

1.12 MultiMediaCard Mode

The following sections provide valuable information on the MultiMediaCard and RS-MultiMediaCard in MultiMediaCard mode.

1.12.1 MultiMediaCard Standard Compliance

The MultiMediaCard and RS-MultiMediaCard are fully compliant with the MultiMediaCard Standard Specification, v3.3. The structure of the Card Specific Data (CSD) Register is compliant with CSD Structure v1.2.

1.12.2 Negotiating Operating Conditions

The MultiMediaCard and RS-MultiMediaCard support the operation condition verification sequence defined in the MultiMediaCard Standard Specification, v3.3. If the host defines an operating voltage range not supported by the card, the card will go into an inactive state and ignore any bus communication. The only way to get a card out of an inactive state is by powering the card down and up again.



In addition, the host can explicitly send either card to an inactive state by using the GO_INACTIVE_STATE command.

1.12.3 Card Acquisition and Identification

The MultiMediaCard and RS-MultiMediaCard bus is a single master (host application) and multi-slaves (cards) bus. The host can query the bus and determine how many cards, and of which type, are connected. The card’s CID Register is pre-programmed with a unique card identification number used during the identification procedure.

In addition, the card host can read either card’s CID Register using the READ_CID command. The CID Register is programmed during MultiMediaCard and RS-MultiMediaCard testing and formatting procedures during manufacturing. The card host can only read, and not write to the CID Register.

1.12.4 Card Status

The MultiMediaCard and RS-MultiMediaCard status is stored in a 32-bit status register that is sent as the data field, in the card response to host commands. The Status Register provides information about the card’s active state and completion codes for the last host command

The card status can be explicitly polled with the SEND_STATUS command.

1.12.5 Memory Array Partitioning

The MultiMediaCard/RS-MultiMediaCard memory space is byte addressable with addresses ranging from 0 to the last byte, and is divided into several structures.

Memory bytes are grouped into 512-byte blocks called sectors. Every block can be read, written and erased individually. Sectors are grouped into erase groups of 16 or 32 sectors depending on card size. Any combination of sectors within one group, or any combination of erase groups can be erased with a single erase command. A write command implicitly erases the memory before writing new data into it. An explicit erase command can be used for pre-erasing memory and speed up the next write operation. Erase groups are grouped into Write Protect Groups (WPG) of 32 erase groups. The write/erase access to each WPG can be limited individually. The last (highest in address) WPG will be smaller and contain less than 32 erase groups.

A diagram of the memory structure hierarchy is shown in Figure 1-2. Table 1-1 summarizes the number of various memory structures for the different MultiMediaCards and RS-MultiMediaCards.



Figure 1-2 Memory Array Partitioning

Table 1-1 Memory Array Structures Summary1

Structure SDMJ-32 SDMRJ-32

SDMJ-64 SDMRJ-64

SDMJ-128 SDMRJ-128

SDMJ-256* SDMRJ-256*

Bytes 32 MB 64 MB 128 MB 256 MBSector 62,720 125,440 250,880 501,760

Erase Group Size [sectors] 32 32 32 32

Number of Erase Groups 1,960 3,920 7,840 15,680

Write Protect Group Size [erase groups] 32 32 32 32

Number of Write Protect Groups 62 123 245 490

*Available 2nd Half 2004

1 All measurements are units-per-card.

SanDisk MMC/RS-MMC Card

WP Group N

WP Group 1

Era

se G

roup

0Sector n

Sector 0

Erase Group m

Sector n

Sector 2

Sector 1: bytes 512 - 1,023

Sector 0: bytes 0 - 511

Era

se G

roup

1

Writ

e P

rote

ct G

roup

0



1.12.6 Read and Write Operations

The MultiMediaCard/RS-MultiMediaCard support two read/write modes as shown in Figure 1-3 and defined in Table 1-2.

Figure 1-3 Data Transfer Formats

Table 1-2 Mode Definitions

Mode Description

Single Block In this mode the host reads or writes one data block in a pre-specified length. The data block transmission is protected with 16-bit CRC that is generated by the sending unit and checked by the receiving unit.

The block length for read operations is limited by the device sector size (512 bytes) but can be as small as a single byte. Misalignment is not allowed. Every data block must be contained in a single physical sector.

The block length for write operations must be identical to the sector size and the start address aligned to a sector boundary.

Multiple Block This mode is similar to the single block mode, except for the host can read/write multiple data blocks (all have the same length) that are stored or retrieved from contiguous memory addresses starting at the address specified in the command. The operation is terminated with a stop transmission command.

Misalignment and block length restrictions apply to multiple blocks and are identical to the single block read/write operations.

1.12.7 Data Protection in the Flash Card

Every sector is protected with an error correction code. The ECC is generated (in the memory card) when the sectors are written and validated when the data is read. If defects are found, the data is corrected prior to transmission to the host.

Multiple Block Mode

MemorySectors

MemorySectors

MemorySectors

MemorySectors

MemorySectors

MemorySectors

MemorySectors

MemorySectors

MemorySectors

MemorySectors

MemorySectors

MemorySectors

MemorySectors

MemorySectors

Start Address(Write)

Start Address(Read/Write)

Start Address(Read)

Write

Start Address Stop Start

Read

Stop

Single Block Mode Misalignment Error



1.12.8 Erase

The smallest erasable unit in the MultiMediaCard/RS-MultiMediaCard is a sector. In order to speed up the erase procedure, multiple sectors can be erased at the same time. The erase operation is divided into two stages as shown in Table 1-3.

Table 1-3 Erase Operation Stages

Stage Name Description

1 Tagging Selecting the Sectors for Erasing. To facilitate selection, a first command with the starting address is followed by a second command with the final address, and all sectors within this range will be selected for erase.

2 Erasing Starting the Erase Process. The sectors are grouped into erase groups of 16 or 32 sectors. Tagging can address sectors or erase groups. Either an arbitrary set of sectors within a single erase group, or an arbitrary selection of erase groups may be erased at one time, but not both together. That is, the unit of measure for determining an erase is either a sector or an erase group. If sectors are tagged, then all selected sectors must lie within the same erase group. Tagging and erasing sectors must follow a strict command sequence.

1.12.9 Write Protection

Two-card level write-protection options are available: permanent and temporary. Both can be set using the PROGRAM_CSD command (refer to CSD Programming, Section 4.2.3). The permanent write protect bit, once set, cannot be cleared. This feature is implemented in the MultiMediaCard /RS-MultiMediaCard controller firmware and not with a physical OTP cell.

1.12.10 Copy Bit

MultiMediaCard/RS-MultiMediaCard content can be marked as an original or a copy using the copy bit. The copy bit of the card is programmed as a copy when testing and formatting are performed during manufacturing. When set, the copy bit in the CSD Register is a copy and cannot be cleared.

The card is available with the copy bit set or cleared. The bit set indicates that the card is a master. This feature is implemented in the card’s controller firmware and not with a physical OTP cell.

1.12.11 CSD Register

All MultiMediaCard/RS-MultiMediaCard configuration information is stored in the CSD register. The MSB bytes of the register contain manufacturer data and the two least significant bytes contain the host-controlled data: the card copy/write protection, the user file format indication and ECC Register.

The host can read the CSD Register and alter the host-controlled data bytes using the SEND_CSD and PROGRAM_CSD commands.



1.13 SPI Mode The SPI mode is a secondary communication protocol for the MultiMediaCard and RS-MultiMediaCard. This mode is a subset of the MultiMediaCard Protocol, designed to communicate with an SPI channel, commonly found in Motorola and other vendors’ microcontrollers.

Table 1-4 SPI Mode

Function Description

Negotiating Operating Conditions The operating condition negotiation function of the MultiMediaCard/RS-MMC bus is not supported in SPI Mode. The host must work within the valid voltage range, 2.7 to 3.6 V, of the card.

Card Acquisition and Identification This function is not supported in SPI Mode. The host must know the number of cards currently connected on the bus. Specific card selection is done using the CS signal.

Card Status In SPI mode, only 16 bits containing errors relevant to SPI mode can be read out of the 32-bit Status Register.

Memory Array Partitioning Memory partitioning in SPI mode is equivalent to MultiMediaCard mode. All read and write commands are byte addressable.

Read/Write Operations In SPI mode, single and multiple block data transfers are supported. Stream mode is not supported.

Data Transfer Rate Same as MultiMediaCard mode.

Data Protection in MultiMediaCard/RS-MultiMediaCard

Same as MultiMediaCard mode.

Erase Same as MultiMediaCard mode.

Write Protection Same as MultiMediaCard mode.

Chapter 2 – Product Specifications Revision 1.0 MultiMediaCard/RS-MultiMediaCard Product Manual


2 Product Specifications

2.1 Overview In this section, all values are defined at an ambient temperature and nominal supply voltage unless otherwise stated.

2.2 System Environmental Specifications Table 2-1 defines the environmental specifications for the SanDisk MultiMediaCard and RS-MultiMediaCard.

Table 2-1 Environmental Specification Summary

Operating -25° C to 85° C Temperature

Non-operating -40° C to 85° C

Operating 8% to 95%, non condensing Humidity

Non-operating 8% to 95%, non condensing

Acoustic Noise 0 dB

Contact Pads +/- 4kV, Human body model according to ANSI EOS/ESD-S5.1-1998

ESD Protection

Non Contact Pad Area +/- 8kV (coupling plane discharge) +/- 15kV (air discharge) Human body model per IEC61000-4-2.

Operating 15 G peak-to-peak max. Vibration

Non-operating 15 G peak-to-peak max.

Operating 1,000 G max. Shock

Non-operating 1,000 G max.

Operating 80,000 ft. max. Altitude1

Non-operating 80,000 ft. max.

1 Relative to sea level.



2.3 System Power Requirements All values quoted in Table 2-2 are at room temperature unless otherwise stated.

Table 2-2 System Power Requirements

Operation Max. Power Dissipation @3.6 V

Read 50 mA

Write 60 mA

Sleep 150 uA

2.4 System Performance All performance values for the MultiMediaCard and RS-MultiMediaCard in Table 2-3 are under the following conditions: • Voltage range 2.7 V to 3.6 V • Temperature -25° C to 85° C • Independent of the MMC clock frequency

Table 2-3 Performance

Timing Typical Maximum

Block Read Access Time 0.5 ms 100 ms

Block Write Access Time 0.5 ms 240 ms

CMD1 to Ready after Power-up 50 ms 500 ms

Sleep to Ready 1 ms 2 ms

2.5 System Reliability and Maintenance Table 2-4 Reliability and Maintenance Summary

MTBF >1,000,000 hours

Preventative Maintenance None

Data Reliability <1 non-recoverable error in 1014 bits read

Endurance 100,000 write and erase cycles (typical)



2.6 Physical Specifications Refer to Table 2-5 and Figure 2-1 for MultiMediaCard, and Figure 2-2, Table 2-6 for RS-MultiMediaCard physical specifications and dimensions.

Table 2-5 MultiMediaCard Physical Specification Summary

Specification MultiMediaCard

Weight 1.8 g maximum

Length 32 mm ± 0.1 mm

Width 24 mm ± 0.08 mm

Thickness 1.4 mm ± 0.1 mm

Figure 2-1 Full-size MultiMediaCard Dimensions

24.00 ± 0.08

3 x R1.0 ± 0.1

4.0 ± 0.1

2 x R0.5 ± 0.1

4.0 ± 0.1

32.0 ± 0.1

4.5 min.

1.2 max.

0.00

3.10 max.4.65 min.

5.60 max.

7.15 min.8.10 max.

9.65 min.10.60 max.

12.15 min.13.10 max.

14.65 min.15.60 max.

17.15 min.18.10 max.

19.65 min.

1.4 ± 0.1

All dimensions are in millimeters.

0.2



Table 2-6 RS-MultiMediaCard Physical Specification Summary

Specification RS-MMC

Weight 1.0 g maximum

Length 18 mm ± 0.1 mm

Width 24 mm ± 0.08 mm

Thickness 1.4 mm ± 0.1 mm

Figure 2-2 Reduced-size MultiMediaCard Dimensions

2.7 Capacity Specifications Table 2-7 shows the specific capacity for the various models.

Table 2-7 Model Capacity Summary

Model No. Form Factor Capacity

SDMJ-32 Full-size MultiMediaCard 32 MB



SDMJ-256 Full-size MultiMediaCard 256 MB*

SDMRJ-32 Reduced-size MultiMediaCard 32 MB



SDMRJ-256 Reduced-size MultiMediaCard 256 MB*


Chapter 3 –Interface Description Revision 1.0 MultiMediaCard and RS-MultiMediaCard Product Manual


3 Interface Description

3.1 Physical Description

The MultiMediaCard and RS-MultiMediaCard has seven exposed contacts on one side. The host is connected to the card using a dedicated seven-pin connector.

3.1.1 Pin Assignments

Table 3-1 MultiMediaCard and RS-MultiMediaCard Pad Assignment

Pin No. Name Type1 Description

MultiMediaCard Mode

1 RSV NC Not connected or Always “1”

2 CMD I/O, PP, OD Command/Response

3 VSS1 S Supply Voltage Ground

4 VDD S Supply Voltage

5 CLK I Clock


7 DAT0 I/O, PP Data 0

SPI Mode

1 CS I Chip Select (active low)

2 DataIn I Host-to-card Commands and Data


4 VDD S Supply Voltage

5 CLK I Clock


7 DataOut O Card-to-host Data and Status

1 Type Key: S=power supply; I=input; O=output using push-pull drivers; PP=I/O using push-pull drivers



3.2 MultiMediaCard/RS-MultiMediaCard Bus Topology

The MultiMediaCard/RS-MultiMediaCard Bus has three communication lines and four supply lines. • CMD • DAT • CLK • VDD • VSS[1:2] The description of each signal is contained in Table 3-2.

Table 3-2 Bus Signal Descriptions

Name Description

CMD Command is a bi-directional signal. Host and card drivers are operating in two modes: open drain and push-pull.

DAT Data line is a bi-directional signal. Host and card drivers are operating in push-pull mode.

CLK Clock is a host to card signal. CLK operates in push-pull mode.

VDD VDD is the power supply line for all cards.

VSS [1:2] VSS are two ground lines.

Figure 3-1 shows the bus circuitry with one host in MultiMediaCard mode.

Figure 3-1 Bus Circuitry Diagram

The ROD is switched on and off by the host synchronously to the open-drain and push-pull mode transitions. RDAT and RCMD are pull-up resistors protecting the CMD and DAT line against bus floating when no card is inserted or all card drivers are in a hi-impedance mode.

A constant current source can replace the ROD in order to achieve better performance (constant slopes for the signal rising and falling edges). If the host does not allow the switchable ROD implementation, a fixed RCMD can be used. Consequently the maximum operating frequency in the open-drain mode has to be reduced in this case.



3.2.1 Hot Insertion and Removal

Hot insertion and removal are allowed; inserting or removing the card into or from the MultiMediaCard bus will not damage the card. This also applies when the power is up.

Data transfer operations are protected by CRC codes; therefore, the bus master can detect any bit changes induced by hot insertion and removal. The inserted card will be properly reset when CLK carries a clock frequency (fpp).

3.2.2 Power Protection

Cards can be inserted or removed to and from the bus without damage, however if one of the supply pins (VDD or VSS) is not connected properly, the current is drawn through a data line to supply the card.

If the hot insertion feature is implemented in the host, the host must withstand a shortcut between VDD and VSS without damage.

3.3 SPI Bus Topology

The MultiMediaCard/RS-MultiMediaCard SPI Interface is compatible with SPI hosts available on the market. Similar to any other SPI device, the card’s SPI channel consists of the following four signals: • CS—Host-to-card Chip Select signal • CLK—Host-to-card Clock signal • DataIn—Host-to-card Data signal • DataOut—Card-to-host Data signal Another SPI common characteristic implemented in the MultiMediaCard and RS-MultiMediaCard are byte transfers. All data tokens are multiples of 8-bit bytes and always byte-aligned to the CS signal. The SPI standard defines the physical link only and not the complete data transfer protocol. In SPI Bus mode, the card uses a subset of the MultiMediaCard Protocol and command set.

The card identification and addressing algorithms are replaced by the hardware CS signal. There are no broadcast commands. A card (slave) is selected for every command by asserting the CS signal (active low). Refer to Figure 3-2.

The CS signal must be continuously active for the duration of the SPI transaction (command, response and data). The only exception is card-programming time. At this time the host can de-assert the CS signal without affecting the programming process.

The bi-directional CMD and DAT lines are replaced by unidirectional dataIn and dataOut signals. This eliminates the ability to execute commands while data is being read or written which prevents sequential multi read/write operations. Only single block read/write is supported by the SPI channel.



Figure 3-2 MultiMediaCard and RS-MultiMediaCard Bus System

3.3.1 Power Protection

Power protection is the same as it is in MultiMediaCard mode.

3.4 Electrical Interface

The following sections provide valuable information about the electrical interface.

3.4.1 Power Up The power-up of the MultiMediaCard/RS-MultiMediaCard bus is handled locally in each card and the bus master. See Figure 3-3.

SPI Bus Master

SPI Card SPI Card

Power Supply

SPI Bus (CLK, DataIn, DataOut)

CS

CS



Figure 3-3 Power-up Diagram

After power up, including hot insertion2 the card enters an idle state and ignores all bus transactions until CMD1 is received.

CMD1 is a special synchronization command used to negotiate the operation voltage range and to poll the cards until they are out of their power-up sequence. Besides the operation voltage profile of the cards, the response to CMD1 contains a busy flag, indicating that the card is still working on its power-up procedure and not ready for identification. This bit informs the host that the card is not ready. The host must wait, while continuing to poll the cards, until this bit is cleared. The MultiMediaCard/RS-MultiMediaCard initialization sequence will be completed within 500 ms.

The bus master has the task of getting the individual cards and the entire card system out of idle state. Because the power-up and the supply ramp-up time depend on application parameters such as the maximum number of cards, the bus length and power supply unit, the host must ensure that the power is built up to the operating level (the same level which will be specified in CMD1) before CMD1 is transmitted.

After power-up, the host starts the clock and sends the initializing sequence on the CMD line. This sequence is a contiguous stream of logical “1”s. The sequence length is the maximum of 1 ms, 74 clocks or the supply ramp-up time; the additional 10 clocks (over the 64 clocks after what the card should be ready for communication) are provided to eliminate power-up synchronization problems.

2Inserting a card when the bus is operating

Power-up TimeSupply Ramp-up

Time First CMD1 to card is ready

time

Supply Voltage

VDD max

Bus master supply voltage

Logic working level

InitializationSequence CMD1

Initialization delay:the max. of 1 ms,74 clock cycles

and supply ramp-up time

Optional repetitions of CMD1 until nocards are responding with busy bit set

CMD1 CMD1 CMD2

VDD min

NCC NCC NCC

Card logic workingvoltage range

Memory fieldworking voltage

range



3.4.2 Bus Operating Conditions

SPI Mode Bus operating conditions are identical to those in MultiMediaCard mode. Table 3-3 lists the power supply voltages. The CS signal timing is identical to the input signal timing (see Figure 3-5).

Table 3-3 Bus Operating Conditions Summary

Parameter Symbol Min Max Unit RemarkGeneral Peak voltage on all lines --- -0.5 3.6 V

All Inputs

Input Leakage Current --- -10 10 uA

All Outputs

Output Leakage Current --- -10 10 uA

Power Supply Voltage3

Supply Voltage VDD 2.7 3.6 V

Supply voltage differentials (VSS1, VSS2)

--- -0.5 0.5 V

Capacitance

VDD Capacitance C (VDD) --- 3.0 uF

3.4.3 Bus Signal Line Load

The total capacitance CL of each line in the MultiMediaCard bus is the sum of the bus master capacitance CHOST, the bus capacitance CBUS itself and the capacitance CCARD of each card connected to this line:

CL = CHOST + CBUS + N*CCARD

Where N is the number of connected cards. Requiring the sum of the host and bus capacitances not to exceed 30 pF for up to 10 cards, and 40 pF for up to 30 cards, the values in Table 3-4 must not be exceeded.

Table 3-4 Host and Bus Capacities

Parameter Symbol Min. Max. Unit Remark Pull-up resistance RCMD, RDAT 50 100 kΩ Prevents bus floating

Bus signal line capacitance CL --- 250 pF fPP < 5 MHz, 30 cards

Bus signal line capacitance CL --- 100 pF fPP < 20 MHz, 10 cards Signal card capacitance CCARD --- 7 pF ---

Max. signal line inductance --- --- 16 nH fPP <20 MHz

3.4.4 Bus Signal Levels

Because the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage (see Figure 3-4).

3 The current consumption of any card during the power-up procedure must not exceed 10 mA.



Figure 3-4 Bus Signal Levels

3.4.5 Open-drain Mode Bus Signal Level

The input levels shown in Table 3-5 are identical to the push-pull mode bus signal levels.

Table 3-5 Open Drain Mode Bus Signal Levels

Parameter Symbol Min. Max. Unit Conditions

Output high voltage VOH VDD-0.2 --- V IOH = -100 uA

Output low voltage VOL --- 0.3 V IOL = 2 mA

3.4.6 Push-pull Mode Bus Signal Level

To meet the requirements of the JEDEC specification JESD8-1A, the card input and output voltages will be within the specified ranges in Table 3-6 for any VDD of the allowed voltage range.

Table 3-6 Push-pull Mode Bus Signal Level

Parameter Symbol Min. Max. Unit Conditions

Output high voltage VOH 0.75 * VDD --- V IOH = -100 uA @ VDD (min.)

Output low voltage VOL --- 0.125 * VDD V IOL = 100 uA @ VDD (min.)

Input high voltage VIH 0.625 * VDD VDD + 0.3 V

Input low voltage VIL VSS-0.3 0.25 * VDD V ---

InputLow

Level

InputHighLevel

OutputHighLevel

OutputLow

Level

Undefined

VDD

VOH

VIH

VL

VOL

VSS t

V



3.4.7 Bus Timing

SanDisk’s MultiMediaCards and RS- MultiMediaCards clock data in on the rising edge and out on the falling edge. The data contained in the shaded areas is not valid in Figure 3-5.

Figure 3-5 Data In/Out Referenced to Clock Timing

Table 3-7 Bus Timing

Parameter Symbol Min Max Unit Remark

Clock (CLK) – all values referred to min. VIH and max. VIL

Clock Freq. Data Transfer Mode fPP 0 20 MHz CL < 100 pF (10 cards)

Clock Freq. Identification Mode fOD 0 400 kHz CL < 250 pF (30 cards)

Clock Low Time tWL 10 --- ns CL < 100 pF (10 cards)

Clock High Time tWH 10 --- ns CL < 100 pF (10 cards)

Clock Rise Time tTLH --- 10 ns CL < 100 pF (10 cards)

Clock Fall Time tTHL --- 10 ns CL < 100 pF (10 cards)

Clock Low Time tWL 50 --- ns CL < 250 pF (30 cards)

Clock High Time tWH 50 --- ns CL < 250 pF (30 cards)

Clock Rise Time tTLH --- 50 ns CL < 250 pF (30 cards)

Clock Fall Time tTHL --- 50 ns CL < 250 pF (30 cards)

Inputs CMD, DAT – referenced to CLK

Input setup time tISU 3 --- ns

Input hold time tIH 3 --- ns

Outputs CMD, DAT – referenced to CLK

Output setup time tOSU 5 --- ns

Output hold time tODLY 5 --- ns



3.5 MultiMediaCard/RS-MultiMediaCard Registers

There is a set of six registers within the card interface. The OCR, CID, and CSD registers carry the card configuration information. The RCA register holds the card relative communication address for the current session.

3.5.1 Operating Conditions Register

The 32-bit Operation Conditions Register (OCR) stores the VDD voltage profile of the MultiMediaCard/RS-MultiMediaCard. In addition, this register includes a status information bit. This status bit is set if the card power-up procedure has been finished. All cards will implement the OCR Register.

The supported voltage range is coded as shown in Table 3-8, for high voltage and low voltage MultiMediaCards and RS-MultiMediaCards. As long as the card is busy, the corresponding bit (31) is set to low, the ‘wired-and’ operation yields low if at least one card is still busy.

Table 3-8 Operating Conditions Register

OCR Bit

VDD Voltage Window High Voltage MultiMediaCard Low Voltage MultiMediaCard

[6:0] Reserved 0000000b 0000000b

[7] 1.65 - 1.95 0b 1b

[14:8] 2.0 - 2.6 0000000b 0000000b

[23:15] 2.7 - 3.6 111111111b 111111111b

[30:24] Reserved 0000000b 0000000b

[31] Card power-up status bit (busy)

3.5.2 Card Identification Register

The Card Identification Register (CID) is 16 bytes long and contains a unique card identification number as shown in Table 3-9. It is programmed during card manufacturing and cannot be changed by MultiMediaCard/RS-MultiMediaCard hosts.

Table 3-9 CID Register Fields

Name Type Width CID-Slice CID Value Comments

Manufacturer ID (MID) Binary 8 [127:120] 0x02 Manufacturer IDs are controlled and assigned by the MMC Association

OEM/Application ID (OID) Binary 16 [119:104] 0x0000 Identifies the card OEM and/or the card contents. The OID is assigned by the MMCA. This field may be specifically configured for OEM customers



Name Type Width CID-Slice CID Value Comments

Product Name (PNM) String 48 [103:56] SDMJ-32 SDM032 SDMJ-64 SDM064 SDMJ-128 SDM128 SDMJ-256 SDM256 SDMRJ-32 SDR032 SDMRJ-64 SDR064 SDMRJ-128 SDR128 SDMRJ-256 SDR256

Six ASCII characters long

Product Revision4 BCD 8 [55:48] --- Two binary-coded decimal

Serial Number (PSN) Binary 32 [47:16] --- 32-bit unsigned integer

Manufacturing Date Code (MDT)

BCD 8 [15:8] Manufact-ure date (for ex. March 2001= 00110100

Manufacturing date—mm/yy (offset from 1997)

CRC7 checksum (CRC) Binary 7 [7:1] CRC7* Calculated

Not used, always “1” --- 1 [0.0] --- ---

*The CRC checksum is computed by using the following formula:

CRC Calculation: G(x)=x7+3+1

M(x)=(MID-MSB)*x119+…+(CIN-LSB)*x0

CRC[6…0]=Remainder[(M(x)*x7)/G(x)]

3.5.3 Card Specific Data Register

The Card Specific Data (CSD) Register configuration information is required to access the card data.

In Table 3-10, the Cell Type column defines the CSD field as read-only (R), one-time programmable (R/W) or erasable (R/W/E). The values are presented in “real world” units for each field and coded according to the CSD structure. The Model Dependent column marks (X) the CSD fields that are model dependent.

4 The product revision is composed of two binary-coded decimal (BCD) digits (4 bits ea.) representing and “n.m” revision number. The “n” is the most significant nibble and the “m” is the least significant nibble. Example: the PRV binary value filed for product revision (6.2) would be “01100010”.



Table 3-10 CSD Register Fields

Field Width Cell Type

CSD Slice

CSD Value

CSD Code

Model Dep.

Description

CSD_ STRUCTURE

2 R [127:126] v1.2 2 CSD Structure

SPEC_VERS 4 R [125:122] v3.3 3 MultiMediaCard Specification

--- 2 R [121:120] 0 0 Reserved

TAAC 8 R [119:112] 1.5 ms 0x0F Data read access time

NSAC 8 R [111:104] 0 0 Data Read access time-2 in CLK cycles (NSAC*100)

TRAN_ SPEED

8 R [103:96] 20 MHz 00x2A Max. data transfer rate

CCC 12 R [95:84] Does not support: I/O, applica-tion- specific, stream write, and stream read

0x0F5 Card command classes

READ_BL_ LEN

4 R [83:80] 512 9 Max. read data block length

READ_BL_ PARTIAL

1 R [79:79] Yes 1 Partial blocks for read allowed

WRITE_BLK_MISALIGN

1 R [78:78] No 0 Write block misalignment

READ_BLK_ MISALIGN

1 R [77:77] No 0 Read block misalignment

DSR_IMP 1 R [76:76] No 0 DSR implemented

--- 2 R [75:74] 0 0 Reserved C_SIZE 12 R [73:62] X Device size (C_SIZE)

VDD_R_ CURR_MIN

3 R [61:59] 60 mA 6 Max. read current @VDD min.

VDD_R_ CURR_MAX

3 R [58:56] 80 mA 6 Max. read current @VDD max.

VDD_W_ CURR_MIN

3 R [55:53] 60 mA 6 Max. write current @VDD min.

VDD_W_ CURR_MAX

3 R [52:50] 80 mA 6 Max. write current @VDD max.



Field Width Cell Type

CSD Slice

CSD Value

CSD Code

Model Dep.

Description

C_SIZE_ MULT 3 R [49:47] X Device size multiplier (C_SIZE_MULT)

ERASE_GRP_ SIZE

5 R [46:42] 1 0 Erase group size

ERASE_GRP_ MULT

5 R [41:37] --- --- X Erase group size multiplier

WP_GRP_ SIZE 5 R [36:32] 32 0x1F Write protect group size

WP_GRP_ ENABLE

1 R [31:31] Yes 1 Write protect group enable

R2W_ FACTOR 3

R

[28:26]

1:16 2 Read to write speed factor

WRITE_BL_ LEN 4 R [25:22] 512 9 Max. write data block length

WRITE_BL_ PARTIAL

1 R [21:21] No 0 Partial blocks for write allowed

--- 4 R [20:17] 0 0 Reserved

CONTENT_PROT_APP

1 R [16:16] --- --- Content protection application

FILE_ FORMAT_ GRP

1 R/W [15:15] 0 0 Indicates file format of selected group

COPY 1 R/W [14:14] Copy 1 Copy flag (OTP)

PERM_ WRITE_ PROTECT

1 R/W [13:13] No 0 Permanent write protection

TMP_WRITE_ PROTECT

1 R/W/E

[12:12] No 0 Temporary write protection

FILE_ FORMAT 2 R/W [11:10] 0 0 File format of card

ECC 2 R/W/E

[9:8] None 0 ECC code

CRC 7 R/W/E

[7:1] --- --- X CRC

--- 1 - [0:0] 1 1 Not used, always “1”



The following sections describe the CSD fields and the relevant data types. If not explicitly defined otherwise, all bit strings are interpreted as binary coded numbers starting with the left bit first. • CSD_STRUCTURE—describes the version of the CSD structure.

Table 3-11 CSD Register Structure

CSD Structure CSD Structure Version Valid for System Specification Version

0 CSD Version 1.0 v1.0 to 1.2



3 Reserved Reserved

• SPEC_VERSION—Defines the MultiMediaCard System Specification version supported by the card.

Table 3-12 System Specification Version

SPEC_VERSION System Specification Version Number

0 v1.0 to 1.2

1 v1.4

2 v2.0 to 2.2

3 v3.1 to 3.3

4 - 15 Reserved

• TAAC—defines the asynchronous part (relative to the card clock (CLK)) of the read access time.

Table 3-13 TAAC Access Time Definition

TAAC Bit Position Code

Time exponent 2:0

0=1 ns, 1=10 ns, 2=100 ns, 3=1 ums, 4=10 ums, 5=100 ums, 6=1 ms, 7=10 ms

Time value 6:3

0=reserved, 1=1.0, 2=1.2, 3=1.3, 4=1.5, 5=2.0, 6=2.5, 7=3.0, 8=3.5, 9=4.0, A=4.5, B=5.0, C=5.5, D=6.0, E=7.0, F=8.0

7 Reserved

• NSAC—Defines the worst case for the clock dependent factor of the data access time. The unit for NSAC is 100 clock cycles. Therefore, the maximal value for the clock dependent part of the read access time is 25.5k clock cycles. The total read access time NAC is the sum of TAAC and NSAC. It has to be computed by the host for the actual clock rate. The read access time should be interpreted as a typical delay for the first data bit of a data block from the end bit on the read commands.



• TRAN_SPEED—Table 3-14 defines the maximum data transfer rate TRAN_SPEED.

Table 3-14 Max. Data Transfer Rate Definition

TRAN_SPEED Bit Code

Transfer rate exponent 2:0

0=100 kb/s, 1=1 Mb/s, 2=10 Mb/s, 3=100 Mb/s, 4…7=reserved

Time mantissa 6:3

0=reserved, 1=1.0, 2=1.2, 3=1.3, 4=1.5, 5=2.0, 6=2.5, 7=3.0, 8=3.5, 9=4.0, A=4.5, B=5.0, C=5.5, D=6.0, E=7.0, F=8.0

7 Reserved

• CCC—The MultiMediaCard command set is divided into subsets (command classes). The Card Command Class Register (CCC) defines which command classes are supported by this card. A value of “1” in a CCC bit means that the corresponding command class is supported.

Table 3-15 Supported Card Command Classes

CCC Bit Supported Card Command Class

0 Class 0

1 Class 1

----11 Class 11

• READ_BL_LEN—The read data block length is computed as 2READ_BL_LEN. The maximum block length might therefore be in the range 1, 2, 4…2048 bytes.

Table 3-16 Data Block Length

READ_BL_LEN Block Length

0 20 = 1 byte

1 21 = 2 bytes

…… 11 211 = 2048 bytes

12-15 Reserved

• READ_BL_PARTIAL—defines whether partial block sizes can be used in block read commands.

Table 3-17 Bit Definition

READ_BL_PARTIAL Definition

0 Only the READ_BL_LEN block size can be used for block-oriented data transfers.

1 Smaller blocks can be used as well. The minimum block size will be equal to minimum addressable unit (one byte).



• WRITE_BLK_MISALIGN—Defines if the data block to be written by one command can be spread over more than one physical block of the memory device. The size of the memory block is defined in WRITE_BL_LEN.


WRITE_BLK_MISALIGN Definition

0 Signals that crossing physical block boundaries is invalid.

1 Signals that crossing physical block boundaries is allowed.

• READ_BLK_MISALIGN—defines if the data block to be read by one command can be spread over more than one physical block of the memory device. The size of the memory block is defined in READ_BL_LEN.


READ_BLK_MISALIGN Definition

0 Signals that crossing physical block boundaries is invalid.

1 Signals that crossing physical block boundaries is allowed.

• DSR_IMP—defines if the configurable driver stage is integrated on the card. If set, a Driver Stage Register (DSR) must be implemented also.

Table 3-20 DSR Implementation Code Table

DSR_IMP DSR Type

0 No DSR implemented

1 DSR Implemented

• C_SIZE (Device Size)—computes the card capacity. The memory capacity of the card is computed from the entries C_SIZE, C_SIZE_MULT and READ_BL_LEN as follows:

Memory capacity = BLOCKNR * BLOCK_LEN Where:

BLOCKNR = (C_SIZE+1) * MULT

MULT = 2C_SIZE_MULT+2 (C_SIZE_MULT < 8)

BLOCK_LEN = 2READ_BL_LEN (READ_BL_LEN < 12)

Therefore, the maximum capacity that can be coded is 4096*512*2048=4 GB. For example, 4-MB card with BLOCK_LEN = 512 can be coded with C_SIZE_MULT = 0 and C_SIZE = 2047.

• VDD_R_CURR_MIN, VDD_W_CURR_MIN—minimum values for read and write currents at the VDD power supply are coded in Table 3-21.

Table 3-21 VDD Minimum Current Consumption

VDD_R_CURR MIN

VDD_W_CURR MIN

Code for Current Consumption @ VDD

2:0 0=0.5 mA, 1=1 mA, 2=5 mA, 3=10 mA, 4=25 mA, 5=35 mA, 6=60 mA, 7=100 mA



• VDD_R_CURR_MAX, VDD_W_CURR_MAX—maximum values for read and write currents on VDD power supply are coded Table 3-22.

Table 3-22 VDD Maximum Current Consumption

VDD_R_CURR MAX

VDD_W_CURR MAX

Code for Current Consumption @ VDD

2:0 0=1 mA, 1=5 mA, 2=10 mA, 3=25 mA, 4=35 mA, 5=45 mA, 6=80 mA, 7=200 mA

• C_SIZE_MULT (Device Size Multiplier)—codes a factor MULT for computing the total device size (see C_SIZE). The factor MULT is defined as 2C_SIZE_MULT+2.

Table 3-23 Device Size Multiplying Factor

C_SIZE_MULT MULT

0 22 = 4

1 23 = 8

2 24 = 16

3 25 = 324 26 = 64

5 27 = 1286 28 = 256

7 29 = 512

• ERASE_GRP_SIZE—contents of this register is a 5-bit binary coded value, used to calculate the size of the erasable unit of the card. The size of the erase unit (also referred to as erase group) is determined by the ERASE_GRP_SIZE and the ERASE_GRP_MULT entries of the CSD, using the following equation: Size of erasable unit = (ERASE_GRP_SIZE + 1) * (ERASE_GRP_MULT + 1)

This size is given as the minimum number of write blocks that can be erased in a single erase command.

• ERASE_GRP_MULT—5-bit binary coded value used for calculating the size of the erasable unit of the card. See ERASE_GRP_SIZE section for detailed description.

• WP_GRP_SIZE—write protected group size. The content of this register is a 5-bit binary coded value, defining the number of Erase Groups (see ERASE_GRP_SIZE). The actual size is computed by increasing this number by one. A value of 0 means 1 erase group, 127 means 128 erase groups.

• WP_GRP_ENABLE—A value of “0” means group write protection is not possible.



• R2W_FACTOR—defines the typical block program time as a multiple of the read access time. Table 3-24 defines the field format.

Table 3-24 R2W_FACTOR

R2W_FACTOR Multiples of Read Access Time

0 1

1 2 (write half as fast as read)

2 4

3 84 16

5 326 64

7 128

• WRITE_BL_LEN—block length for write operations. See READ_BL_LEN for field coding.

• WRITE_BL_PARTIAL—defines whether partial block sizes can be used in block write commands.

Table 3-25

WRITE_BL_PARTIAL Definition

0 Only the WRITE_BL_LEN block size, and its partial derivatives in resolution of units of 512 blocks, can be used for block oriented data write.

1 Smaller blocks can be used as well. The minimum block size is one byte.

• FILE_FORMAT_GROUP—indicates the selected group of file formats. This field is read-only for ROM.

• COPY—marks the card as an original (0) or non-original (1). Once set to non-original, this bit cannot be reset to original. The definition of “original” and “non-original” is application dependent and does not change card characteristics.

• PERM_WRITE_PROTECT—permanently protects the whole card content against overwriting or erasing (all write and erase commands for this card are permanently disabled). The default value is 0 (i.e., not permanently write protected).

• TMP_WRITE_PROTECT—temporarily protects the whole card content from being overwritten or erased (all write and erase commands for this card are temporarily disabled). This bit can be set and reset. The default value is 0 (i.e., not write protected).

• CONTENT_PROT_APP—indicates whether the content protection application is supported. MultiMediaCards that implement the content protection application will have this bit set to 1.



• FILE_FORMAT—indicates the file format on the card. This field is read-only for ROM. The formats are defined in Table 3-26.

Table 3-26 File Format

FILE_FORMAT_GRP FILE_FORMAT Type

0 0 Hard disk-like file system with partition table.

0 1 DOS FAT (floppy-like) w/boot sector only (no partition table).

0 2 Universal file format.0 3 Others/unknown.

1 0, 1, 2, 3 Reserved.

• ECC—defines the ECC code that was used for storing data on the card. This field is used to decode user data by the host (or application). Table 3-27 defines the field format.

Table 3-27 ECC Type

ECC ECC Type Max. Number of Correctable Bits per Block

0 none (default) none

1 BCH (542,512) 3

2 - 3 Reserved ---

• CRC—carries the checksum for the CSD contents. The host must recalculate the

checksum for any CSD modification. The default corresponds to the initial CSD contents.

3.5.4 Status Register

The MMC/RS-MMC Status Register structure is defined in Table 3-28. The Type and Clear Condition fields in the table are coded as follows:

Type: • E—Error bit • S—Status bit • R—Detected and set for the actual command response • X—Detected and set during command execution. The host must poll the card by

sending status command in order to read these bits. Clear Condition: • A—According to the card current state • B—Always related to the previous command. Reception of a valid command will clear

it (with a delay of one command) • C—Clear by read.



Table 3-28 Status Register Description

Bit Identifier Type Value Description Clear Cond.

31 OUT_OF_RANGE E R 0 = no error 1 = error

The command’s argument was out of the allowed range for this card.

C

30 ADDRESS_ ERROR

E R X 0 = no error 1 = error

A misaligned address that did not match the block length was used in the command.

C

29 BLOCK_LEN_ ERROR

E R 0 = no error 1 = error

The transferred block length is not allowed for this card, or the number of transferred bytes does not match the block length.

C

28 ERASE_SEQ_ ERROR


An error in the sequence of erase commands occurred.

C

27 ERASE_PARAM E X 0 = no error 1 = error

An invalid selection of write-blocks for erase occurred.

C

26 WP_VIOLATION E R X 0 = not protected 1 = protected

Attempt to program a write-protected block.

C

25-24

Not applicable. This bit is always set to 0.

23 COM_CRC_ ERROR


The CRC check of the previous command failed.

B

22 ILLEGAL_ COMMAND


Command not legal for the card state

B

21-20

Not applicable. This bit is always set to 0.

19 ERROR E R X 0 = no error 1 = error

A general or an unknown error occurred during the operation

C

17 Not applicable. This bit is always set to 0.

16 CID/CSD_ OVERWRITE

E R X 0 = no error 1 = error

Can be either one of the following errors:

- The CID register has been already written and can not be overwritten

- The read only section of the CSD does not match the card content.

- An attempt to reverse the copy (set as original) or permanent WP (unprotected) bits was made.

C



Bit Identifier Type Value Description Clear

Cond.

15 WP_ERASE_SKIP S X 0 = not protected 1 = protected

Only partial address space was erased due to existing write protected blocks.

C

14 CARD_ECC_ DISABLED

S X 0 = enabled 1 = disabled

The command has been executed without using the internal ECC.

A

13 ERASE_RESET S R 0 = cleared 1 = set

An erase sequence was cleared before executing because an out of erase sequence command was received.

C

12-9

CURRENT_STATE S X 0 = idle 1 = ready 2 = ident 3 = stby 4 = tran 5 = data 6 = rcv 7 = prg 8 = dis 9-15 = reserved

The state of the card when receiving the command. If the command execution causes a state change, it will be visible to the host in the response to the next command.

The four bits are interpreted as a binary coded number between 0 and 15.

B

8 READY_FOR_ DATA

S X 0 = not ready 1 = ready

Corresponds to buffer-empty signaling on the bus (RDY/BSY).

A

7-0 Reserved. Always set to 0.



3.5.5 Relative Card Address Register

The 16-bit Relative Card Address (RCA) Register carries the card address that is published by the card during the card identification. This address is used for the addressed host-card communication after the card identification procedure.

3.5.6 MultiMediaCard Registers in SPI Mode

In SPI mode, only the MultiMediaCard CSD and CID registers are accessible. Their format is identical to the format in the MultiMediaCard mode. However, a few fields are irrelevant in SPI mode.

In SPI mode, the card status register has a different, shorter format as well. Refer to the SPI Protocol section for more details.

3.6 File System Format

SanDisk MultiMediaCards and RS-MultiMediaCards are formatted with a “hard disk-like” partitioned DOS FAT file system.

Similar to hard disks in PCs, the first data block of the memory consists of a partition table. Thus, using the same notation as for hard disks, i.e., partitioning the memory field into logical sectors of 512 bytes each, the first sector is reserved for this partition table. Table 3-29 shows how the data in this sector is structured.

Table 3-29

Byte Position Length (bytes) Entry Description Value/Range

0x0 446 Consistency check routine ---

0x1be 16 Partition Table entry See Table 3-30

0xce 16 Partition Table entry See Table 3-30

0x1de 16 Partition Table entry See Table 3-30

0x1ee 16 Partition Table entry See Table 3-30

0x1fe 1 Signature 0x55

0x1ff 1 Signature 0xaa

Table 3-30 Partition Entry Description


0x0 1 Boot descriptor 0x00 (Non-bootable Device) 0x80 (Bootable Device)

0x1 3 First partition sector Address of First Sector

0x4 1 File system descriptor 0 = Empty 1 = DOS 12-bit FAT < 16 MB 4 = DOS 16-bit FAT < 32 MB 5 = Extended DOS 6 = DOS 16-bit FAT >= 32 MB 0x10-0xff = Free for other File Systems*



cDescriptors marked by an asterisk are not used in DOS systems. Every DOS partition is based on a 12-bit, 16-bit FAT or VFAT respectively. All sector numbers are stored in Little-Endian format (least significant byte first). The start and end addresses of the partition are given in terms of heads, tracks and sectors, and can therefore be ignored for the MultiMediaCard, since the position of the partition can be determined by the last two entries.

The boot sector is described in Table 3-31.

Table 3-31 Boot Sector Configuration


0x0 3 Jump command 0xeb 0xXX 0x90

0x3 8 OEM name XXX

0xb 2 Bytes/sector 512

0xd 1 Sectors/cluster XXX (range: 1-64)

0xe 2 Reserved Sectors (Number of reserved sectors at the beginning of the media including the boot sector.)

1

0x10 1 Number of FATs 2

0x11 2 Number of root directory entries

512

0x13 2 Number of sectors on media

XXX (Depends on card capacity, if the media has more than 65535 sectors, this field is zero and the ‘number of total sectors’ is set.)

0x15 1 Media descriptor 0xf8 (hard disk)

0x16 2 Sectors/FAT XXX

0x18 2 Sectors/track 32 (no meaning)


0x5 3 Last partition sector Address of Last Sector

0x8 4 First sector position relative to beginning of device

Number of First Sector (Linear Address)

0xc 4 Number of sectors in partition Between one and the max. amount of sectors on device




0x1a 2 Number of heads 2 (no meaning)

0x1c 4 Number of hidden sectors

0

0x20 4 Number of total sectors XXX (depends on capacity)

0x24 1 Drive number 0x80

0x25 1 Reserved 0

0x26 1 Extended boot signature

0x29

0x27 4 Volume ID or serial number

XXX

0x2b 11 Volume label XXX (ASCII characters padded with blanks if less than 11 characters.)

0x36 8 File system type XXX (ASCII characters identifying the file system type FAT12 or FAT16.)

0x3e 448 Load program code XXX

0x1fe 1 Signature 0x55

0x1ff 1 Signature 0xaa

All ‘X’ entries are denoting card dependent or non-fixed values. The number of sectors per track and the number of heads are meaningless for the MultiMediaCard and can be ignored.

Chapter 4 – MultiMediaCard Protocol Description Revision 1.0 MultiMediaCard/RS-MultiMediaCard Product Manual


4 MultiMediaCard Protocol Description The host (master) controls all communication between the host and MultiMediaCard/RS-MultiMediaCard. The host sends the following two types of commands:

• Broadcast Commands—Broadcast commands are intended for all MultiMediaCards and RS-MultiMediaCards . Some of these commands require a response

• Addressed (Point-to-Point) Commands—The addressed commands are sent to the addressed cards and cause a response to be sent from this card.

A general overview of the command flow is shown in Figure 4-1 for the Card Identification Mode and Figure 4-2 for the Data Transfer Mode. The commands are listed in Table 4-5 to 4-7. The dependencies between the current MultiMediaCard/RS-MultiMediaCard state, received command and following state are listed in Table 4-1. In the following sections, the different card operation modes will be described first. Thereafter, the restrictions for controlling the clock signal are defined. All card commands together with the corresponding responses, state transitions, error conditions and timings are presented in the following sections.

The MultiMediaCard/RS-MultiMediaCard has two operation modes.

• Card Identification Mode— The host will be in card identification mode after reset and while it is looking for new cards on the bus. MultiMediaCards will be in this mode after reset until the SET_RCA command (CMD3) is received.

• The Interrupt Mode option defined in the MultiMediaCard Standard is not implemented on the SanDisk MultiMediaCard.

• Data Transfer Mode—MultiMediaCards will enter data transfer mode once an RCA is assigned to them. The host will enter data transfer mode after identifying all the MultiMediaCards on the bus.

Table 4-1 lists the dependencies between operation modes and card states. Each state in the card state diagram (Figure 4-1 and 4-2) is associated with one operation mode.

Table 4-1 Card States vs. Operation Modes Overview

Card State Operation Mode Bus Mode

Inactive Inactive

Idle, Ready, Identification Card Identification Mode Open-drain

Standby, Transfer, Send data, Receive data, Programming, Disconnect

Data Transfer Mode Push-pull

If a command with improper CRC was received, it is ignored. If there was a command execution (e.g., continuous data read) the card continues in the operation until it gets a correct host command.



4.1 Card Identification Mode While in Card Identification Mode, the host resets all the cards that are in Card Identification Mode, validates operation voltage range, identifies cards and asks them to publish a Relative Card Address (RCA). This operation is done to each card separately on its own command (CMD) line. All data communication in the Card Identification Mode uses the CMD line only.

Figure 4-1 MultiMediaCard State Diagram—Card Identification Mode

4.1.1 Reset

GO_IDLE_STATE (CMD0) is the software-reset command that sets each MultiMediaCard or RS-MultiMediaCard to Idle State regardless of the current state of the card. Cards already in an inactive state are not affected by this command.

After power-on by the host, all cards are in Idle State, including the cards that were in Inactive State.1

After power-on or CMD0, all card CMD lines are in input mode, waiting for the start bit of the next command. The cards are initialized with a default relative card address (RCA=0x0000) and with a default driver stage register setting (lowest speed, highest driving current capability).

4.1.2 Operating Voltage Range Validation

The MultiMediaCard standard requires that all MultiMediaCards and RS-MultiMediaCards be able to establish communication with the host using any operating voltage between VDD-min and VDD-max. However, during data transfer, minimum and maximum values

1 At least 74 clock cycles are required prior to starting bus communication.



for VDD are defined in the CSD Register and may not cover the entire range. Card hosts are expected to read the card’s CSD Register and select the proper VDD values or reject the card.

A MultiMediaCard/RS-MultiMediaCard that stores the CID and CSD data in the payload memory can communicate this information only under data-transfer VDD conditions. This means if the host and card have incompatible VDD ranges, the card will not be able to complete the identification cycle, nor to send CSD data.

SEND_OP_COND (CMD1) is designed to provide card hosts with a mechanism to identify and reject cards that do not match the host’s desired VDD range. To accomplish this task, the host sends the required VDD voltage window as the operand of this command. MultiMediaCards/RS-MultiMediaCards that cannot perform data transfer in the specified range must discard themselves from further bus operations and go into Inactive State. All other cards will respond concurrently (same method as card identification) sending back their VDD range. The wired-or result of the response will show all voltage ranges, some of which the cards do not support.

By omitting the voltage range in the command, the host can query the card stacks and determine if there are any incompatibilities before sending out-of-range cards into the Inactive State. A bus query should be used if the host can select a common voltage range or wants to notify the application of unusable cards in the stack.

The MultiMediaCard or RS-MultiMediaCard can use the busy bit in the CMD1 response to tell the host that it is still working on the power-up/reset procedure (e.g., downloading the register information from memory field) and is not ready for communication. In this case the host must repeat CMD1 until the busy bit is cleared.

During the initialization procedure, the host is not allowed to change OCR values; the card will ignore OCR content changes. If there is a actual change in the operating conditions, the host must reset the card stack (using CMD0) and begin the initialization procedure again.

GO_INACTIVE_STATE (CMD15) can also be used to send an addressed MultiMediaCard/RS-MultiMediaCard into the Inactive State. CMD15 is used when the host explicitly wants to deactivate a card—for example, the host changes VDD into a range not supported by this card.

4.1.3 Card Identification Process

The host starts the card identification process in open-drain mode with the identification clock rate fOD. The open-drain driver stages on the CMD line allow parallel card operation during card identification.

After the bus is activated and a valid operation condition is obtained, the host asks all cards for their unique card identification (CID) number with the broadcast command, ALL_SEND_CID (CMD2). All remaining unidentified cards, those in Ready State, simultaneously start sending their CID numbers serially, while bit-wise monitoring their outgoing bit stream. The MultiMediaCards and RS-MultiMediaCards with outgoing CID bits that do not match the corresponding bits on the command line, in any one of the bit periods, stop sending their CID immediately and must wait for the next identification cycle (cards stay in the Ready State). Because CID numbers are unique for each card, there should be only one card that successfully sends its full CID number to the host; the cards then goes into Identification State. The host issues CMD3, (SET_RELATIVE_ADDR) to assign this card a relative address (RCA), which is shorter than CID and used to address the card in future data transfer mode communication typically with a higher clock rate than fOD. When the RCA is received, the card transfers to the Stand-by State and does not react



to further identification cycles. The MultiMediaCard/RS-MultiMediaCard also switches output drivers from open-drain to push-pull.

The host repeats the identification process as long as it receives a response (CID) to its identification command (CMD2). All cards have been identified when a card does not respond to CMD2. The time-out condition that recognizes completion is the absence of a start bit for more than five clock periods after sending CMD2.

4.2 Data Transfer Mode

When all cards are in Stand-by State, communication over the CMD and DAT lines are in push-pull mode. Until the host knows all CSD Register content, the fPP clock rate must remain at fOD because some cards may have operating frequency restrictions. The host issues SEND_CSD (CMD9) to obtain the content—for example, ECC type, block length, card storage capacity, and maximum clock rate.

Figure 4-2 MultiMediaCard State Diagram—Data Transfer Mode

CMD7 is used to select one MultiMediaCard/RS-MultiMediaCard and place it in the Transfer State. Only one card can be in the Transfer State at a given time. If a previously selected card is in the Transfer State, its connection with the host is released and it will move back to the Stand-by State. When CMD7 is issued with the reserved relative card address “0x0000,” all cards transfer back to Stand-by State. This may be used before identifying new cards without resetting other already registered cards. Cards that already have an RCA do not respond to identification command flow in this state.

Sending Data State (data)

Stand-byState (stby)

CMD0Card Identification Mode

Data TransferMode From all States in Data

Transfer Mode

CMD3 CMD15

CMD13

CMD7

CMD7

CMD7

CMD7

CMD12, "operation complete"

CMD16, 32...37

CMD20, 24, 25, 26, 27, 42

CMD4, 9, 10

CMD28, 29, 38

CMD24, 25

"operation complete"

"operation complete"

Transfer State (tran)

Receive Data State (rcv)

Programming State (prg)

Disconnect State (dis)

No State Transition in Data Transfer Mode

CMD12 or "transfer

end"

CMD11, 17, 18, 30

InterruptMode

Wait-IRQState (irqq)

Any start bitdetected onthe bus

CMD40



All data communication in the Data Transfer Mode is point-to point between the host and the selected MultiMediaCard (using addressed commands). All addressed commands are acknowledged with a response on the CMD line.

The relationship between the various data transfer modes is summarized in the card state diagram, Figure 4-2, and in the following paragraphs:

• The stop command (CMD12) can abort all data read commands at any given time. The data transfer will terminate and the card will return to the Transfer State. The read commands are block read (CMD17), multiple block read (CMD18), and send write protect (CMD30).

• The stop command (CMD12) can abort all data write commands at any given time. The write commands must be stopped prior to deselecting the card with CMD7. The write commands are block write (CMD24 and CMD25), write CID (CMD26), and write CSD (CMD27).

• When the data transfer is complete, the MultiMediaCard/RS-MultiMediaCard exits the data write state and moves to either the Programming State (successful transfer) or Transfer State (failed transfer).

• If a block write operation is stopped and the block length and CRC of the last block are valid, the data will be programmed

• The card may provide buffering for block write: the next block can be sent to the card while the previous is being programmed. If all write buffers are full, and the MMC/RS-MMC is in Programming State (see MultiMediaCard state diagram Figure 4-2), the DAT line will be kept low.

• No buffering option is available for write CSD, write CID, write protection, or erase: no other data transfer commands will be accepted when the MMC/RS-MMC is busy servicing any one of the aforementioned commands. The DAT line will be kept low throughout the period when the card is busy and in Programming State.

• Parameter-set commands are not allowed when the card is programming. Parameter-set commands are set block length (CMD16), and erase tagging/untagging (CMD32-37).

• Read commands are not allowed while the card is programming.

• Moving another MultiMediaC/RS-MultiMediaCard from Stand-by to Transfer State (using CMD7) will not terminate a programming operation. The card will switch to the Disconnect State and release the DAT line.

• A card can be reselected while in the Disconnect State, using CMD7. In this case the card will move to the Programming State and reactivate the busy indication.

• Resetting the card (using CMD0 or CMD15) will terminate any pending or active programming operation, which may destroy the data contents on the card. It is the host’s responsibility to prevent the potential destruction of data.



4.2.1 Data Read Format

When data is not being transmitted, the DAT bus line is high. A transmitted data block consists of a start bit (low), followed by a continuous data stream. The data stream contains the net payload data, and error correction bits if an off-card ECC is used. The data stream ends with an end bit (high). The data transmission is synchronous to the clock signal

The payload for a block-oriented data transfer is preserved by a CRC checksum. The generator polynomial is standard CCITT format: x16 + x12 + x5 + 1.

Block Read The basic unit of data transfer is a block whose maximum size is defined by READ_BL_LEN in the CSD. Smaller blocks with a starting and ending address contained entirely within one physical block, as defined by READ_BL_LEN, may also be transmitted. A CRC appended to the end of each block ensures data transfer integrity. CMD17 or READ_SINGLE_BLOCK starts a block read and returns the card to the Transfer State after a complete transfer. CMD18 or READ_MULTIPLE_BLOCK starts a transfer of several consecutive blocks. Blocks will be continuously transferred until a stop command is issued.

If the host uses partial blocks with an accumulated length that is not block aligned, the card, at the beginning of the first misaligned block, will detect a block misalignment error, set the ADDRESS_ERROR bit in the Status Register, abort transmission, and wait in the Data State for a stop command.

4.2.2 Data Write Format

The data transfer format is similar to the data read format. For block-oriented write data transfer, the CRC check bits are added to each data block. Prior to an operation, the MultiMediaCard/RS-MultiMediaCard performs a CRC check for each such received data block.2 This mechanism prevents the erroneous writing of transferred data.

Block Write Block write or CMD24-27 means that one or more blocks of data are transferred from the host to the card with a CRC appended to the end of each block by the host. If the CRC fails, the card will indicate the failure on the DAT line; the transferred data will be discarded and not written and all further transmitted blocks (in multiple block write mode) will be ignored.

If the host uses partial blocks with an accumulated length that is not block aligned, the card, at the beginning of the first misaligned block, will detect a block misalignment error, set the ADDRESS_ERROR bit in the Status Register, abort programming, and wait in the Data State for a stop command.

The write operation will also be aborted if the host tries to write over a write-protected area. In this case, however, the card will set the WP_VIOLATION bit.

After receiving a block of data and completing the CRC check, the card will begin programming and hold the DAT line low if its write buffer is full and unable to accept new data from a new WRITE_BLOCK command. The host may poll the status of the card with a SEND_STATUS command at any time, and the card will respond with its status. The status bit READY_FOR_DATA indicates whether the card can accept new data or whether the write process is still in progress. The host may deselect the card by issuing CMD7 (to select a different card), which will place the card in the Disconnect State and release the

2The polynomial is the same one used for a read operation.



DAT line without interrupting the write operation. When reselecting the card, it will reactivate busy indication by pulling DAT to low if programming is still in progress and write buffer is unavailable.

4.2.3 CSD Programming

Programming of the CSD register does not require a previous block length setting. After sending CMD27 and receiving an R1 response, the start bit (=0) is sent, the modified CSD register (=16 bytes), CRC16 (=2 bytes), and end bit (=1). The host can change only the least significant 16 bits [15:0] of the CSD. The rest of the CSD register content must match the MultiMediaCard/RS-MultiMediaCard CSD Register. If the card detects a content inconsistency between the old and new CSD register, it will not reprogram the CSD in order to ensure validity of the CRC field in the CSD register.

Bits [7:1] are the CRC7 of bits [127:8] of the CSD Register, which should be recalculated once the register changes. After calculating CRC7, the CRC16 should also be calculated for all of the CSD Register [127:0].

4.2.4 Erase

It is desirable to erase many sectors simultaneously in order to enhance the data throughput. Identification of these sectors is accomplished with the TAG_* commands. Either an arbitrary set of sectors within a single erase group or an arbitrary selection of erase groups may be erased at one time but not together; that is, the unit of measure for determining an erase is either a sector or an erase group. If it is a sector, all selected sectors must lay within the same erase group. To facilitate selection, a first command with the starting address is followed by a second command with the final address and all sectors within this range will be selected for erase. After a range is selected, an individual sector (or group) within that range can be removed using the UNTAG command.

The host must adhere to the following command sequence: TAG_SECTOR_START, TAG_SECTOR_END, UNTAG_SECTOR (up to 16 UNTAG sector commands can be sent for one erase cycle) and ERASE (or the same sequence for group tagging). Condition exceptions the MultiMediaCard/RS-MultiMediaCard may detect includes:

• An erase or TAG/UNTAG command is received out of sequence. The card will set the ERASE_SEQ_ERROR bit in the Status Register and reset the entire sequence.

• An out-of-sequence command (except SEND_STATUS) is received. The card will set the ERASE_RESET status bit in the Status Register, reset the erase sequence and execute the last command.

If the erase range includes write protected sectors, they will remain intact and only the non-protected sectors will be erased. The WP_ERASE_SKIP status bit in the Status Register will be set.

The address field in the TAG commands is a sector or a group address in byte units. The card will ignore all LSBs below the group or sector size. The number of UNTAG commands (CMD34 and CMD37) used in a sequence is limited for up to 16.

As described for block write, the MultiMediaCard/RS-MultiMediaCard will indicate that an erase is in progress by holding DAT low.



4.2.5 Write Protect Management

Write protection features may protect MultiMediaCard/RS-MultiMediaCard data against either erase or write. The entire card may be permanently write-protected by the manufacturer or content provider by setting the permanent or temporary write-protect bits in the CSD. Portions of the data may also be protected in units of WP_GRP_SIZE sectors as specified in the CSD. The SET_WRITE_PROT command sets the write protection of the addressed write-protect group, and the CLR_WRITE_PROT command clears the write protection of the addressed write-protect group.

The SEND_WRITE_PROT command is similar to a single block read command. The card will send a data block containing 32 write protection bits (representing 32 write protect groups starting at the specified address) followed by 16 CRC bits. The address field in the write protect commands is a group address in byte units. The card will ignore all LSBs below the group size.

4.2.6 Card Lock/Unlock Operation

The password protection feature enables the host to lock a card while providing a password that will be used later for unlocking the card. The password and its size are kept in 128-bit PWD and 8-bit PWD_LEN registers, respectively. These registers are non-volatile which protects a power cycle erase.

Locked cards respond to, and execute, all commands in the basic command class (class 0) and lock card command class. Therefore, the host is allowed to reset, initialize, select, query for status, etc., but not access data on the MultiMediaCard/RS-MultiMediaCard. If the password was previously set, it will be locked automatically after power on.

Similar to the existing CSD and CID register write commands, the lock/unlock command is available in transfer state only; it does not include an address argument and the card has to be selected before using it.

The card lock/unlock command has the structure and bus transaction type of a regular single block write command. The transferred data block includes all required information of the command—for example, password setting mode, PWD itself, card lock/unlock, etc. Table 4-2 describes the structure of the command data block.

Table 4-2 Lock Card Data Structure

Byte Bit 7

Bit 6

Bit 5

Bit 4

Bit 3 Bit 2 Bit 1 Bit 0

0 Reserved ERASE LOCK_UNLOCK CLR_PWD SET_PWD

1 PWD_LEN

2

…

PWD_LEN + 1

Password Data

Bit Name Description

ERASE 1 = Forced Erase Operation (all other bits shall be ‘0’) and only the CMD byte is sent.

LOCK/UNLOCK 1 = Lock the card. 0 = Unlock the card (it is valid to set this bit together with SET_PWD but it is not



Bit Name Description allowed to set it together with CLR_PWD).

CLR_PWD 1 = Clear PWD.

SET_PWD 1 = Set new password to PWD.

PWD_LEN Define the following password length (in bytes).

PWD Password (new or currently used depending on the command).

The host will define the data block size before it sends the card lock/unlock command. This will allow for different password sizes.

• Set Password The sequence for setting the password is as follows:

1. Select a card (CMD7), if not previously selected already. 2. Define the block length (CMD16), given by the 8bit card lock/unlock mode, the 8

bits password size (in bytes), and the number of bytes of the new password. In case that a password replacement is done, then the block size shall consider that both passwords, the old and the new one, are sent with the command.

3. Send Card Lock/Unlock command with the appropriate data block size on the data line including 16-bit CRC. The data block shall indicate the mode (SET_PWD), the length (PWD_LEN) and the password itself. In case that a password replacement is done, then the length value (PWD_LEN) shall include both passwords, the old and the new one, and the PWD field shall include the old password (currently used) followed by the new password.

4. In case that the sent old password is not correct (not equal in size and content) then LOCK_UNLOCK_FAILED error bit will be set in the status register and the old password does not change. In case that PWD matches the sent old password then the given new password and its size will be saved in the PWD and PWD_LEN fields, respectively. Note that the password length register (PWD_LEN) indicates if a password is currently set. When it equals ‘0’ there is no password set. If the value of PWD_LEN is not equal to zero the card will lock itself after power up. It is possible to lock the card immediately in the current power session by setting the LOCK/UNLOCK bit (while setting the password) or sending additional command for card lock.

• Reset Password The sequence for resetting the password is as follows:

1. Select a card (CMD7), if not previously selected already. 2. Define the block length (CMD16), given by the 8-bit card lock/unlock mode, the 8-

bit password size (in bytes), and the number of bytes of the currently used password.

3. Send the card lock/unlock command with the appropriate data block size on the data line including 16-bit CRC. The data block shall indicate the mode CLR_PWD, the length (PWD_LEN) and the password (PWD) itself (LOCK/UNLOCK bit is don’t care). If the PWD and PWD_LEN content match the sent password and its size, then the content of the PWD register is cleared and PWD_LEN is set to 0. If the password is not correct then the LOCK_UNLOCK_FAILED error bit will be set in the status register.

• Lock Card The sequence for locking a card is as follows:

1. Select a card (CMD7), if not previously selected already.



2. Define the block length (CMD16), given by the 8-bit card lock/unlock mode, the 8-bit password size (in bytes), and the number of bytes of the currently used password.

3. Send the card lock/unlock command with the appropriate data block size on the data line including 16-bit CRC. The data block shall indicate the mode LOCK, the length (PWD_LEN) and the password (PWD) itself. If the PWD content equals to the sent password then the card will be locked and the card-locked status bit will be set in the status register. If the password is not correct then LOCK_UNLOCK_FAILED error bit will be set in the status register. Note that it is possible to set the password and to lock the card in the same sequence. In such case the host shall perform all the required steps for setting the password (as described above) including the bit LOCK set while the new password command is sent. If the password was previously set (PWD_LEN is not ‘0’), then the card will be locked automatically after power on reset. An attempt to lock a locked card or to lock a card that does not have a password will fail and the LOCK_UNLOCK_FAILED error bit will be set in the Status Register.

• Unlock Card The sequence for unlocking a card is as follows:

1. Select a card (CMD7), if not previously selected already. 2. Define the block length (CMD16), given by the 8-bit card lock/unlock mode, the 8-

bit password size (in bytes), and the number of bytes of the currently used password.

3. Send the card lock/unlock command with the appropriate data block size on the data line including 16-bit CRC. The data block shall indicate the mode UNLOCK, the length (PWD_LEN) and the password (PWD) itself.

If the PWD content equals to the sent password then the card will be unlocked and the card-locked status bit will be cleared in the status register. If the password is not correct then the LOCK_UNLOCK_FAILED error bit will be set in the status register.

Unlocking occurs only for the current power session. As long as the PWD is not cleared the card will be locked automatically on the next power up. The only way to unlock the card is by clearing the password.

An attempt to unlock an unlocked card will fail and LOCK_UNLOCK_FAILED error bit will be set in the Status Register.

• Force Erase In case the user forgot the password (the PWD content) it is possible to erase all the card data content along with the PWD content. This operation is called Forced Erase:

1. Select a card (CMD7), if not previously selected already. 2. Define the block length (CMD16) to 1 byte (8-bit card lock/unlock command).

Send the card lock/unlock command with the appropriate data block of one byte on the data line including 16-bit CRC. The data block shall indicate the mode ERASE (the ERASE bit shall be the only bit set).

If the ERASE bit is not the only bit in the data field then the LOCK_UNLOCK_FAILED error bit will be set in the status register and the erase request is rejected. If the command was accepted then ALL THE CARD CONTENT WILL BE ERASED including the PWD and PWD_LEN register content and the locked card will get unlocked.

An attempt to force erase on an unlocked card will fail and LOCK_UNLOCK_FAILED error bit will be set in the status register.



4.3 Clock Control

The host can use the MultiMediaCard/RS-MultiMediaCard bus clock signal to set the cards to energy-saving mode or control the bus data flow. The host is allowed to lower the clock frequency or shut it down.

A few restrictions the host must follow include:

• The bus frequency can be changed at any time (under the restrictions of maximum data transfer frequency, defined by the MultiMediaCard/RS-MultiMediaCard and the identification frequency).

• It is an obvious requirement that the clock must be running for the card to output data or response tokens. After the last bus transaction, the host is required, to provide eight clock cycles for the card to complete the operation before shutting down the clock. Following is a list of various card bus transactions:

− A command with no response—eight clocks after the host command end bit.

− A command with response—eight clocks after the card response end bit.

− A read data transaction—eight clocks after the end bit of the last data block.

− A write data transaction—eight clocks after the CRC status token.

• The host is allowed to shut down the clock of a card that is busy; the card will complete the programming operation regardless of the host clock. However, the host must provide a clock edge for the card to turn off its busy signal. Without a clock edge the card (unless previously disconnected by a deselect command -CMD7) will permanently force the DAT line down.

4.4 Cyclic Redundancy Codes

The Cyclic Redundancy Check (CRC) is intended to protect MultiMediaCard/RS-MultiMediaCard commands, responses, and data transfer against transmission errors on its bus. One CRC is generated for every command and checked for every response on the CMD line. For data blocks, CRCs are generated for each DAT line per transferred block. The CRC is generated and checked as shown in the following subsections.

4.4.1 CRC7

The CRC7 check is used for all commands, all responses except type R3, and CSD and CID registers. The CRC7 is a 7-bit value and is computed as follows:

generator polynomial: G(x) = x7 + x3 + 1

M(x) = (first bit) * xn + (second bit) * xn-1 +...+ (last bit) * x0

CRC[6...0] = Remainder [(M(x) * x7) / G(x)]

All CRC registers are initialized to zero. The first bit is the most significant bit of the corresponding bit string (of the command, response, CID or CSD). The degree n of the polynomial is the number of CRC protected bits decreased by one. The number of bits to be protected is 40 for commands and responses (n = 39), and 120 for the CSD and CID (n = 119) registers.



Figure 4-3 CRC7 Generator/Checker

4.4.2 CRC16

The CRC16 is used for payload protection in block transfer mode. The CRC checksum is a 16-bit value and is computed as follows:

generator polynomial: G(x) = x16 + x12 + x5 +1

M(x) = (first bit) * xn + (second bit) * xn-1 +...+ (last bit) * x0

CRC[15...0] = Remainder [(M(x) * x16) / G(x)]

All CRC registers are initialized to zero. The first bit is the first data bit of the corresponding block. The degree n of the polynomial denotes the number of bits of the data block decreased by one. For example, n = 4,095 for a block length of 512 bytes. The generator polynomial G(x) is a standard CCITT polynomial. The code has a minimal distance d=4 and is used for a payload length of up to 2,048 bytes (n < 16,383).

Figure 4-4 CRC16 Generator/Checker



4.5 Error Conditions

The following sections provide valuable information on error conditions.

4.5.1 CRC and Illegal Commands

CRC bits protect all commands. If the addressed MultiMediaCard/RS-MultiMediaCard CRC check fails, the card does not respond and the command is not executed. The card does not change its state, and the COM_CRC_ERROR bit is set in the Status Register.

Similarly, if an illegal command has been received, an MMC/RS-MMC will not change its state or respond, and will set the ILLEGAL_COMMAND error bit in the Status Register. Only the non-erroneous state branches are shown in the state diagrams (Figure 4-1 and Figure 4-2). Table 4-7 contains a complete state transition description.

Different types of illegal commands include:

• Commands belonging to classes not supported by the MMC/RS-MMC (e.g., I/O command CMD39).

• Commands not allowed in the current state (e.g., CMD2 in Transfer State).

• Commands not defined (e.g., CMD6).

4.5.2 Read, Write and Erase Time-out Conditions

The period after which a time-out condition for read/write/erase operations occurs is (card independent) 10 times longer than the typical access/program times for the operations given in Table 4-3. A card will complete the command within this time period, or give up and return an error message. If the host does not get a response within the defined time-out it should assume the card is not going to respond any more and try to recover (e.g., reset the card, power cycle, reject). The typical access and program times are defined as shown in Table 4-3.

Table 4-3 Typical Access and Program Time

Operation Definition

Read The read access time is defined as the sum of the two times given by the CSD parameters TAAC and NSAC. These card parameters define the typical delay between the end bit of the read command and the start bit of the data block.

Write The R2W_FACTOR field in the CSD is used to calculate the typical block program time obtained by multiplying the read access time by this factor. It applies to all write/erase commands (e.g., SET(CLEAR)_WRITE_PROTECT, PROGRAM_CSD(CID) and the block write commands).

Erase The duration of an erase command will be (order of magnitude) the number of sectors to be erased multiplied by the block write delay.



4.6 Commands

The following sections provide important information on commands.

4.6.1 Command Types

There are four kinds of commands defined to control the MultiMediaCard/RS-MultiMediaCard bus as shown in Table 4-4.

Table 4-4 Command Definition

Command Abbreviation Definition

Broadcast bc Sent on CMD, no response

Broadcast w/Response bcr Sent on CMD, response3 on CMD

Addressed point-to-point ac Sent on CMD, response on CMD

Addressed point-to-point data transfer adtc Sent on CMD, response on CMD, data transfer on DAT

The command transmission always starts with the most significant bit (MSB).

4.6.2 Command Format

The command length shown in Figure 4-5 is 48 bits.

Figure 4-5 Format (2.4 µs @ 20 MHz)

0 1 bit 5….bit 0 bit 31….bit 0 bit 6….bit 0 1

start bit host command argument CRC7 end bit

Commands and arguments are listed in Table 4-6.

7-bit CRC Calculation: G(x) = x7+ x3+ 1

M(x) = (start bit)*x39 + (host bit)*x38 +…+ (last bit before CRC)*x0

CRC[6…0] = Remainder[(M(x)*x7)/G(x)]

4.6.3 Command Classes

The command set of the MultiMediaCard/RS-MultiMediaCard is divided into several classes (refer to Table 4-5). Each class supports a set of card functions.

The supported Card Command Classes (CCC) are coded as a parameter in the CSD Register data of each card, providing the host with information on how to access the card.

3 All cards simultaneously.



Table 4-5 Card Command Classes

Class 0 2 4 5 6 7 8 9 10-11

CMD Basic Block Read

Block Write

Erase Write Protection

Lock Card

Application Specific

I/O Mode

R

CMD0 +

CMD1 +

CMD2 +

CMD3 +

CMD4 +

CMD7 +

CMD9 +

CMD10 +

CMD11

CMD12 +

CMD13 +

CMD15 +

CMD16 + +

CMD17 +

CMD18 +

CMD20

CMD24 +

CMD25 +

CMD26 +

CMD27 +

CMD28 +

CMD29 +

CMD30 +

CMD32 +

CMD33 +

CMD34 +

CMD35 +

CMD36 +

CMD37 +

CMD38 +

CMD39 +

CMD40 +

CMD42 +

CMD55 +

CMD56 +

R = Reserved



4.6.4 Command Description

All future reserved commands and their responses must be 48 bits long. Responses may not have any response. Table 4-6 details the MultiMediaCard/RS-MultiMediaCard bus commands.

Table 4-6 Command Descriptions

CMD Index

Type Argument Resp. Abbreviation Description

Basic Commands (Class 0 and Class 1)

CMD0 bc [31:0] don’t care

--- GO_IDLE_STATE Reset all cards to Idle State.

CMD1 bcr [31:0] OCR w/out busy

R3 SEND_OP_COND Ask all cards in idle state to send their operation conditions register content in the response on the CMD line.

CMD2 bcr [31:0] don’t care

R2 ALL_SEND_CID Asks all cards to send their CID numbers on the CMD line.

CMD3 ac [31:16]RCA [15:0] don’t care

R1 SEND_RELATIVE_ADDR Assign relative address to the card

CMD4 Not Supported

CMD5 Reserved

CMD6 Reserved


R1 (from selected card only)

SELECT/DESELECT_CARD Toggles card between the Stand-by and Transfer states or Programming and Disconnect states. In both cases, the card is selected by its own relative address and deselected by any other address; address 0 deselects all.

CMD8 Reserved


R2

SEND_CSD Sends addressed card’s card-specific data (CSD) on the CMD line.


R2 SEND_CID Sends addressed card’s card identification (CID) on the CMD line.

CMD11 Not supported

CMD12 ac [31:0] don’t care

R1b STOP_TRANSMISSION Terminates a multiple block read/write operation.


R1 SEND_STATUS Sends addressed card’s status register.

CMD14 Reserved

CMD15 ac [31:16]RCA [15 0] d ’t

--- GO_INACTIVE_STATE Sets the card to inactive t t



CMD Index


[15:0] don’t care

state.

Block Read Commands (Class 2)

CMD16 ac [31:0] block length

R1 SET_BLOCKLEN Selects a block length (in bytes) for all subsequent block commands (read and write).

CMD17 adtc [31:0] data address

R1 READ_SINGLE_BLOCK Reads a block of the size selected by the SET_BLOCKLEN command.


R1 READ_MULTIPLE_BLOCK Sends blocks of data continuously until interrupted by a stop transmission or a new read command.

CMD19 Reserved

Block Write Commands (Class 4)


R1 WRITE_BLOCK Writes a block of the size selected by the SET_BLOCKLEN command.


R1 WRITE_MULTIPLE_BLOCK Writes blocks of data continuously until a STOP_TRANSMISSION is received.

CMD26 Not applicable

CMD27 adtc [31:0] don’t care

R1 PROGRAM_CSD Programs the programmable bits of the CSD.

Write Protection Commands (Class 6)

CMD28 ac [31:0] data address

R1b SET_WRITE_PROT Sets the write protection bit of the addressed group. The properties of write protection are coded in the card-specific data (WP_GRP_SIZE).


R1b CLR_WRITE_PROT Clears the write protection bit of the addressed group if the card provides write protection features.

CMD30 adtc [31:0] write protect data address

R1 SEND_WRITE_PROT Asks the card to send the status of the write protection bits if the card provides write protection features.

CMD31 Reserved

Erase Commands (Class 5)


R1 TAG_SECTOR_START Sets the first sector’s address of the erase



CMD Index


address group.


R1 TAG_SECTOR_END Sets the address of the last sector in a continuous range within the selected erase group, or the address of a single sector to be selected for erase.


R1 UNTAG_SECTOR Removes one previously selected sector from the erase selection.


R1 TAG_ERASE_GROUP_START Sets the address of the first erase group within a range to be selected for erase.


R1 TAG_ERASE_GROUP_END Sets the address of the last erase group within a continuous range to be erased.


R1 UNTAG_ERASE_GROUP Removes one previously selected erase group from the erase selection.

CMD38 ac [31:0] don’t care

R1b ERASE Erases all previously selected write blocks.

I/O Mode Commands (Class 9)

CMD39 CMD40

MMCA Optional Command, currently not supported.

CMD41 Reserved

Lock Card Commands (Class 7)

CMD42 adtc [31:0] stuff bits

R1b LOCK_UNLOCK Used to set/reset the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command.

CMD43 … CMD54

MMCA Optional Command, currently not supported.

Application-specific Commands (Class 8)

CMD55 … CMD56

MMCA Optional Command, currently not supported



4.7 Card State Transition

Table 4-7 shows the MultiMediaCard/RS-MultiMediaCard state transition dependence on the received command.

Table 4-7 Card State Transition Table

Current Status

idle ready ident stby tran data rcv prg dis ina irq

Command Changes to

Class Independent

CRC error --- --- --- --- --- --- --- --- --- --- stby

Command not supported

--- --- --- --- --- --- --- --- --- --- stby

Class 0

CMD0 idle idle idle idle idle idle idle idle idle

--- stby

CMD1, card VDD range compatible

ready

--- --- --- --- --- --- --- --- --- stby

CMD1, card is busy

idle --- --- --- --- --- --- --- --- --- stby

CMD1, card VDD range not compatible

ina --- --- --- --- --- --- --- --- --- stby

CMD2, card wins bus

--- ident --- --- --- --- --- --- --- --- stby

CMD2, card loses bus

--- ready --- --- --- --- --- --- --- --- stby

CMD3 --- --- stby --- --- --- --- --- --- --- stby

CMD4 Not supported

CMD7, card is addressed

--- --- --- tran --- --- --- --- prg --- stby

CMD7, card is not addressed

--- --- --- -- stby stby --- dis --- --- stby

CMD9 --- --- --- stby --- --- --- --- --- --- stby

CMD10 --- --- --- stby --- --- --- --- --- --- stby

CMD12 --- --- --- --- --- tran prg --- --- --- stby

CMD13 --- --- --- stby tran data rcv prg dis --- stby

CMD15 --- --- --- ina ina ina ina ina ina --- stby

Class 2

CMD16 --- --- --- --- tran --- --- --- --- --- stby

CMD17 --- --- --- --- data --- --- --- --- --- stby

CMD18 --- --- --- --- data --- --- --- --- --- stby



Current Status

idle ready ident stby tran data rcv prg dis ina irq

Command Changes to

Class 4

CMD16 See Class 2

CMD24 --- --- --- --- rcv --- --- --- --- --- stby

CMD25 --- --- --- --- rcv --- --- --- --- --- stby

CMD26 --- --- --- --- rcv --- --- --- --- --- stby

CMD27 --- --- --- --- rcv --- --- --- --- --- stby

Class 6

CMD28 --- --- --- --- prg --- --- --- --- --- stby

CMD29 --- --- --- --- prg --- --- --- --- --- stby

CMD30 --- --- --- --- data --- --- --- --- --- stby

Class 5

CMD32 --- --- --- --- tran --- --- --- --- --- stby

CMD33 --- --- --- --- tran --- --- --- --- --- stby

CMD34 --- --- --- --- tran --- --- --- --- --- stby

CMD35 --- --- --- --- tran --- --- --- --- --- stby

CMD36 --- --- --- --- tran --- --- --- --- --- stby

CMD37 --- --- --- --- tran --- --- --- --- --- stby

CMD38 --- --- --- --- prg --- --- --- --- --- stby

Class 7

CMD42 --- --- --- --- rcv --- --- --- --- --- stby

Class 8

CMD55 MMCA Optional Command, currently not supported

CMC56: RD/WR = 0


CMD56: RD/WR = 1


Class 9

CMD39 CMD40


Class 10-11

CMD41 …CMD59


CMD60 … CMD63

Reserved for manufacturer



4.7.1 Responses

All responses are sent on the CMD line. The response transmission always starts with the MSB. The response length depends on the response type.

A response always starts with a start bit (0), followed by the bit indicating the direction of transmission (card = 0). A value denoted by x in the Table 4-8 to 4-10 indicates a variable entry. All responses except for the type R3 are protected by a CRC. The end bit (1) terminates every response.

There are five types of responses supported in the SanDisk MultiMediaCard and RS-MultiMediaCard. Their formats are defined as follows:

1) R1 (standard response): response length 48 bit.

Bits 45:40 indicate the index of the command to which it is responding. The status of the card is coded in 32 bits.

Table 4-8 Response R1

Bit Position 47 46 [45:40] [39:8] [7:1] 0

Width (bits) 1 1 6 32 7 1

Value 0 0 x x x 1

Description start bit transmission bit command index card status CRC7 end bit

2) R1b is identical to R1 with the additional busy signal transmitted on the data line. 3) R2 (CID, CSD register): response length 136 bits.

The content of the CID register is sent as a response to CMD2 and CMD10. The content of the CSD register is sent as a response to CMD9. The only bits transferred are [127...1] of the CID and CSD; Bit [0] of these registers is replaced by the end bit of the response.


Bit Position 135 134 [133:128] [127:1] 0

Width (bits) 1 1 6 127 1

Value 0 0 111111 x 1

Description start bit transmission bit reserved CID or CSD register inc. internal CRC7

end bit



4) R3 (OCR register): response length 48 bits.

The contents of the OCR Register are sent as a response to CMD1.


Bit Position 47 46 [45:40] [39:8] [7:1] 0

Width (bits) 1 1 6 32 7 1

Value 0 0 111111 x 111111 1

Description start bit transmission bit reserved OCR Register reserved end bit

R4 and R5: responses are not supported.

4.8 Timing Diagrams

All timing diagrams use schematics and abbreviations listed in Table 4-11.

Table 4-11 Timing Diagram Symbols

Symbol Definition

S Start Bit (= 0)

T Transmitter Bit (Host = 1, Card = 0)

P One-cycle pull-up (= 1)

E End Bit (= 1)

Z High Impedance State (-> = 1)

D Data bits

X Repeater

CRC Cyclic Redundancy Check Bits (7 bits)

Card active

Host active

4.8.1 Command and Response

Card Identification and Card Operation Conditions Timing

The card identification (CMD2) and card operation conditions (CMD1) timing are processed in the open-drain mode. The card response to the host command starts after exactly NID clock cycles.

Identification Timing (Card ID Mode)

S T Content E Z ****** Z S T Z Z Z

Host Command NID

CMD CRC Content

CID or OCRCycles



The minimum delay between the host command and card response is NCR clock cycles. This timing diagram is relevant for host command CMD3.

Command Response Timing (ID Mode)

Data Transfer Mode

There is just one Z bit period followed by P bits pushed up by the responding card. This timing diagram is relevant for all responded host commands except CMD1, 2, 3.

Command Response Timing (Data Transfer Mode)

Last Card Response—Next Host Command Timing

After receiving the last card response, the host can start the next command transmission after at least NRC clock cycles. This timing is relevant for any host command.

Timing Response End to Next CMD Start (Data Transfer Mode)

Last Host Command—Next Host Command Timing

After the last command has been sent, the host can continue sending the next command after at least NCC clock periods. This timing is relevant for any host command that does not have a response.

Timing CMDn End to CMDn+1 Start (all modes)

In the case where the CMDn command was a last acquisition command with no further response by any card, then the next CMDn+1 command is allowed to follow after at least NCC +136 (the length of the R2 response) clock periods.

CMD S T Content E Z ****** Z S T Z Z Z

Host Command NCR

CRC

ResponseCycles

Content CRC ZE

CMD S T Content E Z *** P S T Z Z Z

Host Command NCR

CRC

ResponseCycles

Content CRC ZEZ P

CMD S T Content E Z ****** Z S T Z

Response NRC

CRC

Host CommandCycles

Content CRC E

CMD S T Content E Z ****** Z S T Z

Host Command NCC

CRC

Host CommandCycles

Content CRC E



4.9 Data Read

Single Block Read

The host selects one card for data read operation by CMD7 and sets the valid block length for block-oriented data transfer by CMD16. The basic bus timing for a read operation is shown in the Transfer of Single Block Read timing diagram. The sequence starts with a single block read command, CMD17 that specifies the start address in the argument field. The response is sent on the CMD line as usual.

Transfer of Single Block Read

Data transmission from the card starts after the access time delay NAC beginning from the end bit of the read command. After the last data bit, the CRC check bits are suffixed to allow the host to check for transmission errors.

Multiple Block Read

In multiple block read mode, the card sends a continuous flow of data blocks following the initial host read command. The data flow is terminated by a stop transmission command, CMD12. The Timing of Multiple Block Read Command timing diagram describes the timing of the data blocks, and the Timing of Stop Command (CMD12,Data Transfer Mode) timing diagram describes the response to a stop command. The data transmission stops two clock cycles after the end bit of the stop command.

Timing of Multiple Block Read Command

Timing of Stop Command (CMD12, Data Transfer Mode)

CMD S T Content E Z *** P S TCRC

ResponseCycles

Content CRC EZ P

DAT Z Z **** Z Z **********Z P S D

NAC Read DataCycles

DZ Z Z Z P D ***

CMD S T E Z * P S TResponse

CRC EZ P

DAT Z Z **** Z Z **********Z P S D DZ Z Z Z P D *****

Z PZ P P PP P PPP P P P PNCRCycles

D E P ********** P DDS D D D

Content CRC ContentHost Command

NACCyclesNAC Cycles Read Data Read Data

CMD S T E Z *** P S TZ PNCRCycles

Content CRCHost Command

Content ECRC

D D D ******** D D D E Z Z **********

Response

DAT



4.10 Data Write

Single Block Write

The host selects one card for data write operation by CMD7. The host sets the valid block length for block-oriented data transfer by CMD16.

The basic bus timing for a write operation is shown in the Block Write Command timing diagram. The sequence starts with a single block write command, CMD24 that determines (in the argument field) the start address. The card responds on the CMD line, and the data transfer from the host starts NWR clock cycles after the card response was received.

The data is suffixed with CRC check bits to allow the card to check it for transmission errors. The card sends back the CRC check result as a CRC status token on the data line. In the case of transmission error, the card sends a negative CRC status (“101”). In the case of non-erroneous transmission, the card sends a positive CRC status (“010”) and starts the data programming procedure.

Block Write Command Timing

If the MultiMediaCard/RS-MultiMediaCard does not have a free data receive buffer, it indicates this condition by pulling down the data line to low. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer block length becomes free. This signaling does not give any information about the data write status that must be polled by the host.

Multiple Block Write

In multiple block write mode, the card expects continuous flow of data blocks following the initial host write command. The data flow is terminated by a stop transmission command (CMD12). The Multiple Block Write Command timing diagram describes the timing of the data blocks with and without card busy signal.

Multiple Block Write Command Timing

In write mode, the stop transmission command works similarly to the stop transmission command in the read mode. The following figure describe the timing of the stop command in different card states.

CMD E Z

Busy

CRC E

DAT Z Z **** SZ Z Z

Z Z P P PP P PPP PNCR Card Response

E S E Z

Content

HostCommand

NWR Write Data CRC Status

Z P * P S ******************

***Z Z Z Z P*P Content CRC E Z Z S Status L*L

T

CMD E Z

BusyDAT Z Z P*P S ZE

P P PP P PPP PNWR

E S

CardResponse

NWRWrite Data CRC Status

Z P *******************

E Z SP*PData+CRC E Z Z S Status L*L

P P P P *********************

Data+CRC E Z Z S Status

P

P*PWrite Data CRC Status NWR



Stop Transmission During Data Transfer from the Host

The card will treat a data block as successfully received and ready for programming only if the CRC data of the block was validated and the CRC status token sent back to the host. The figure below is an example of an interrupted (by a host stop command) attempt to transmit the CRC status block. The sequence is identical to all other stop transmission examples. The end bit of the host command is followed, on the data line, with one more data bit, end bit and two Z clock for switching the bus direction. The received data block in this case is considered incomplete and will not be programmed.

Stop Transmission during CRC Status Transfer from the Card

All previous examples dealt with the scenario of the host stopping the data transmission during an active data transfer. The following two diagrams describe a scenario of receiving the stop transmission between data blocks. In the first example, the card is busy programming the last block while the card is idle as shown in the second diagram. However, there remains un-programmed data blocks in the input buffers. These blocks are being programmed as soon as the stop transmission command is received and the card activates the busy signal.

Stop Transmission Received after Last Data Block—Card Busy Programming

Stop Transmission Received after Last Data Block—Card becomes Busy

Erase, Set and Clear Write Protect Timing

The host must first tag the sectors to erase using the tag commands, CMD32-CMD37. The erase command, CMD38 once issued, will erase all tagged sectors. Similarly, set and clear write protect commands start a programming operation as well. The card will signal “busy” (by pulling the DAT line low) for the duration of the erase or programming operation.

CMD S T

DAT ZZ

E S T

Z Z

Card Response

Z

Content

*********

Z Z P S

E Z Z

E

Card is Programming

Host Command

Content P* ****P T Content CRCCRC

Z

Host Command NCRCycles

D D D D D Z SD D D D D E LZ

CMD S T

DAT ZZ

E S T

Z Z

Card Response

Z

Content

*********

Z Z P S

E Z Z

E

Card is Programming

Host Command


Z


D D D D Z Z SD Z S E LZData Block

CRCCRC Status

CMD S T

DAT ZZ

E S T

Z Z

Card Response

Z

Content

******************************************************************

Z Z P S

E Z Z

E

Card is Programming

Host CommandContent P* **P T Content CRCCRC

Z


S L L

CMD S T

DAT ZZ

E S T

Z Z

Card Response

Z

Content

*********************

Z Z P S

E Z Z

E

Card is Programming

Host Command


Z


Z Z Z Z Z Z SZ Z Z LZ Z L



4.11 Timing Values

Table 4-12 defines all timing values.

Table 4-12 Timing Values

Value Min. Max. Unit

NCR 2 64 Clock cyclesNID 5 5 Clock cyclesNAC 2 Note Clock cycles

NRC 8 --- Clock cycles

NCC 8 --- Clock cycles

NWR 2 --- Clock cycles

NOTE: 10 * ((TAAC*f) + (100*NSAC))]* where f is the clock frequency.

Chapter 5 –SPI Mode Revision 1.0 MultiMediaCard/RS-MultiMediaCard Product Manual


5 SPI Mode SPI mode is a secondary, optional communication protocol, which is offered by the MultiMediaCard and RS-MultiMediaCard. This mode is a subset of the MultiMediaCard Protocol, designed to communicate with an SPI channel, commonly found in some vendors’ microcontrollers. The interface is selected during the first reset command after power up (CMD0) and cannot be changed once the part is powered on.

The SPI standard defines the physical link only, and not the complete data transfer protocol. The MultiMediaCard/RS-MultiMediaCard SPI implementation uses a subset of the MultiMediaCard Protocol and command set because it pertains to systems that require a small number of cards (typically one) and have lower data transfer rates (compared to MultiMediaCard Protocol-based systems). From the application point of view, the advantage of the SPI mode is the capability of using an off-the-shelf host, hence reducing the design-in effort to a minimum. The disadvantage is the loss of performance with SPI mode as compared to MultiMediaCard mode (lower data transfer rate, fewer cards, hardware CS per card, etc.).

5.1 SPI Interface Concept The SPI is a general purpose synchronous serial interface originally found on certain Motorola microcontrollers. A virtually identical interface can now be found on some other microcontrollers as well.

The MultiMediaCard SPI interface is compatible with SPI hosts available on the market. As in any other SPI device, the MultiMediaCard SPI channel consists of the following four signals:

• CS—Host to card Chip Select signal

• CLK—Host to card clock signal

• DataIn—Host to card data signal

• DataOut—Card to host data signal

Byte transfers are another common SPI characteristic. They are implemented in the card as well. All data tokens are multiples of bytes (8-bit) and always byte aligned to the CS signal.

5.2 SPI Bus Topology Card identification and addressing methods are replaced by the hardware Chip Select (CS) signal; there are no broadcast commands. For every command, a card (slave) is selected by asserting (active low) the CS signal. See the following figure.

The CS signal must be continuously active for the duration of the SPI transaction (command, response and data). The only exception occurs during card programming when the host can de-assert the CS signal without affecting the programming process.

The bi-directional CMD and DAT lines are replaced by unidirectional dataIn and dataOut signals. This eliminates the ability to execute commands while data is being read or written and, therefore, makes the sequential and multi block read/write operations obsolete. The SPI channel supports single block read/write commands only.

The SPI interface uses the same seven signals as the standard MultiMediaCard bus (Figure 5-1).



Figure 5-1 MultiMediaCard/RS-MultiMediaCard Bus System

Table 5-1 SPI Interface Pin Configuration

MultiMediaCard Mode SPI Mode Pin #

Name Type1 Description Name Type Description

1 RSV NC Reserved for future use

CS I Chip Select (neg true)

2 CMD I/O/PP/OD Command/Response

DI I/PP Data In

3 VSS1 S Supply voltage ground

VSS S Supply voltage ground

4 VDD S Supply voltage VDD S Supply voltage

5 CLK I Clock SCLK I Clock

6 VSS2 S Supply voltage ground

VSS2 S Supply voltage ground

7 DAT I/O/PP Data DO O/PP Data Out

1) S: power supply; I: input; O: output; PP: push-pull; OD: open-drain; NC: Not connected (or logical high).

SPI Bus Master

SPI Card SPI Card

Power Supply

SPI Bus (CLK, DataIn, DataOut)

CS

CS



5.3 Card Registers in SPI Mode The register usage in SPI mode is summarized in Table 5-2. Most of them are inaccessible.

Table 5-2 MultiMediaCard/RS-MultiMediaCard Registers in SPI Mode

Name Available in SPI mode Width [Bytes] Description

CID Yes 16 Card identification data (serial number, manufacturer ID, etc.).

RCA No

DSR No

CSD Yes 16 Card-specific data, information about the card operation conditions.

OCR Yes 32 Operation condition register.

5.4 SPI Bus Protocol While the MultiMediaCard channel is based on command and data bit streams, which are initiated by a start bit and terminated by a stop, bit, the SPI channel is byte oriented. Every command or data block is built of 8-bit bytes and is byte aligned to the CS signal (i.e., the length is a multiple of 8 clock cycles).

Similar to the MultiMediaCard Protocol, SPI messages consist of command, response and data-block tokens. The host (master) controls all communication between the host and cards. The host starts every bus transaction by asserting the CS signal low.

The response behavior in SPI mode differs from MultiMediaCard mode in the following three aspects:

· Selected card always responds to the command.

· Additional (8, 16 and 40 bit) response structures are used.

· Card encounters a data retrieval problem, it will respond with an error response (which replaces the expected data block) rather than by a time-out, as in the MultiMediaCard mode.

Only single and multiple block read/write operations are supported in SPI mode (sequential mode is not supported). In addition to the command response, every data block sent to the card during a write operation will be responded to with a special data response token. A data block may be as big as one card sector and as small as a single byte. Partial block read/write operations are enabled by card options specified in the CSD register.

5.5 Mode Selection The MultiMediaCard and RS_MultiMediaCard “wake up” in the MultiMediaCard mode. The card will enter SPI mode if the CS signal is asserted (negative) during the reception of the reset command (CMD0). Selecting SPI mode is not restricted to Idle state (the state the card enters after power up) only. Every time the card receives CMD0, including while in Inactive state, CS signal is sampled.

If the card recognizes that MultiMediaCard mode is required (CS signal is high), it will not respond to the command and remain in MultiMediaCard mode. If SPI mode is required



(CS signal low), the module will switch to SPI mode and respond with the SPI mode R1 response.

The only way to return to MultiMediaCard mode is by a power cycle (turning the power off and on). In SPI mode, the MultiMediaCard protocol state machine is not observed. All of the MultiMediaCard commands supported in SPI mode are always available.

5.6 Bus Transfer Protection CRC bits protect every MultiMediaCard/RS-MultiMediaCard token transferred on the bus. In SPI mode, the card offers a non-protected mode that enables systems built with reliable data links to exclude the hardware or firmware required for implementing the CRC generation and verification functions.

The SPI interface is initialized in the non-protected mode. However, the RESET command (CMD0), which is used to switch the card to SPI mode, is received by the card while in MultiMediaCard mode and, therefore, must have a valid CRC field.

Since CMD0 has no arguments, the content of all the fields, including the CRC field, are constants and need not be calculated in run time. A valid reset command is:

0x40, 0x0, 0x0, 0x0, 0x0, 0x95

The host can turn the CRC option on and off using the CRC_ON_OFF command (CMD59).

5.7 Data Read SPI Mode supports single block and multiple-block read operations The main difference between SPI and MultiMediaCard modes is that the data and the response are both transmitted to the host on the DataOut signal. Therefore, the card response to the STOP_COMMAND might end abruptly and replace the last data block. (Figure 5-2).

Figure 5-2 Single Block Read Operation

The basic unit of data transfer is a block whose maximum size is defined in the CSD (READ_BL_LEN). If READ_BL_PARTIAL is set, smaller blocks whose starting and ending address are entirely contained within one physical block (as defined by READ_BL_LEN) may also be transmitted. A CRC is appended to the end of each block ensuring data transfer integrity. CMD17 (READ_SINGLE_BLOCK) initiates a single block read.

CMD18 (READ_MULTIPLE_BLOCK) starts a transfer of several consecutive blocks. The number of blocks for the multiple block read operation is not defined. The card will continuously transfer data blocks until a stop transmission command is received.

CommandDataIn Command

Response Data Block CRC

From Hostto Card

From Cardto Host

Data fromCard to Host

Next Command

DataOut



Figure 5-2 Multiple Block Read Operation

In case of a data retrieval error, the card will not transmit any data. Instead, a special data error token will be sent to the host. Figure 5-4 shows a single block-read operation, which terminated with an error token rather than a data block. Figure 5-4 Read Operation—Data Error

The multiple block read operation can be terminated the same way by the error token replacing a data block anywhere in the sequence. The host must then abort the operation by sending the Stop Transmission command.

If the host sends a Stop Transmission command out of the valid sequence, it will be responded to as an illegal command.

If the host uses partial blocks whose accumulated length is not block aligned and block misalignment is not allowed, the card detects a block misalignment error condition at the beginning of the first misaligned block (ADDRESS_ERROR error bit is set in the data error token).

5.8 Data Write In SPI Mode, the MultiMediaCard/RS-MultiMediaCard supports single block or multiple block write operations. Upon reception of a valid write command (CMD24 or CMD25), the card will respond with a response token and wait for a data block to be sent from the host. CRC suffix, block address, and start address restrictions are identical to the read operation. If a CRC error is detected it will be reported in the data-response token and the data block will not be programmed.

CommandDataIn Command

Response Data Error

From Hostto Card

From Cardto Host

Data ErrorToken fromCard to Host

Next Command

DataOut

DataIn

From hostto card(s)

DataOut

Command

From cardto host

Data Block CRCResponse Data Block CRC Response

StopTransmissioncommand

Data fromcard to host

Data Block

Command



Figure 5-7 Single Block Write Operation

Every data block has a prefix or “start block” token (one byte). After a data block is received, the MultiMediaCard/RS-MultiMediaCard will respond with a data-response token, and if the data block is received with no errors, it will be programmed. A continuous stream of busy tokens will be sent to the host (effectively holding the dataOut line low) for the duration of time the card is busy, programming.

In multiple-block write operations, the stop transmission is accomplished by sending, at the beginning of the next block, a Stop Tran token, instead of a Start Block token.

Figure 5-9 Multiple Block Write Operation

The number of blocks for the write multiple block operation is not defined. The card will continuously accept and program data blocks until a ‘Stop Tran’ token is received.

If the card detects a CRC error or a programming error (e.g., write protect violation, out of range, address misalignment, internal error) during a multiple block write operation, it will report the failure in the data-response token and ignore any further incoming data blocks. The host must then abort the operation by sending the ‘Stop Tran’ token.

If the host uses partial blocks whose accumulated length is not block aligned and block misalignment is not allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card detects the block misalignment error before the beginning of the first misaligned block and responds with an error indication in the data response token, ignoring any further incoming data blocks. The host must then abort the operation by sending the ‘Stop Tran’ token.

Once the programming operation is completed (either successfully or with an error), the host must check the results of the programming (or the cause of the error if already reported in the data-response token) using the SEND_STATUS command (CMD13).

Resetting the CS signal while the card is busy does not terminate the programming process. Instead, the card releases the dataOut line (tri-state) and continues programming. If the card

CommandDataIn

From hostto card

Data fromhost tocard

DataOut

Data Block

Data_Response Busy

Newcommandfrom host

From cardto host

Command

Response

Start blocktoken

Dataresponseand busyfrom card

CommandDataIn

From hostto card


DataOut

DataBlock

Data_Response Busy


From cardto host

Response

Start blocktoken

Dataresponseand busyfrom card

Data_Response Busy Busy

DataBlock

Stop trantoken



is reselected before the programming has finished, the dataOut line will be forced back to low and all commands will be rejected.

Resetting a card (using CMD0) will terminate any pending or active programming operation. However, this may destroy data formats on the card. It is the host’s responsibility to prevent that from happening.

5.9 Erase and Write Protect Management Erase and Write Protect Management procedures in SPI Mode and MultiMediaCard mode are identical. When the card is erasing or changing the write protection bits of the predefined write-protect group list, it will be in a busy state and hold the dataOut line low. Figure 5-11 illustrates a “no data” bus transaction with and without busy signaling.

Figure 5-11 No Data Operations

5.10 Read CID/CSD Registers Unlike MultiMediaCard Protocol where the register contents are sent as a command response, SPI Mode provides a simple read block transaction for reading the contents of the CSD and CID registers. The card will respond with a standard response token followed by a data block of 16 bytes, suffixed with a 16-bit CRC.

The data timeout for the CSD command cannot be set to the card TAAC because its value is stored in the CSD. Therefore, the standard response timeout value (NCR) is used for read latency of the CSD register.

5.11 Reset Sequence The MultiMediaCard/RS-MultiMediaCard requires a defined reset sequence. After power-on reset or software reset (CMD0), the card enters an idle state. In this state, the only legal host commands are CMD1 (SEND_OP_COND) and CMD58 (READ_OCR).

The host must poll the card by repeatedly sending CMD1 until the “in-idle-state” bit in the card response indicates, by being set to 0, that the card completed its initialization processes and is ready for the next command.

However, in SPI mode, CMD1 has no operands and does not return the contents of the OCR Register. Instead, the host can use CMD58 (SPI Mode Only) to read the register. It is the responsibility of the host to refrain from accessing cards that do not support its voltage range.

The use of CMD58 is not restricted to the initialization phase only, but can be issued at any time. The host must poll the card by repeatedly sending CMD1 until the “in-idle-state” bit

CommandDataIn

Response

From Hostto Card

From Hostto Card

DataOut

Command

Response Busy

From Cardto Host

From Cardto Host



in the card response indicates, by being set to 0, that the card has completed its initialization process and is ready for the next command.

5.12 Clock Control The SPI Bus clock signal can be used by the SPI host to set the cards to energy-saving mode or to control the data flow to avoid under-run or over-run conditions on the bus. The host is allowed to change the clock frequency or shut it down.

There are a few restrictions the SPI host must follow:

• The bus frequency can be changed at any time under the restrictions of maximum data transfer frequency, defined by the MultiMediaCard/RS-MultiMediaCard.

• The clock must be running for the card to output data or response tokens.

After the last SPI bus transaction, the host is required to provide eight clock cycles for the card to complete the operation before shutting down the clock. The state of the CS signal is irrelevant throughout this eight-clock period. The signal can be asserted or de-asserted. Various SPI bus transactions are listed below.

− Command/response sequence; occurs eight clocks after the card response end bit. The CS signal can be asserted or de-asserted during the eight clocks.

− Read data transaction; occurs eight clocks after the end bit of the last data block. − Write data transaction; occurs eight clocks after the CRC status token.

• The host is allowed to shut down the clock of a busy card. The MultiMediaCard/RS-MultiMediaCard will complete the programming operation regardless of the host clock. However, the host must provide a clock edge for the card to turn off its busy signal. Without a clock edge, the card (unless previously disconnected by de-asserting the CS signal) will permanently force the dataOut line down.

5.13 Error Conditions The following sections provide valuable information on error conditions.

5.13.1 CRC and Illegal Commands

The CRC bits provide an optional protection of all commands. If the addressed MultiMediaCard/RS-MultiMediaCard CRC check fails, the COM_CRC_ERROR bit will be set in the card's response. Similarly, if an illegal command has been received, the ILLEGAL_COMMAND bit will be set in the card’s response.

Types of illegal commands include:

• Command belongs to a class not supported by the MultiMediaCard/RS-MultiMediaCard − For example, Interrupt and I/O commands

• Command not allowed in SPI Mode

• Command is not defined − For example, CMD6

5.13.2 Read, Write and Erase Timeout Conditions

The time period after which a timeout condition for read/write/erase operations occur is card independent and ten times longer than the typical access/program times for these operations given in Table 5-1. A card will complete the command within the stated time



period or return an error message. If the host does not get any response within the given timeout, it ascertains that the card is not going to respond any further and will try to recover (e.g., reset module, power cycle, reject). The typical access and program times are defined in Table 5-3.

Table 5-3 Timeout Conditions

Operation Access and Program Times

Read The read access time is defined as the sum of the two times given by the CSD parameters TAAC and NSAC. These card parameters define the typical delay between the end bit of the read command and the start bit of the data block. This number is card dependent.

Write The R2W_FACTOR field in the CSD is used to calculate the typical block program time obtained by multiplying the read access time by this factor. It applies to all write/erase commands (e.g., SET (CLEAR)_WRITE_PROTECT, PROGRAM_CSD (CID) and block write commands).

Erase The duration of an erase command will be (order of magnitude) the number of sectors to be erased multiplied by the block write delay.

5.14 Read Ahead in Multiple Block Read Operation In Multiple Block read operations, in order to improve read performance, the card may fetch data from the memory array, ahead of the host. In this case, when the host is reading the last addresses of the memory, the card attempts to fetch data beyond the last physical memory address and generates an OUT_OF_RANGE error. Therefore, even if the host times the Stop Transmission command to stop the card immediately after the last byte of data was read, the card may already have generated the error, which will show in the response to the Stop Transmission command. The host should ignore this error.

5.15 Memory Array Partitioning Refer to MultiMediaCard Mode section.

5.16 Card Lock/Unlock Operation Refer to MultiMediaCard Mode section.

5.17 SPI Command Set The following sections provide valuable information on the SPI Command Set.

5.17.1 Command Classes

As in MultiMediaCard Mode, the SPI commands are divided into several classes, and each class supports a set of card functions as shown in Table 5-4. The MultiMediaCard/RS-MultiMediaCard supports the same set of optional command classes in both communication modes.2 The available command classes and supported commands for a specific class, however, are different in the MultiMediaCard and the SPI Communication modes.

2 There is only one command class table in the CSD register.



Table 5-4 Command Classes in SPI Mode

Class Supported Commands

CCC Descrip. 0 1 9 10 12 13 16 17 18 23 24 25 27 28 29 30 35 36 38 42 55 56 58 59

0 Basic + + + + + + +

1 NS

2 Block read + + + + +

3 NS

4 Block write + + + + +

5 Erase + + +

6 Write- protect

+ + +

7 Lock card +

8 App-specific

+ +

9 NS

10-11

R

Key: CCC = Card CMD Class

NS = Not supported in SPI mode. R = Reserved

5.17.2 Command Description

Table 5-5 provides a detailed description of the SPI Mode commands. The responses are defined in Section 4-16.

A “yes” in the SPI Mode column indicates that the command is supported in SPI Mode. With these restrictions, the command class description in the CSD is still valid. If a command does not require an argument, the value of this field should be set to zero. Reserved SPI commands are also reserved in MultiMediaCard mode.

The binary code of a command is defined by the mnemonic symbol. As an example, the content of the CMD Index field for CMD0 is (binary) “000000” and for CMD39 is (binary) “100111”.

Table 5-5 SPI Bus Command Description

CMD Index

SPI Mode

Argument Resp Abbreviation Description

CMD0 Yes None R1 GO_IDLE_STATE Resets MultiMediaCard or RS-MultiMediaCard.

CMD1 Yes None R1 SEND_OP_COND Activates the card’s initialization process.

CMD2 No --- --- --- ---

CMD3 No --- --- --- ---

CMD4 No --- --- --- ---

CMD5 Reserved

CMD6 Reserved

CMD7 No --- --- --- ---



CMD Index

SPI Mode


CMD8 Reserved

CMD9 Yes None R1 SEND_CSD Asks the selected card to send its specific data (CSD).

CMD10 Yes None R1 SEND_CID Asks the selected card to send its identification (CID).

CMD11 No --- --- --- ---

CMD12 Yes None R1 STOP_ TRANSMISSION

Forces card to stop transmission during a multiple block read operation.

CMD13 Yes None R2 SEND_STATUS Asks the selected card to send its status register.

CMD14 Reserved

CMD15 No --- --- --- ---

CMD16 Yes [31:0] block length

R1 SET_BLOCKLEN Selects a block length (in bytes) for all following block commands (read & write).

CMD17 Yes [31:0] data address

R1 READ_SINGLE_ BLOCK

Reads a block of the size selected by the SET_BLOCKLEN command.


R1 READ_MULTIPLE_ BLOCK

Continuously transfers data blocks from card to host until interrupted by a STOP_TRANSMISSION command or the requested number of data blocks transmitted.

CMD19 Reserved

CMD20 No --- --- --- ---

CMD21 … CMD23

Reserved


R1 WRITE_BLOCK Writes a block of the size selected by the SET_BLOCKLEN command.


R1 WRITE_MULTIPLE_ BLOCK

Continuously writes blocks of data until a stop transmission token is sent or the requested number of blocks is received.

CMD26 No --- --- --- ---

CMD27 Yes None R1 PROGRAM_CSD Programming of the programmable bits of the CSD.


R1b SET_WRITE_PROT If the card has write protection features, this command sets the write protection bit of the addressed group. Write protection properties are coded in the card-specific



CMD Index

SPI Mode


data (WP_GRP_SIZE).


R1b CLR_WRITE_PROT If the card has write protection features, this command clears the write protection bit of the addressed group.

CMD30 Yes [31:0] write protect data address

R1 SEND_WRITE_PROT If the card has write protection features, this command asks the card to send the status of the write protection bits.

CMD31 Reserved


R1 TAG_SECTOR_START Sets the address of the first sector of the erase group.


R1 TAG_SECTOR_END Sets the address of the last sector in a continuous range within the selected erase group, or the address of a single sector to be selected for erase.


R1 UNTAG_SECTOR Removes one previously selected sector from the erase selection.


R1 TAG_ERASE_GROUP_START

Sets the address of the first erase group within a range to be selected for erase.


R1 TAG_ERASE_GROUP_END

Sets the address of the last erase group within a continuous range to be selected for erase.


R1 UNTAG_ERASE_ GROUP

Removes one previously selected erase group from the erase selection.

CMD38 Yes [31:0] stuff bits

R1b ERASE Erases all previously selected sectors.

CMD39 No --- --- --- ---

CMD40 No --- --- --- ---

CMD41 Reserved

CMD42 Yes [31:0] stuff bits

R1b LOCK_UNLOCK Set/resets the password or lock/unlock the card. The size of the Data Block is defined by the SET_BLOCK_LEN command.

CMD43 … CMD54

Reserved

CMD55 Yes This optional MMCA command is not supported in the SanDisk MultiMediaCard/RS-MultiMediaCard.

CMD56 Yes This optional MMCA command is not supported in the SanDisk MultiMediaCard/RS-MultiMediaCard.

CMD57 Reserved



CMD Index

SPI Mode


CMD58 Yes None R3 READ_OCR Reads the OCR Register of a card.

CMD59 Yes [31:1] stuff bits, [0:0] CRC option

R1 CRC_ON_OFF Turns the CRC option on or off. A “1” in the CRC option bit will turn the option on; a “0” will turn it off.

CMD60-CMD63

No --- --- --- ---

5.18 Responses There are several types of response tokens and all are transmitted MSB first.

5.18.1 R1 Format

The card sends this response token after every command with the exception of SEND_STATUS commands. It is one-byte long, the MSB is always set to zero, and the other bits are error indications (1= error).

The structure of the R1 format is shown in Figure 5-13 and the error definitions are listed in Table 5-6.

Figure 5-13 R1 Response Format

Table 5-6 R1 Response

Error Indication Definition

Idle State The card is in an idle state and running initializing process.

Erase reset An erase sequence was cleared before execution because an out-of-erase sequence command was received.

Illegal command An illegal command code was detected.

Communication CRC error The CRC check of the last command failed.

Erase sequence error An error in the sequence of erase commands occurred.

Address error A misaligned address that did not match the block length was used in the command.

Parameter error The command’s argument (e.g., address, block length) was out of the allowed range for this card.

7

0

0

Idle StateErase ResetIllegal CommandCom CRC ErrorErase Seq ErrorAddress ErrorParameter Error



5.18.2 R1b Format

This response token is identical to R1 format with the optional addition of the busy signal.

The busy signal token can be any number of bytes. A zero value indicates card is busy. A non-zero value indicates card is ready for the next command.

5.18.3 R2 Format The card sends the two-byte-long response token a response to the SEND_STATUS command. The format of the R2 status is shown in Figure 5-15.


The first byte is identical to response R1. The content of the second byte is defined in Table 5-7.

Table 5-7 R2 Response

Error Indication Definition

Out of range/CSD overwrite This status bit has two functions. It is set if the command argument was out of its valid range, or if the host is trying to change the ROM section or reverse the copy bit (set as original) or permanent WP bit (un-protect) of the CSD register.

Erase parameter An invalid selection, sectors, or groups for erase.

Write protect violation The command tried to write to a write-protected block.

Card ECC failed The card’s internal ECC was applied but failed to correct the data.

CC error Internal card controller error.

Error A general or an unknown error occurred during the operation.

Write protect erase skip This status bit has two functions. It is set when the host attempts to erase a write-protected sector or if a sequence or password error occurred during a card lock/unlock operation.

Card is locked This bit is set when the user locks the card. It is reset when it is unlocked.

7

0

0 7 0Byte 1 Byte 2

Com CRC Error

Address Error

Idle State

CC Error

WP Violation

Card is LockedWP EraseSkip, Lock/Unlock Cmd FailedError

Erase Parameter

Parameter Error

Erase ResetIllegal Command

Erase Sequence Error

Card ECC Failed

Out-of-Range, CSD_Overwrite



5.18.4 R3 Format

The card sends this response token when an READ_OCR command is received. The response length is five bytes. The structure of the first byte (MSB) is identical to response type R1. The other four bytes contain the OCR Register.


5.18.5 Data Response

Every data block written to the card is acknowledged by a data response token. The token is one byte long and has the format shown in Figure 5-18.

Figure 5-18 Data Response Format

The meaning of the status bits is defined as follows:

• 010 —Data accepted.

• 101 —Data rejected due to a CRC error.

• 110 —Data rejected due to a write error

In case of any error, CRC or Write, during a Write Multiple Block operation, the host will abort the operation using the Stop Transmission token. In case of a write error, the host may send CMD13 (SEND_STATUS) in order to discover the cause of the write problem.

5.19 Data Tokens Read and write commands have data transfers associated with them. Data is being transmitted or received via data tokens. All data bytes are transmitted MSB first.

Data tokens are 4 to (N+3) bytes long3 and have the following format:

• First byte: Start Block.

• Bytes 2-(N+1): User data.

• Last two bytes: 16-bit CRC.

3 N = the data block length set by the SET_BLOCK_LENGTH command

39

0

32 31 0

R1 OCR

7

x x x 0

0

Status 1

6



Table 5-8 Start Data Block Token Format

Token Type Transaction Type 7 Bit Position 0

Start Block Single Block Read 1 1 1 1 1 1 1 0

Start Block Multiple Block Read 1 1 1 1 1 1 1 0

Start Block Single Block Write 1 1 1 1 1 1 1 0

Start Block Multiple Block Write 1 1 1 1 1 1 0 0

Stop Tran Multiple Block Write 1 1 1 1 1 1 0 1

5.20 Data Error Token If a read operation fails and the card cannot provide the required data it will send a data error token instead. This token is one byte long and has the format shown in Figure 5-19.

Figure 5-19 Data Error Token

The four least significant bits (LSB) are the same error bits as in the response format R2.

5.21 Clearing Status Bits In SPI Mode, status bits are reported to the host in three different formats: response R1, response R2, and data-error token.4 Similar to MultiMediaCard Mode, error bits are cleared when read by the host, regardless of the response format.

Table 5-9 SPI Mode Status Bits

Identifier Inc in Resp. Type Value Description Clear Cond.

Out of range R2 DataErr E R X 0 = no error 1 = error

Command argument was out of the allowed range for this card.

C

Address error R1 R2 E R X 0 = no error 1 = error

A misaligned address that did not match the block length was used in the command.

C

Erase sequence error

R1 R2 E R 0 = no error 1 = error

An error in the sequence of erase commands occurred.

C

Erase parameter

R2 E X 0 = no error 1 = error

An error in the parameters of the erase command sequence occurred.

C

4 The same bits may exist in multiple response types—e.g., Card ECC failed.

7

0 0 0

0

ErrorCC ErrorCard ECC failedOut of rangeCard Locked



Identifier Inc in Resp. Type Value Description Clear Cond.

Parameter error

R1 R2 E R X 0 = no error 1 = error

An error in the parameter of the command

C

WP violation R2 E R X 0 = not protected 1 = protected

Attempt to program a write-protected block.

C

Com CRC error


The CRC check of the previous command failed.

C

Illegal command


Command not legal for the card state

C

Card ECC failed

R2 DataEr E X 0 = success 1 = failure

Card internal ECC was applied but failed to correct the data.

C

CC error R2 DataEr E R X 0 = no error 1 = error

Internal card controller error C

Error R2 DataEr E R X 0 = no error 1 = error

A general or an unknown error occurred during the operation

C

WP erase skip

R2 S X 0 = not protected 1 = protected

Only partial address space was erased due to existing write protected blocks

C

Lock/unlock CMD failed


Sequence or password error during card lock/unlock operation

C

Card is locked

R2 DataEr S X 0 = card is not locked 1 = card is locked

Card is locked by a user password

A

Erase reset R1 R2 S R 0 = cleared 1 = set

An erase sequence was cleared before executing because an out of erase sequence command was received.

C

in Idle state R1 R2 S R 0 = card ready 1 = card in idle state

The card enters the idle state after a power up or reset command. It will exit this state and become ready upon completion of its initialization procedures.

A

CSD overwrite


The host is trying to change the ROM section, or is trying to reverse the copy bit (set as original) or permanent WP bit (un-protect) of the CSD register.

C



5.22 Card Registers In SPI Mode, only the OCR, CSD and CID registers are accessible. Although the registers’ format is identical to those in MultiMediaCard Mode, a few fields are irrelevant in SPI Mode.

5.23 SPI Bus Timing Diagrams All timing diagrams use the schematics and abbreviations listed in Table 5-10.

Table 5-10 SPI Bus Timing Abbreviations

Symbol Definition

H Signal is high (logical 1)

L Signal is low (logical 0)

X Don’t care (undefined value)

Z High impedance state (-> = 1)

* Repeater

Busy Busy token

Command Command token

Response Response token

Data block Data token

The host must keep the clock running for at least NCR clock cycles after the card response is received. This restriction applies to command and data response tokens.

5.23.1 Command and Response

This section provides valuable information on commands and responses.

Host Command to Card Response—Card is Ready

Figure 5-20 describes the basic command response (no data) in an SPI transaction.

Figure 5-20 Host Command to Card Response—Card is Ready

Host Command to Card Response--Card is Busy

The timing diagram in Figure 5-21 illustrates the command response transaction for commands when the card response is of type R1b—for example, SET_WRITE_PROT and ERASE.

When the card is signaling busy, the host may de-select it by raising the CS at any time. The card will release the DataOut line one clock after CS goes high. To check if the card is still busy, it needs to be re-selected by asserting the CS signal (set to low). The card will resume the busy signal, pulling DataOut low, one clock after the falling edge of CS.

H HHHHL

X HX

ZZ HHZ

H

H HHH XXXX

*******************L

H H HH

L L

H

Z1 or 2 Bytes Response************* H

DataIn

CS

DataOut

HH H H

H H H

L

H 6 Bytes Command

ZH

LL

H H*******************

H H H H

N CR

N CS N EC



Figure 5-21 Command Response Transaction Timing, Card is Busy

Card Response to Host Command

Figure 5-22 Card Response to Next Host Command Timing

5.23.2 Data Read

This section provides valuable information on the Data Read function.

Card Response to Host Command

Figure 5-23 Single Block Read Transaction Timing

Multiple Block Read— Stop transmission is sent between blocks

Figure 5-24 Multiple Block Transaction Timing (no data overlap)

The timing for de-asserting the CS signal after the last card response is identical to a standard command/response transaction.

Multiple Block Read—Stop transmission is sent within a block

Figure 5-25 Multiple Block Transaction (data overlap)

H HHHHL

X HHH

ZZ HHHHH

NCR

N CS

L

H HHH XXXX

*******************

NAC

L

H

NEC*******************

H HData Block

HH H

HH

L LL

H H

Z Z ZHH********H

Read Command

H H H Card Response

DataIn

CS

DataOut

H LLLLL

X HHH

ZZ HHH H HHHH ********NCR

NCS

L

H HHH HHHH

*******************

N AC

L

H

H

H H HN AC NCR

******************* StopCommand

H HData Block Data Block

H H H H

Card Resp Card RespHH

Read CommandDataIn

CS

DataOut

H LLLLL

X HHHHHHHH

ZZ HHH H HHHH ** H******** Data

Read Command

Card Resp

NCR

N CS

L

H

HCard Resp

H HHH HHHH

*******************

N AC

L

XXHData Block

H H H

H H H

N AC NCR

******************* StopCommandDataIn

CS

DataOut

H HHLLL

X HH

ZZ HHHNCR

NCS

L

H HHH XXHH

*******************LNEC

H HBusy H H

L LL

H

Z********H

6 Bytes Command

H Card Response

DataIn

CS

DataOut

LHHHLLLL

HH H H

L

HH H H HH H H HX XXH

H H H Z Z ZBusy

NEC NDS

L HHHHL

H HH

HH HHHNCR

L

H HHH XXXH

*******************L

H H HH

L L

H

Z1 or 2 Bytes Response

*************

H

DataIn

CS

DataOut

HH H H

H H H

L

H 6 Bytes Command

ZH*******************



The Stop Transmission command may be sent asynchronously to the data transmitted out of the card and may overlap the data block. In this case the card will stop sending the data and transmit the response token as well. The delay between command and response is standard NCR clocks. The first byte, however, is not guaranteed to be all set to ‘1.’ The card is allowed up to two clocks to stop data transmission.

The timing for de-asserting the CS signal after the last card response is identical to a standard command/response transaction. Reading the CSD Register

The following timing diagram describes the SEND_CSD command bus transaction. The timeout values between the response and the data block are NCX because the NAC remains unknown.

Figure 5-26 Read CSD Register Timing

5.23.3 Data Write

This section provides valuable information on the Data Write function.

Single Block Write

The host may de-select a card by raising the CS at any time during the card busy period. (Refer to the given timing diagram.) The card will release the DataOut line one clock after the CS going high. To check if the card is still busy, it needs to be re-selected by asserting the CS signal (set to low). The card will resume the busy signal (pulling DataOut low) one clock cycle after the falling edge of CS.

Figure 5-27 Single Block Write Timing

Multiple Block Write

The timing of the multiple block write transaction starting from the command up to the first data block is identical to the single block write. The figure below describes the timing between the data blocks of a multiple block write transaction. Timing of the ‘Stop Tran’ token is identical to a standard data block. After the card receives the Stop Transmission token, the data on the DataOut line is undefined for one byte (NBR), after which a Busy token may appear. The host may de-select and re-select the card during every busy period between the data blocks. Timing for toggling the CS signal is identical to the Single block write transaction.

H LL HHHHL

X HH

ZZ

XXXH HH

HHH HH H Z******** Card Resp

*******************

Z

N CS

N CXNCR

L L L

HH H H H H H H H X

H H H H H H H H H H Z

NEC

*******************Read Command

Data Block

DataIn

CS

DataOut

DataIn

CS

DataOut

H L HL L HLLLLL LLLLH

X H HHHHHHHHHHHH

ZZ HHHH HHHH L ZZ******** DataResp

Write Command Data Block

Busy

NWR

NCR

N CS

L

H HH

H

ZBusyHHHCard Resp

HH H H HH XXX HHHH

*******************

NEC NDS



Figure 5-28 Multiple Block Write Timing

5.24 Timing Values Table 5-11 shows the timing values and definitions.

Table 5-11 Timing Constants Definitions

Value Min. Max. Unit

NCS 0 --- 8 Clock cyclesNCR 0 8 8 Clock cyclesNRC 1 --- 8 Clock cycles

NAC 1 [10*((TAAC*f)+(100*NSAC))]*1/8* 8 Clock cyclesNWR 1 --- 8 Clock cycles

NEC 0 --- 8 Clock cyclesNDS 0 --- 8 Clock cycles

NBR 0 1 8 Clock cycles

*Where f is the clock frequency.

5.25 SPI Electrical Interface The SPI Electrical Interface is identical to MultiMediaCard mode with the exception of the programmable card output-drivers option, which is not supported in SPI mode.

5.26 SPI Bus Operating Conditions SPI Bus operating conditions are identical to MultiMediaCard mode.

5.27 SPI Bus Timing SPI Bus timing is identical to MultiMediaCard mode. The timing of the CS signal is the same as any other card input.

L L L L L L LL LL LLLLLL LLLLL

H HHHH HHHHHHHHHHHHHHHH

HH

HHHHH

HHHHHHHHHH X

Data Block

HHHHHH X X

Data Block

Data Resp Data Resp BusyBusy

*******************

Stop Tran

Busy

NWR

NBR

N CS

DataIn

CS

DataOut

Appendix A –Ordering Information Revision 1.0 MultiMediaCard/RS-MultiMediaCard Product Manual

© 2004 SanDisk Corporation A-1 05/13/04

Appendix A Ordering Information

A.1 MultiMediaCard and RS-MultiMediaCard To order SanDisk products directly from SanDisk, call (408) 542-0595.

Part Number Form Factor Capacity




SDMJ-256* Full-size MultiMediaCard 256 MB




SDMRJ-256* Reduced-size MultiMediaCard 256 MB


Appendix B –SanDisk Worldwide Sales Offices Revision 1.0 MultiMediaCard/RS-MultiMediaCard Product Manual

© 2004 SanDisk Corporation B-1 05/13/04

Appendix B SanDisk Worldwide Sales Offices

To order SanDisk products directly from SanDisk, call (408) 542-0595.

SanDisk Corporate Headquarters 140 Caspian Court Sunnyvale, CA 94089 Tel: 408-542-0500 Fax: 408-542-0503 http://www.sandisk.com U.S. Industrial/OEM Sales Offices

Northwest, Southwest USA & Mexico140 Caspian Court Sunnyvale, CA 94089 Tel: 408-542-0730 Fax: 408-542-0410

North Central USA & South America 134 Cherry Creek Circle, Suite 150 Winter Springs, FL 32708 Tel: 407-366-6490 Fax: 407-366-5945

Northeastern USA & Canada 620 Herndon Pkwy. Suite 200 Herndon, VA 22070 Tel: 703-481-9828 Fax: 703-437-9215

International Industrial/OEM Sales Offices

Europe SanDisk GmbH Karlsruher Str. 2C D-30519 Hannover, Germany Tel: 49-511-875-9131 Fax: 49-511-875-9187

Northern Europe Videroegatan 3 B S-16440 Kista, Sweden Tel: 46-08-75084-63 Fax: 46-08-75084-26

Central & Southern Europe Rudolf-Diesel-Str. 3 40822 Mettmann, Germany Tel: 49-210-495-3433 Fax: 49-210-495-3434

Japan 8F Nisso Bldg. 15 2-17-19 Shin-Yokohama, Kohoku-ku Yokohama 222-0033, Japan Tel: 81-45-474-0181 Fax: 81-45-474-0371

Asia/Pacific Rim Suite 3402, Tower I, Lippo Centre 89 Queensway Admiralty, Hong Kong Tel: 852-2712-0501 Fax: 852-2712-9385

Appendix C –Limited Warranty Revision 1.0 MultiMediaCard/RS-MultiMediaCard Product Manual

© 2004 SanDisk Corporation C-1 05/13/04

Appendix C Limited Warranty I. WARRANTY STATEMENT

SanDisk warrants its products to be free of any defects in materials or workmanship that would prevent them from functioning properly for one year from the date of purchase. This express warranty is extended by SanDisk Corporation. II. GENERAL PROVISIONS

This warranty sets forth the full extent of SanDisk’s responsibilities regarding the SanDisk MultiMediaCard. In satisfaction of its obligations hereunder, SanDisk, at its sole option, will repair, replace or refund the purchase price of the product. NOTWITHSTANDING ANYTHING ELSE IN THIS LIMITED WARRANTY OR OTHERWISE, THE EXPRESS WARRANTIES AND OBLIGATIONS OF SELLER AS SET FORTH IN THIS LIMITED WARRANTY, ARE IN LIEU OF, AND BUYER EXPRESSLY WAIVES ALL OTHER OBLIGATIONS, GUARANTIES AND WARRANTIES OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR INFRINGEMENT, TOGETHER WITH ANY LIABILITY OF SELLER UNDER ANY CONTRACT, NEGLIGENCE, STRICT LIABILITY OR OTHER LEGAL OR EQUITABLE THEORY FOR LOSS OF USE, REVENUE, OR PROFIT OR OTHER INCIDENTAL OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION PHYSICAL INJURY OR DEATH, PROPERTY DAMAGE, LOST DATA, OR COSTS OF PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES. IN NO EVENT SHALL THE SELLER BE LIABLE FOR DAMAGES IN EXCESS OF THE PURCHASE PRICE OF THE PRODUCT, ARISING OUT OF THE USE OR INABILITY TO USE SUCH PRODUCT, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW.

SanDisk’s products are not warranted to operate without failure. Accordingly, in any use of products in life support systems or other applications where failure could cause injury or loss of life, the products should only be incorporated in systems designed with appropriate redundancy, fault tolerant or back-up features. III. WHAT THIS WARRANTY COVERS

For products found to be defective within one year of purchase, SanDisk will have the option of repairing or replacing the defective product, if the following conditions are met:

A. A warranty registration card for each defective product was submitted and is on file at SanDisk. If not, a warranty registration card must accompany each returned defective product. This card is included in each product’s original retail package.

B. The defective product is returned to SanDisk for failure analysis as soon as possible after the failure occurs.

C. An incident card filled out by the user, explaining the conditions of usage and the nature of the failure, accompanies each returned defective product.

D. No evidence is found of abuse or operation of products not in accordance with the published specifications, or of exceeding storage or maximum ratings or operating conditions.

All failing products returned to SanDisk under the provisions of this limited warranty shall be tested to the product’s functional and performance specifications. Upon confirmation of failure, each product will be analyzed, by whatever means necessary, to determine the root cause of failure. If the

Appendix C –Limited Warranty Revision 1.0 MultiMediaCard/RS-MultiMediaCard Product Manual

© 2004 SanDisk Corporation C-2 05/13/04

root cause of failure is found to be not covered by the above provisions, then the product will be returned to the customer with a report indicating why the failure was not covered under the warranty.

This warranty does not cover defects, malfunctions, performance failures or damages to the unit resulting from use in other than its normal and customary manner, misuse, accident or neglect; or improper alterations or repairs.

SanDisk reserves the right to repair or replace, at its discretion, any product returned by its customers, even if such product is not covered under warranty, but is under no obligation to do so.

SanDisk may, at its discretion, ship repaired or rebuilt products identified in the same way as new products, provided such cards meet or exceed the same published specifications as new products. Concurrently, SanDisk also reserves the right to market any products, whether new, repaired, or rebuilt, under different specifications and product designations if such products do not meet the original product’s specifications.

IV. RECEIVING WARRANTY SERVICE According to SanDisk’s warranty procedure, defective product should be returned only with prior authorization from SanDisk Corporation. Please contact SanDisk’s Customer Service department at 408-542-0595 with the following information: product model number and description, serial numbers, nature of defect, conditions of use, proof of purchase and purchase date. If approved, SanDisk will issue a Return Material Authorization or Product Repair Authorization number. Ship the defective product to:

SanDisk Corporation Attn: RMA Returns (Reference RMA or PRA #) 140 Caspian Court Sunnyvale, CA 94089

V. STATE LAW RIGHTS

SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES, OR LIMITATION ON HOW LONG AN IMPLIED WARRANTY LASTS, SO THE ABOVE LIMITATIONS OR EXCLUSIONS MAY NOT APPLY TO YOU. This warranty gives you specific rights and you may also have other rights that vary from state to state.

Appendix D –Disclaimer of Liability Revision 1.0 MultiMediaCard/RS-MultiMediaCard Product Manual

© 2004 SanDisk Corporation D-1 05/13/04

Appendix D Disclaimer of Liability

D.1 SanDisk Corporation Policy SanDisk Corporation general policy does not recommend the use of its products in life support applications wherein a failure or malfunction of the product may directly threaten life or injury. Accordingly, in any use of products in life support systems or other applications where failure could cause damage, injury or loss of life, the products should only be incorporated in systems designed with appropriate redundancy, fault tolerant or back-up features. SanDisk shall not be liable for any loss, injury or damage caused by use of the Products in any of the following applications:

− Special applications such as military related equipment, nuclear reactor control, and aerospace

− Control devices for automotive vehicles, train, ship and traffic equipment

− Safety system for disaster prevention and crime prevention

− Medical-related equipment including medical measurement device

Engineer-to-Engineer Note EE-264

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Technical notes on using Analog Devices DSPs, processors and development toolsContact our technical support at [email protected] and at [email protected] visit our on-line resources http://www.analog.com/ee-notes and http://www.analog.com/processors

Interfacing MultiMediaCard™ with ADSP-2126x SHARC® Processors Contributed by Aseem Vasudev Prabhugaonkar and Jagadeesh Rayala Rev 1 – March 11, 2005

Copyright 2005, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices’ Engineer-to-Engineer Notes.

Introduction This application note describes how to implement the interface between an ADSP-2126x SHARC® processor and a MultiMediaCard™ (MMC). The application note also describes the MMC command format and demonstrates with example code how an MMC card can be interfaced seamlessly with the SHARC processor’s SPI port. Example code supplied with this application note implements the most commonly used commands of MultiMediaCard.

About MultiMediaCard The MMC was introduced in 1998 and had an amazing reduction in cubic capacity compared with CompactFlash™. MMC cards are now widely used in digital cameras, smart cell phones, PDAs, and portable MP3 players. Their intended use is to store information and content.

The MMC consists of a 7-pin interface and supports two serial data transfer protocols viz. the MMC (MultiMediaCard) mode and SPI (Serial Peripheral Interface) mode. The maximum operating clock frequency used for serial communication in both modes can go up to 20 MHz. The data written in any of these modes can be read by host in either mode. The advantage of MMC supporting SPI mode is that MMC can be interfaced seamlessly to many controllers or DSP processors, which have on-chip support for SPI. Most MMCs have a communication voltage from 2.0 to 3.6 V, a

memory access voltage of 2.7 to 3.6 V, and a capacity from 4 MB to the gigabyte range.

About the ADSP-2126x SPI Port The ADSP-2126x processor is equipped with a synchronous serial peripheral interface port that is compatible with the industry-standard Serial Peripheral Interface (SPI). The SPI port supports communication with a variety of peripheral devices including codecs, data converters, sample rate converters, S/PDIF or AES/EBU digital audio transmitters and receivers, LCDs, shift registers, micro-controllers, and FPGA devices with SPI emulation capabilities.

Important features of ADSP-2126x SPI port include:

Simple four-wire interface, consisting of two data pins, a device select pin, and a clock pin

Full duplex operation, allowing simultaneous data transmission and reception on the same SPI port

Data formats to accommodate little and big endian data, different word lengths, and packing modes

Master and slave modes as well as multimaster mode in which the ADSP-2126x processor can be connected to up to four other SPI devices

Open drain outputs to avoid data contention and to support multimaster scenarios

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Interfacing MultiMediaCard™ with ADSP-2126x SHARC® Processors (EE-264) Page 2 of 6

Programmable bit rates, clock polarities, and phases

DMA capability, allowing transfer of data without core overhead

Master or slave booting from a master SPI device

The MultiMediaCard Interface In SPI mode, four signals (clock, data in, data out and chip select) are used for the interface. The clock is used to drive data out on the data out pin and receive data on the data in pin. The host drives commands and data to the MMC over the MMC’s data in pin. The host receives response and data from the MMC on its data out pin. The chip select signal is used to enable the MMC during data and command transfer. The chip select signal is also used initially to drive the MMC in SPI mode. Note that in SPI mode, data is transferred in units of eight clock cycles.

Pin Name Type Function

1 CS# Input Chip select (active low)

2 Din Input Data input

3 VSS1 Power GND

4 VDD Power VCC

5 CLK Input Clock input

6 VSS2 Power GND

7 Dout Output Data output

Table 1. MultiMediaCard Pin Assignment

Figure 1. MultiMediaCard Pin Assignments

The MMC pin assignments in SPI mode are shown in Table 1 and Figure 1. Figure 2 shows the MMC interface with the ADSP-2126x SPI port.

Figure 2. MultiMediaCard Interface with SPI Port

The MultiMediaCard Protocol The SHARC processor's SPI issues commands to the MMC over the data in (Din) pin of the MMC. The data in pin of the MMC is connected to MOSI of the SPI. The data is also written to the MMC over the data in signal of the MMC. Based on the received command, the MMC sends response or data on the data out (Dout) pin. The data out pin of the MMC is connected to MISO of the SHARC processor's SPI port. The processor's SPI port uses one of the Programmable Flag pins (FLAGx) to drive CS# of the MMC. The communication is initiated by different commands sent from the SHARC processor to the MMC. All commands are six bytes long and are transmitted MSB first. Refer to Figure 3 for generic transfer protocol between the MMC and the SHARC processor's SPI port.

Figure 3. MultiMediaCard Transfer Protocol

Din Dout CLK

ADSP-2126x SPI

MOSI

MISO

SPICLK

FLAGx

VCC

GND

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Commands and Responses

Table 2 lists the MultiMediaCard's most commonly used commands in SPI mode. The command format is shown in Figure 6.

Each MMC command consists of 48 bits (6 bytes) comprising a start bit (always 0), a transfer bit (always 1), a 6-bit command field, a 4-byte (32-bit) argument field, a 7-bit CRC field, and an end bit (always 1). The argument field contains the necessary information (card relative address, read address, write address, etc.) for issuing that command. For every received command (except the SEND_STATUS command), the MMC responds with a token value.

The R1 response token is 1-byte long and its MSB is always 0. The other bits in the response indicate error conditions. The structure of an R1 response is shown in Figure 4. The R1 format byte description is given in Table 3.

Figure 4. The MultiMediaCard R1 Response Format

Response format R2 is 2 bytes long. The response token is sent by the card as a response to the SEND_STATUS command. The format of the R2 status is shown in Figure 5.

Figure 5. The MultiMediaCard R2 Response Format

The R2 format description is given in Table 4.

Table 2. Most Commonly Used MultiMediaCard Commands

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Figure 6. The MultiMediaCard Command Format

Table 3. MultiMediaCard R1 Response Format Description

Table 4. MultiMediaCard R2 Response Format Description

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The Algorithm By default, the MMC starts in MMC mode after power up. To configure the card for SPI mode, the CS# is driven logic low while transmitting the CMD0 command. The following procedure is required to set up data transfer in SPI mode.

1. After power up, drive CS# inactive (logic high). This disables the card .

2. Issue at least 80 dummy clock cycles for MMC initialization.

3. Drive CS# low and transmit a CMD0 command. At this point, card mode changes from default MMC mode to SPI mode.

4. Wait for an R1 response from the MMC. The R1 response from the MMC should be 0x01. Any other value indicates an error condition. Re-execution starting from powering on may be required.

5. Issue a CMD1 command and wait for an R1 response. The R1 response should be 0x00. Any other response value indicates of error condition.

6. After a correct R1 response for CMD1, data transfer can occur. Note that until the CMD1 command is successful, the SPI baud rate (clock frequency) should be less than 400 kHz. Before data transfer can begin, the SPI baud rate can be increased.

7. Commands such as set block length can now be issued.

8. Issue commands to read/write the MMC card.

9. When powering off, check that the card is in the Ready state and drive CS# high (inactive) before turning off the power supplies.

The commands implemented in the supplied code are:

MMC initialization

CMD0 (GO_IDLE_STATE)

CMD1 (SEND_OP_COND)

CMD16 (SET_BLOCKLEN)

CMD24 (WRITE_BLOCK)

CMD59 (CRC_ON_OFF)

CMD17 (READ_SINGLE_BLOCK)

The following are screen captures for some of the MMC commands:

Figure 7. Initialization with 80 CLK Cycles, CMD0 Command and R1 Response – 0x01

Figure 8. CMD1 Command and R1 Response - 0x00

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Figure 9. Write Data Completed – 0x00 (BUSY) Followed by 0xFF(High) Indicating Write Complete

Figure 10. Data Being Read After Receiving Read Token 0xFE from the MMC

The example code is supplied in the file EE264v01.zip associated with this EE-Note. For further information on commands, responses, and code flow, refer to the readme.txt file included in the ZIP file.

References [1] ADSP-2126x SHARC DSP Peripherals Manual. Rev 2.0, January 2004. Analog Devices, Inc.

[2] ADSP-21262 DSP EZ-KIT Lite Evaluation System Manual. Rev 1.2, March 2004, Analog Devices, Inc.

[3] Interfacing a MultiMediaCard to the LH79520 System-On-Chip. SHARP Application Note.

[4] MultiMediaCard User’s Manual, ADE-603-002B. Rev.3.0, 3/20/2003 Hitachi, Ltd.

Document History

Revision Description

Rev 1 – March 11, 2005 by Aseem Vasudev Prabhugaonkar and Jagadeesh Rayala

Initial Release

Documents

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