FPGA Creating Counter

Created by

Akhmad Hendriawanhendri@eepis-its.edu

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Created by

Akhmad Hendriawanhendri@eepis-its.edu

Design system

Background

I try implement counter seven segmen with input clock from switch.

Because push button is mechanical then I try to remove bouncing effect with debouncing circuit

Problem and solution

Although I succeed to implement my design and upload to bit stream to FPGA but there was warning with warning message prescaller may have excessive skew.

My first prescaller with warning

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;

Library UNISIM;use UNISIM.vcomponents.all;

entity Prescaller is Port ( clk_i : in STD_LOGIC; psc_out : out STD_LOGIC);end Prescaller;

architecture Behavioral of Prescaller issignal clk_r: std_logic_vector(17 downto 0) := (others=>'0');begin

process (clk_i,clk_r)begin if rising_edge(clk_i) then clk_r clk_r(17) -- Clock buffer input );

end Behavioral;

Prescaller.vhd

Implement clock buffer to output prescaler solve warning error.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity debouncing is Port ( clk_i : in STD_LOGIC; dbin : in STD_LOGIC; dbout : out STD_LOGIC);end debouncing;

architecture Behavioral of debouncing issignal Q1, Q2, Q3 : std_logic;beginA: process(clk_i)begin if (clk_i'event and clk_i = '1') then Q1 segment7 segment7 segment7 segment7 segment7 segment7 segment7 segment7 segment7 segment7 segment7 clk_i,psc_out => psc_cable);Inst_debouncing: debouncing PORT MAP(clk_i => psc_cable,dbin => pb_i,dbout => db_cable);Inst_counterBCD: counterBCD PORT MAP(clk_i => db_cable ,bcd_o => bcd_o_cable);Inst_decoder: decoder PORT MAP(clk => db_cable,bcd => bcd_o_cable,segment7 => counter_out);end Behavioral;

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity syscnt is Port ( clk_i : in STD_LOGIC; pb_i : in STD_LOGIC; counter_out : out STD_LOGIC_VECTOR (6 downto 0) );end syscnt;

architecture Behavioral of syscnt is

COMPONENT PrescallerPORT(clk_i : IN std_logic; psc_out : OUT std_logic);END COMPONENT;COMPONENT debouncingPORT(clk_i : IN std_logic;dbin : IN std_logic; dbout : OUT std_logic);END COMPONENT;COMPONENT counterBCDPORT(clk_i : IN std_logic; bcd_o : OUT std_logic_vector(3 downto 0));END COMPONENT;

Syscnt.vhd