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Tutorial on
FPGA Design Flow
based on
Xilinx ISE Webpack
and ModelSim
ver. 1.8
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Prepared by Marcin Rogawski, Ekawat (Ice) Homsirikamol, Kishore Kumar Surapathi, Jeremy Kelly, Malik Umar sharifand Dr. Kris Gaj
The example codes used in this tutorial can be obtained from http://ece.gmu.edu/coursewebpages/ECE/ECE448/S11/labs/448_lab3.htm The current version of the tutorial was tested using the following tools: Toolset At School: Synthesis Tool
− Xilinx ISE/WebPack Version : 14.2
Implementation Tool − Xilinx ISE/WebPack Version : 14.2 Simulation Tool − ModelSim SE Version : 10.0b
At Home: Synthesis Tool
− Xilinx ISE/WebPack Version : 14.2 Implementation Tool
− Xilinx ISE/WebPack Version : 14.2 Simulation Tool
• ModelSim SE ver. 6.6 or below to support Timing simulation. Note:Free version of the software (ModelSim Student PE Edition 10.0c) available on the website does not allow you to perform timing simulation.
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Table of Contents 1. Project Settings 4 2. Behavioral Simulation 12 3. Synthesis and Implementation 15 3.1 Synthesis with Xilinx XST 12 3.2 Synthesis with Synplify Premier DP 19 3.3 Translate 24 3.4 Post-Translate Simulation 24 3.5 Map 25 3.6 Place and Route 26 3.7 Post Place and Route Simulation 27 3.8 Implementation Reports 28 4. Specifying Frequency/ Time period using User Constraints 30 5. Optimization strategies 32 6. Pin Assignment 35 7. Bit Stream Generation 39 8. Uploading Bitstream to FPGA Board 40
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1. Project Settings To Start Xilinx ISE in the ECE Labs go to: Start->All Programs-> VLSI Tools->Xilinx ISE <version number>->ISE Design Tools ->Project Navigator At home, adjust the path accordingly based on your installation.
To start new Project go to: menu File->New Project
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Specify Project Name and location for project files
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Click Next and specify
Family : Xilinx13x Spartan3E Device : XC3S100E Package : cp132 Speed Grade : -5
Simulator : ModelSim SE VHDL
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Click Finish and then Add Source. Choose files for the project.
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Then click Ok. Your project has been defined.
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2. Behavioral simulation In the Design Menu we choose BehavioralSimulation. The testbench for this design was set as a top level. In the Processes menu choose ModelSim Simulator, Simulate Behavioral Model, right-click and choose Run.
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You will see a picture similar to the one above.
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Finally, you should be able to observe waveforms for your design.
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3. Synthesis and Implementation 3.1 Synthesis with Xilinx XST Go to the menu Sources for and change this option to Synthesis/Implementation. Click Check Syntax to check if vhdl sources are properly coded.
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When you right-click on Generate Post-Synthesis SimulationModel then pop-up menu appears. ChooseRun to start synthesis (There is no option to simulate post-synthesis netlist for Xilinx ISE WebPack). But you can see the post synthesis vhdl file in folder <project name>-�<netgen>�<synthesis>
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When Synthesis process is completed, the report from synthesis becomes available. Some of the most important features of the design are the minimum clock period and the maximum clock frequency. We can find these two parameters in the report file from Synthesis. Please remember that the values of these parameters after synthesis are different than the values of the same parameters after implementation.
The other important information we can find in this report is the amount of FPGA resources your design requires.
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Generating the libraries for Xilinx ISE <version number>: Before doing post-synthesis, post-translate, post map and post place & route simulation, it is important to compile the libraries (Unisim and Simprim). Click on the radioi button beside simulation to change the view from implementation to simulation in design menu. Now click on the device (in our case: xc3s100e-5cp132). It will automatically show Compile HDL Simulation Libraries in the processes menu. Double to start the the process. It will take 20-25 minutes to compile the libraries and place them in a folder under Xilinx ISE installation.
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Synthesis and generation of Post-Synthesis Simulation Model were completed successfully and we can start Implementation part.
3.2 Synthesis with Synplify Premier DP Go to edit menu and click on Preferences. Once a new Preferences window pops up, select Integrated Tools under Category and ISE General option. Set the path for Synplify Premier DP under the synthesis tool "Synplify". Click Apply to save the settings and then click OK.
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Go to Project menu and click on Design Properties. A new window pops up for Design properties. Go to synthesis tool and click on drop down menu to select Synplify (VHDL). Click OK to save the settings.
Now you can observe that the synthesis tool changes automatically in the processes menu.
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Double click on the Synthesize - Synplify to run synthesis using Synplify Premier DP. You can also view RTL and technology view of the schematic. Once you double click on View RTL Schematic, it will automatically invoke the tool "Synplify Premier DP ".
Finding the Critical path of the design: Click on Run to start the synthesis inside Synplify Premier DP. Click to
Technology view icon , followed by Show Critical path button to see the critical path of your design
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Go to View menu and click on View Log File. It will open a window and will show you following options:
Click to Technology
view icon , followed by Show Critical path button
to see the critical path of your design
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Select compiler report and go down to see the performance summary for the maximum frequency and minimum clock period of the design, estimated after synthesis.
Now click on Resource Utilization to see the summary of device utilization in terms of different resources utilized by your design.
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Implementation :
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3.3 Translate The first step in the Xilinx Design Flow for implementation is Translate. Under Implement Design option, choose Translate, and then Run. If you are successful with this part you should generate Post Translate Simulation Model. 3.4 Post-Translate Simulation When you right-click on Generate Post-Translate SimulationModel then pop-up menu appears. Choose Run to start. In the menu Sources for we choose Post-Translate Simulation. The testbench for this design was set as a top level. In the menu Processes for choose ModelSim Simulator, right-click and choose Run.
ModelSim SE will be launched and waveforms for our design should appear. We can save script for further re-simulation by saving .do type files.
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There is in the bottom part ModelSim terminal. We can type there commands such like do name_of_script.do and our waveform will be updated. It is possible to use terminal in every step of implementation. 3.5 Map Go to the menu Sources for and change this option to Synthesis/Implementation. From the Implement Design menu choose Map. Do right-click and pop-up menu should appear. Choose Run to start mapping process. Post-Map Simulation When you right-click on Generate Post-Map SimulationModel then pop-up menu appears. Choose Run to start. In the menu Sources for we choose Post-Map Simulation. The testbench for this design was set as a top level. In the menu Processes for choose ModelSim Simulator, right-click and choose Run.
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3.6 Place and Route Go to menu Sources for and change this option to Synthesis/Implementation. From the Implement
Design menu choose Place and Route. Do right-click and pop-up menu should appear. Choose Run to start place and route process. When we right-click on Generate Post Place and Route Simulation Model then pop-up menu appears and you should choose Run.
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3.7 Post Place and Route (Timing) Simulation In the menu Sources for we choose Post-Route Simulation. The testbench for this design was set as a top level. In the menu Processes for choose ModelSim Simulator, right-click and choose Run.
ModelSim SE will be launched and waveforms for our design should appear.
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5.7 Implementation Reports Review the Implementation Reports shown in the following pages.
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4. Specifying Frequency/ Time period using User Constraints: Go to menu Sources for and change this option to Synthesis/Implementation.
4.1 Requesting Synthesis clock frequency: In order to apply timing constraints on the design during the synthesis phase, we specify constraints in .xcf file. Create a new file in any text editor and save it with the extension (.xcf) with the clock period settings as per the design requirement.
e.g., NET "clk" PERIOD = 3.82 ns;
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4.2 Requesting Implementation clock frequency: In order to apply timing constraints on the design during the implementation phase, we specify constraints in .ucf file. Create a new file in any text editor and save it with the extension (.ucf) with the clock period settings as per the design requirement.
e.g., NET "clk" PERIOD = 3.82 ns;
Go to Project and click on Add source. Browse and select the .ucf file by giving path to the specific ucf file. Click OK to add the ucf file to the project.
provide the path for synthesis constraint file (.xcf) to include it for synthesis constraints.
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4.3 Obtaining textual representation of critical path using Timing analyzer (after place & route): Go to Tools menu and then click on Timing Analyzer and select Post Place and Route option. It will automatically include one more tab Timing in the menu. Click on Timing menu and then select Run Analysis.
4.3.1 Choosing between default (auto-generated) or user-defined constraints: The second setting in the Run Timing Analysis is Analyze again where you can specify through a drop down menu whether you want to specify any constraint on the design or you want to use default (auto- generated) constraint of the tool.
As we have already specified the timing constraint in the ucf file for the sample design here, tool will show the constraints that are applied in the ucf file (lab_demo_ucf.ucf). Click OK to see the text report about the timing result after place route. If you have already specified the timing information in the ucf file, choose the default (auto-generated) timing constraints from the tool.
selection between auto-generated and user-defined timing constraints
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Scroll down till the end of the file (Analysis 1.twx) to see the timing summary that includes minimum period and maximum frequerncy of the design after place and route.
As we did not change the Report options, the tool will automatically show the timing information of the paths that have the biggest slack (worst critical path). Search for minimum period in the .twx file from all three paths
and choose the one that matches the maximum period shown in the timing summary. It will also have the corresponding critical path information of your design after place and route along with it in the text format.
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5. Optimization strategies: Right click on the synthesis and implemention options in processes menu and then choose process properties to select a complete list of optimization strategies.
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6. Print the output waveform in PDF format: In order to view all the important details of the behavioral, post-synthesis, post-translate, post-map and post-place & route simulations in waveform in PDF format, use 3rd part tools (PDF creator, PDF Lite etc). Go to file menu and click on the print menu. A pop up will appear that will give you the option to select time range (full range or for a specific range). Click OK and chose PDF Lite or any other tool to do PDF conversion. After completing the print setup, a new window pops up and ask you to save the file in PDF format.
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Here is the output waveform of post-translate simulation in PDF format.
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Note: Remaining two sections apply only to users that target specific FPGA boards (e.g., ECE-448 students)
6. Pin Assignment: Go to menu Sources for and change this option to Synthesis/Implementation. Click on Assign Package Pins. The User Constraint File (UCF) will be created if you decide to assign design port names to the physical pins. Columns I/O Names and I/O Descriptions represent ports from your design. The Loc column should be used to input the location of the corresponding pin in the FPGA device.
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We can specify Pin Assignments by going to User Constraint menu. We can assign design port names to the physical pins of a chosen device by option Edit Constraints (Text). Keyword NET is for a port name assignment and keyword LOC is for a physical pin assignment.
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5.8 Bit Stream Generation
Go to menu Sources for and change this option to Synthesis/Implementation. Choose Generate Programming File, do right-click and pop-up menu should appear. Choose Run to start bit generation process.
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6. Uploading Bitstream to FPGA Board
Before uploading Bit file, make sure that you change your constant values in all your files to proper values, and re-synthesize/re-implement all the files. In particular, in our example, please change the value of the constant slow_clock_period in the Lab3Demo_package.vhd. Select the Adept program as shown in the picture above. When the program is opened, a device will be shown if it is connected and recognized. Select the bit file by clicking Browse and finding the appropriate file. Click Program to program the file device.
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