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Ottmar Ried, Christian Boleat, Alexandra Parasidi, Yanitsa Stoyanova
Airbus Defence and Space
FPGA experience and SoC design methodology SEFUW, ESTEC 2018
Contents
FPGA Experience at Airbus Defence and Space
BRAVE-Medium evaluation
SoC Design methodology
Mentor Vista evaluation
FPGA Experience at Airbus Defence and Space
Antifuse FPGAs
RTSX32/72 RTAX2000/4000 RTAX2000D/4000D
Complexity Small Medium Medium
Special features 5V compatible RAM RAM+MATH
Applications Control Complex Control
Data handling
Signal processing
Product examples Power, Motor Mass memory, ICU, OBC,
Power, Motor
Instrument
Prototyping Commercial device Progr. Adapter
Commercial device (AX)
Progr. Adapter
PROTO device
Export restriction Yes Yes Yes
Comment Almost 20 years on the
market
High runner with well
established development
flow.
Special devices which
are only used if no other
solution reasonable.
SEFUW 2018 4
Reprogrammable FPGAs
(RT-)PA3 RTG4 Spartan-6 Virtex XQR5VFWX130
BRAVE-Medium BRAVE-Large
Technology FLASH FLASH SRAM SRAM SRAM SRAM
Complexity Medium Large Large Large Medium Large
Hardened SW-TMR Technology SW-TMR Technology Technology Technology
Special features RAM RAM+MATH+
PLL+HSSL
RAM+MATH+
PLL+HSSL
RAM+MATH+
PLL+HSSL
RAM+MATH+
PLL
RAM+MATH+
PLL+HSSL
Applications Control SoC, High perf.
data handling
GNSS,
Compression
Compression evaluation evaluation
Products
examples
Motor Mass memory Communication,
Navigation
evaluation evaluation
Prototyping Commercial
device
Proto-Device COTS Commercial
device
Export restriction RT only Yes No yes No No
Comment AIRBUS COTS SW+HW
Evaluation
ongoing
SEFUW 2018 5
BRAVE-Medium 1/2
AGGA4 ASIC ported to BRAVE NG-MEDIUM:
• Design split in 2 parts, since too big for 1 FPGA
• LEON2 + AMBA bus + peripherals is Part1
• GNSS receiver is Part2
• Multiple iterations of synthesis, place and route
with various NanoXmap settings to achieve
best results
• Functional verification through simulations with
the netlist generated after synthesis, placement
and routing.
• Physical tests on Part1 with the development
kit board: Demo SW program ran on LEON2
SEFUW 2018 6
BRAVE-Medium 2/2
Digital Signal Processing algorithm (Radix-2) synthesized, placed and routed.
• Resource utilization and maximal frequency results comparable to RTG-4
Technology demonstrated to work by porting LEON2FT
and executing correctly simple application.
SW tools are brand new
• Main challenges on synthesis stage
• SW tools are constantly improved.
• Better performance with each version.
SEFUW 2018 7
FPGA Trends
More complex FPGA’s and designs
Higher integration of boards
More COTS devices used
HSSL will dominate the communication
SW and HW will come together in SoC
SEFUW 2018 8
PCM
A
MSS
A
OBC
Power
Control
Bus A
Sec.
Power A
PCM
B
MSS
B
OBC
Sec.
Power B
Power
Control
Bus B
External SpW
Control Links
Prim.
Power A
Prim.
Power B
Internal SpW
Control Links
Internal SpW
Control Links
External SpW
Control Links
Link_1_8
Link_1_4
Link_1_3
Link_1_2
Link_1_1
Link_1_7
Link_1_6
Link_1_5
Link_2_1
Link_2_2
Link_2_3
Link_2_4
Link_2_5
Link_2_6
Link_2_7
Link_2_8
IOM
2
COM
2
FMM
3
FMM
5
FMM
4
FMM
1
FMM
2
IOM
1
COM
1
SoC Design Methodology
Development organisation
• Large design teams may be distributed in several companies
• Several HW and SW modules are designed separately by
different teams
• The use of IP are increased
• The use of high level languages to describe the FPGA behaviour
is necessary to perform the HW/SW partitioning
SEFUW 2018 10
requirements
Specifications
System architecture analysis
Hardware software partitioning
Hardware
Development &
test
Software
Development &
test
System integration & test
Hardware software
Integration & test
System architects Hardware team 1 Hardware team 2
Ver ification team Software team 1
Software team 2
Even if the methodology is the
same, the capacity and
performances of large FPGA
make that :
Design phase
The equipment specification is distributed in module specifications which are designed separately
A first place & route analysis is done at local level, second is done if necessary during the synthesis of all functions
Software is integrated at this level.
SEFUW 2018 11
Equipment
specification
module
specification HDL simulation
Place & route
optimization
Global optimization
Place & route Test board
module
specification
module
specification HDL
HDL
simulation
simulation
Place & route
optimization
Place & route
optimization
Mentor Vista evaluation 1/2 • Integration and system functionality
verification with the use of Vista and Questa.
• Evaluation in frame of DAHLIA project.
• Vista provides model library in SystemC
(CPU, Memories, Interconnects, etc.).
• Vista providing software stimulus to the RTL
DUT for peripheral accesses through
interconnect.
• System Verilog Testbench for Data transfer
from Vista model (SystemC) to RTL DUT
(conversion from generic payload to AXI
transactions).
SEFUW 2018 12
Mentor Vista evaluation 2/2 • Successful conversion of generic payload into AXI transactions.
• Successful peripheral AXI read and write accesses through the Interconnect.
• Replacement of RTL modules with Vista models reduces the simulation time allowing software test-
case execution (~60-80% of the design is modelled in Vista).
• Easy usage of the model libraries of Vista and easy model configuration.
• Easy AXI protocol violations monitoring.
• No cycle accurate simulation
results for the SystemC parts
• Future use for evaluation of
the overall performance of
SoC and debugging purposes.
SEFUW 2018 13
Conclusion
The complexity of FPGAs will further grow into the System on Chip area
The development flow must be adapted to distributed System on Chip design
Tools shall support efficiently the handling of this complexity
SEFUW 2018 14
Thank you
Copyright Airbus Defence and Space
