FPGA Implementation and Performance Evaluation of a Digital

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    By:-

    Garima Singh

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    The telecommunication system has a heightened

    impact on the digital integrated circuit design

    industry.

    There are many methods available for the

    implementation of digital communication

    systems:

    Field Programmable Gate Array(FPGA)

    Application Specific Integrated Circuit

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    Cooperative communication protocols in which two or more

    sources transmit simultaneously in a single subchannel offer

    the potential for increased power efficiency and achievable

    rate with respect to orthogonal transmit cooperation.

    These protocols are, however, complicated by the fact that

    they require strict transmitter synchronization in order for

    the carrier signals from each source to arrive in phase and

    constructively combine at the intended destination.

    Carrier Synchronization plays an important role in coherent

    communication systems, especially for those utilizing a high

    bandwidth efficiency modulation schemes such as Modem.

    The main method available for providing this synchronization

    is Phase Locked Loop(PLL).

    Traditionally a negative feedback loop is employed by the PLL

    in order to operate as a Carrier Synchronizer.

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    The basic components of a Digital Carrier Synchronizerare:

    Phase Detector

    Loop Filter

    Numerically Controlled Oscillator

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    The NCO is a digital signal generator which creates asynchronous(i.e. clocked), discrete time, discretevalued representation of a waveform usuallysinusoidal.

    The NCO has several advantanges in terms of

    Agility Accuracy

    Stability

    Reliability

    NCOs are used in many communication systems such

    as Digital Up/Down convertors used in 3G wireless andsoftware radio systems.

    Digital PLLs

    Multilevel FSK/PSK modulators/demodulators

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    1. LUT based NCO

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    2. CORDIC based NCO

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    3. Xilinx ROM based NCO

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    The design is generated by inputting the circuit intoXilinx ISE8.li which is done by using Verilog HDL.

    Simulations are important before configuring thechip.

    Certain User Constraints and Synthesis Results arestated below:

    User Constraints:

    Timing Constraint

    Package Pin Assignment

    Synthesis Result: Synthesis wise DCS using CORDIC based NCO occupies

    less area.

    Simulation proved that DCS configuration using XilinxROM based NCO provided a faster Locking Time andbetter Tracking Frequency Range.

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    Simulation Report of Different

    DCS

    Synthesis Report of Different

    DCS

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    In order to serve the purpose for rapid prototyping,emulation technique presents itself as a strong candidate.

    This emulation technique is not only involved in DCS butalso can be customized for any data synchronizationsystem.

    The functional sanctity of DCS core is validated. The same emulation environment can be used for analysing

    the performance of DCS configurations with differentNCOs.

    A DCS architecture is built up which exploits faster lockingand wider tracking range.

    The locking time of Xilinx ROM based NCO implementationis the best among the other techniques.

    Thus, a flexible DCS for FPGA based design solution whichcan accommodate various NCO configurations has beendeveloped.

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    THANK YOU