FPGA Logic Emulation and Reconfigurable Systems

8/11/2019 FPGA Logic Emulation and Reconfigurable Systems

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Par t III

LogicEmulation


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What is a LogicEmulation System?

1.A programmable hardwarebuilt withprogrammable logic (FPGA) andprogrammable interconnect devices (PID).

2.A software which automatically programs thehardware according to the circuit under design

3.Control HW/SW to support operation of theemulated designas a hardware componentoperating in real time.


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Target System

Typical Logic EmulationEnvironment

Workstation

Logic Emulator

Logic Module

Probe Module

In-circuitInterface

Compiler, runtimesoftware

Stimulus generator, logic analyzer


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Why we need Logic

Emulation?Design verificationissues.

Real-timeoperation.

System-level testing.

Rapid prototyping.


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Design Verification

IssuesSimulation-based verification methods have

run out of steamwhen chip complexity

grows.

Emulation is a verification technologythat

grows along with design size.


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Real-Time Operation

Simulationrequires test vector developmentwhich is costly and difficult.

Verification depends on test vector correctness.

Certain applications must be verified in real time -human perception: audioand video.

Emulation connected to actual hardwarecan run:real diagnostic code,

operating systems, and

applications.


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System-Level Testing

Often the chip meets its specificationsbut it failsin the system.

We have to verify the system-level interactionsbetween the chip and other components. Theyare hard to formalize.

Internal probing is impossiblewhen the chip isfabbed and placed in a system

But it is possibleusing emulation.


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Rapid Prototyping

Once emulated designis debuggedit isavailable for immediate use by software

developersfor software debugging.

Emulated design is available for demoand

experiments with architectureon realapplications and data.


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Programmable Hardware includes

programmable interconnect

Programmableinterconnect

Memoryelement

VLSIcore

InterfaceLogic

element

Logicelement


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Considerations for

programmable interconnect

The capacity of logic and interconnection depends onpackage constraints.

This forces a hierarchicalsystem.Chips => boards => boxes => system

The interconnect structuremust:1. Provide successful connectivity,

2. Maximize FPGA utilization, and3. Minimize delay and skew.

Rents ruleapplies to predict the interconnect needs.


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Structures of Multi-FPGA

Systems

Topologies:

- Mesh- nearest neighboring.

- Crossbar- full and partial.

Interconnect scheme:

- Circuit switched.

- Time multiplexed.


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Nearest Neighbor

Interconnection

FPGA FPGA FPGA

FPGA FPGA FPGA

FPGA FPGA FPGA


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Advantages and Disadvantages of

Nearest Neighbor Interconnection

Advantages:

Uniform: all chips the same.

Easy to lay out on PCB.

Disadvantages:

Routing is easily blocked.

The through pins limit the logic utilization of FPGAs.Long and unpredictable delays.

No natural hierarchical extension.


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Nearest Neighbor Extensions

FPGA FPGA FPGA

FPGA FPGA FPGA

FPGA FPGA FPGA

Add more

neighbors

Connect to

non-neighbors


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Advantages and Disadvantages of

nearest-neighbor extended architectures

Advantages:

More choices for router by adding diagonal

lines & skip lines.

Disadvantages:

More complex PCB.

More complex routing software.


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Partial Crossbar Interconnect

A B C D A B C D A B C D A B C D

A pins B pins C pins D pins

Logic blocks

Crossbars

Second-level crossbars


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Partial Crossbar Interconnect

Partial crossbar consists of a set of small fullcrossbars,

connected to logic blocks

but not to each other.

I/O pins of each FPGA are divided into subsets.Each subsetis connected by a full crossbar circuitswitch.

Partial crossbar is a potentially blockingnetwork.


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Characteristics of Partial

Crossbar Architecture

Partial crossbars size is proportional to thenumber of FPGA pins.

All interconnections go through one/threecrossbar chips for a one-level/two-level

partial crossbar interconnectdelays are uniform and bounded.


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Mixed Full and Partial

Crossbar

FPGA

LocalFPIC

Global

FPIC

Global

FPIC

LocalFPIC

LocalFPIC

FPGA FPGAFPGAFPGA FPGA

Externalconnections

Partialcrossbar

Fullcrossbar


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Circuit Switched versus TimeMultiplexedInterconnect Schemes

Trade-offsbetween the operating speedand thehardware cost.

Time-multiplexing method:

can greatly expandavailable interconnect.allows lower costIC package and PCB.

makes partitioning easier.

BUTSystem power increasesdue to frequent signalswitching (higher hardware cost).

Complex scheduling software.

Slow operating speed.


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Virtual Wires

FPGA FPGA

Physicalwires

Logicaloutputs

Logicalinputs

FPGA FPGA

Mux

DeMu

x

I change space to time

L i E l ti S t


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Logic Emulation Systems and theirinterconnection schemes

System with mesh topology- Quickturns RPM andVirtual Machine Works (IKOS).

System with partial crossbar- Quickturns Enterprise,

Mars, and System Realizer.

System with mixed full and partial crossbar-AptixPrototyping System.

System using time-multiplexed interconnect- VirtualMachine Works (IKOS) , CoBALT and Arkos (Quickturn).

M S l ti i E l t d


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Memory Solutions in Emulators and

future devices/systems

Goal:programmable memories withdifferent width/depth/port combinations.

FPGA-based memories:inefficient of using logic resources.

timing correctness is difficult to be insured.

large or highly multi-ported memories must be

partitioned across several FPGAs.

SRAMswith dedicated or programmable

controllers.


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Logic Emulation Design Flow

Pre-configurationpreparation

Full-chip

configuration

In-circuit

emulation

HDL synthesis

Synthesis

Partitioning

System mapping

P & R

Design downloading

Emulators


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Logic Emulation DesignCompiler and its components

Logic emulation design compileris a large and complexEDA tool which includes:

Front-end design importer.

HDL-based synthesizer.

Clock and timing analyzer.

Partitioner.

System-level placer and router.

FPGA-basedplacer and router.

Obj i f l i l i


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Objectives of logic emulation

compiler

Fast compilationtime.

Fast emulation clock.

Timing correctness.

Easy (ECO ENGINEERING Change Order).

Minimize circuit size.

Design Considerations for Logic


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Emulators

HDL synthesis:Trade-off run-time and quality.

CLB-basedvs. gate-baseddesigns.

Clock and timing analysis:

Timing correctness, hold-time violation free.

Clock skewminimization.

Partitioning:Run time. -

Timing and area.

D i C id ti f L i


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System placement and routing:

Timing.

Completeness of routing.

FPGA-basedplacement and routing:

Fast run time.

Parallel compilation.


Emulators

Remember you

emulate not the same

logic as your design


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Hold-Time Violation

Hold-time violation occurswhen Routing delay > LUT delay!!!

D Q

CK

D Q

CKLUTCLB

Routing delay

Clock distribution problem (Skew)!!!


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Timing Correctness

D Q

CK

D Q

CK

LUT

CLB

Routing delay

Delayelement

Delay insertion


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Timing Correctness

D Q

CK

D Q

CK

LUT

CLB

Clock path

CE

Primary clock Low-skew net

Use clock enablesfor gated clocks


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Methodology and components of LogicEmulator System

Pre-configuration preparation- prepare netlistsand control files for configuration.

Testbed preparation- prepare emulation-basedoperation environment.

Full-chip configuration- download design to the

emulator.

In-circuit emulation- test the design.

Pre Configuration in Emulator


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Pre-Configuration in Emulator

System

Translate the leaf-cell librariesinto emulationprimitives.

Translated libraries must be verified for functional

equivalenceto original.

Modify and redesign some components to attaincompatibility with emulation techniques,such asprecharge logic circuits.

Assemble all the gate-level netlistsfor the entire

design.


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Testbed in Logic Emulator

Design and implement the target ICE board

combining the emulated designwith real

hardware.

Slowdown testbedto emulation speed.

Assemblethe testbed and emulation

equipment.

Full Chip Configuration & In


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Full-Chip Configuration & In-Circuit Emulation

Full-chipconfiguration:

Prepare control files.

Partition the design to fit into the emulationsystem.

Download design into the system.

Verify that the emulation model faithfullyimplements the design as specified by RTL.

In-circuit emulation


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Part IV

Reconfigurable

Computing and

Systems


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General-Purpose Computingvs. Custom Computing

General-purpose computing- applyingapplications on a general-purpose computer.

Custom computing- applying applicationson a custom-made application-specific

hardware.

Field-programmable devices make this into areality.


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Goals of ReconfigurableComputing

Tailorthe architecture to the application.

Minimizeor eliminate instruction interpretation.

Exploit fine grainedparallelism.

Mapsoftware to hardware.


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Applications of reconfigurable

computing

Database search and analysis.

Image processing and machine vision.

Data compression.Signal processing.

Neural networks.

Biology computing.

Medical computing.

Design Automation (PSU)

Many more.

Multi Mode Systems


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ROM

Application 1

Multi-Mode Systems mapvarious applications to a reconfigurable

system

Reconfigurablesystem

Different configurations for read & writeoperations of a tape driver(Honeywell).

Different configurations for different

printer controllers(Tektronix).

Application 2

R Ti R fi ti


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Run-Time Reconfiguration inmilitary image recognition system

Jeep?

Tank?

I/OTruck?

Image data

?

Breaksingle computation into multiple pieces.

Page incomponents as needed(virtual hardware),

ex., automatic target recognition.

C t C ti


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Custom Computing

Application-specific systems.

Numerous applications for similarreconfigurable

systems.

Offers hardware performance, flexibilityto handlenumerous algorithms.

Multi-FPGA systems can be viewed as hardwaresupercomputers.

Tell about DEC Perle


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Reconfigurable Co-processors

Processor

Coprocessor

Program 1

Inst1

Program 2

Inst2- Provide custom instructions

on aper-application basis.

Types of Reprogrammable


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Types of ReprogrammableSystems

Coprocessor

CPU

Attachedprocessing

unit

Memorycaches

I/Ointerface

StandalonePU

PU = processing Unit

Three ways to attach

custom computing units

T f R bl


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Types of ReprogrammableSystems

Attachedand standalone processing units arereprogrammable systems on computer add-oncards and separate reprogrammable cabinets.

Considerations:large communication overheadmayover-shadow the speed gain.

Application-specific coprocessorscan achievesignificant improvement over a wide range ofapplications.


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Types o f Reprogrammab leSystems

Integratethe reprogrammable logic intothe processor itself.

A reprogrammable functional unit can beconfigured on a per-algorithmbasis.

Providing some special-purpose instructionstailored to the needs of a given application.

A hit t f M lti FPGA


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Architectures of Multi-FPGA(Reconfigurable) Systems

The most commonly used topologies:

Mesh:1D (linear array), 2D, and 3D.

Crossbar:full, partial, mixed, andhierarchical.

Hybrid between mesh and crossbar.

Application-specificarchitecture.

Hybrid Topology of a reconfigurable


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Hybrid Topology of a reconfigurable

system

Splash 2:augments a linear array of FPGAs witha crossbar switch.

Goal:Supportingsystolic circuits.

RAM

FPGA

RAM

FPGA

RAM

FPGA

RAM

FPGA

FPGA

16 FPGAs

Ext. InterfaceExt. Interface


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Hyb r id Topology

FPGA

RAM

FPGA

RAM

FPGA

RAM

FPGA

Hostinterface

Anyboard: A linear array of FPGAs augmentedby global buses.


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Hyb r id Topology

4 X 4 meshof FPGAs

RAM

RAM

RAM

RAM

Hostinterface

DECPeRLe-1: a 4 X 4 mesh of FPGAs augmented

with shred global buses.

Application-Specific Topology of


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Application-Specific Topology of

MARC-1, one subsystem

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

FPGA

FPU

Memory

1

1

1

1

4 5 2 3

4 5 2 3

4 5 2 3

The Marc-1: subsystem 1.

Connections to otherFPGAs

Appl icat ion-Speci f ic


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Appl icat ion Speci f ic

Topo logy of Marc-1, cont.

1

5

4

3

2Subsystem1

Subsystem1

The Marc-1

Application in circuit

simulation where the

program to be executed

can be optimized on a

per-run basis.

This is done for

values constant

within that run,

but which may varyfrom dataset to

dataset.


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App l ication-Speci f ic Topo logy

FPGA

RAM

FPGA

RAM

FPGA

RAM

FPGA

RAM

FPGA

RAM

FPGA

RAM

FPGA

RAM

FPGA

RAM

FPGA

RAM

The RM-nc system: neural network.

A h i t t f C t


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Arch i tectu re for Compu terPrototyp ing

FPGA

FPGA

FPGA

FPGAFPGA

FPGAFPGACache memory

Register file

ALU FPU

VME bus

The Mushroom processor

prototyping system.


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Expandable Topologies

Hierarchical crossbar topology: can be

expanded by adding extra level.

- Quickturn systems.

Expandable mesh topology:can be

expanded by connecting individual boards

to form a large mesh.

The Virtual Wires Emulation System (IKOS).

Topology for Adapting Other


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Topology for Adapting OtherComponents

Many multi-FPGA systems include non-FPGA resourcesto provide more generalpurpose solutions.

The MORRPHsystem - sockets next toFPGAs which allow to add arbitrary devices

to the array.

The G800board - contains two FPGAs and

four sockets.



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The COBRA systemContains:based modules (expanding to 2D mesh),

RAM modules,

I/O modules,and bus modules.

The Springbok system

a pre-made daughter board which is able tocontain an arbitrary device(on the top) and anFPGA (on the bottom).

Daughter boards are mounted on a baseplate.



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The Quickturnsystems - external

component adapters.

TheAptixFPCB - a reprogrammable PCB.

Design Methodology for


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Design Methodology forgeneral-purpose configurable

systems

Applications

Hostcomputer

Reprogrammablesystem

Mapping

Typical Software Methodology f


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Typical Software Methodology forgeneral-purpose configurable systems

Applicationspec.

Analysis System-levelsynthesis

Softwarespec.

Codegeneration

Object code

Hardwaresynthesis

Hardwarespec.

Typ ical Software Methodo logy for


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yp gygeneral-purpose configurable systems

Hardware spec.

Synthesis

Partitioning & placement

Pin assignment & routing

FPGA P & R

Bit-stream files

Considerations for such


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Considerations for such

complex software systems

Architectural-specificdesign tasks.

Design automationprocess.

The mapping timedominates the setuptimefor operating the system.

Run-time reconfigurability.

Design Specification and Languages for


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Design Specification and Languages forreconfigurable software systems

Standard software programming languages,e.g., C, C++, FORTRAN, and assembly language, vs.HDLs.

Standard software programming languages - asequentialexecution model.

HDLs- a parallel execution model.

Who will use it and which one is more suitable forsystem description???


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Compilation Issues

Translate code from software languagesinto hardware without losing the inherentconcurrencyof hardware.

Compiler techniques for parallelizing code.

Straight-line code, control flow, and loops.

Transmogrifier C compiler.

System-level and High-


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System-level and High-level Synthesis

System-level design evaluation and analysis.

Design estimation.

Hardware-software partitioning.

Interfacesynthesis.

RTL synthesis.

Logic synthesis and technology mapping.

Partitioning and


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Partitioning and

PlacementTopology-aware partitioningmethods.

Partitioning onto a multi-FPGA system is

equivalent toa placement problem.

Logic utilizationand timing.

Pin Assignment and


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Pin Assignment and

RoutingPin-assignment- the process of determiningwhich I/O pins to be used for each inter-FPGAsignal.

Pin-assignment for a pre-fabricated multi-FPGAsystem is equivalent tothe global routingproblem.

Pin-assignment will greatly affectthe quality ofFPGAs logic utilization and routability.

Run-Time Reconfigurability


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Run-Time Reconfigurability

Virtual hardware virtual memory. What are theirrelations? Artificial Intelligence, robotics. Vision.

Hardware on demand.

What is the Initial Un-configured structure?What are the reconfiguringmethods.

Software supporting time-varying mapping.

Many open problemsneed to be solved in the forthcoming years.

This is a new issue in system design: how much of the processor is

virtual, when to reconfigure?

Applications: Splash 2


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Applications: Splash 2

Stream oriented systolicand SIMDapplications.

Scalable linear arrayof 16 to 256 processingelements (1 XC4010 with 1/2 Mbyte).

VHDL based.

Sequence comparison- 2300M:0.75M cellupdates/sec (Splash 2:Sparc 10).

Edge detection- 10M:242K pixels/sec (Splash

2:Sparc 10).

Applications: PAM (DEC)


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Applications: PAM (DEC)

Programmable Active Memory (PAM).

C++ based and mesh arrays of XC3090(DECPeRLe-1).

Applications:Multiple precision arithmetic.

RSA encryption.

Video compression (JPEG, MPEG, DCT). -High energy physics.

Telecommunications.


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Sources o f some sl idesPeter Alfke

Xilinx, Inc

[email protected]

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FPGA Logic Emulation and Reconfigurable Systems