FR Series MCUs with on-chip DMAC - Fujitsu Global · FR Series MCUs with on-chip DMAC • DMA: The intelligent peripheral assumes control of the system’s buses to conduct direct

FR Series MCUs with on-chip DMAC

Fujitsu Microelectronics America, Inc.

i

Introduction ........................................................................................................................................................... 1

Overview ................................................................................................................................................................ 1

I/O Transfer Methods ............................................................................................................................................... 1

Why DMA?............................................................................................................................................................. 1

DMA Transfer Types ............................................................................................................................................... 1

Synchronous DMA ........................................................................................................................................... 1

Single/Block Transfer ........................................................................................................................................ 2

Demand Transfer............................................................................................................................................... 2

Burst Mode DMA.............................................................................................................................................. 2

Flyby DMA ...................................................................................................................................................... 2

Operation of General DMAC .............................................................................................................................. 2

Features of FR Family DMAC ................................................................................................................................... 3

Operation of FR Series DMAC................................................................................................................................... 4

Features of FR30 Series ........................................................................................................................................... 5

Transfer Modes of FR30 Series ............................................................................................................................ 5

Addressing Modes............................................................................................................................................. 5

Transfer Type ................................................................................................................................................... 5

DMAC Block Diagram of FR30 Series ................................................................................................................. 5

Operation......................................................................................................................................................... 6

Channel Priority: ............................................................................................................................................. 6

Features of FR50 and 65E Series................................................................................................................................ 6

Data Transfer Modes in FR50 and FR65E ............................................................................................................ 6

Addressing Modes ............................................................................................................................................. 6

Transfer Types .................................................................................................................................................. 7

Fly-by Transfer ................................................................................................................................................. 7

DMAC Block Diagram of FR50 and FR65E Series ................................................................................................ 7

Operation......................................................................................................................................................... 8

Channel Priority ............................................................................................................................................... 8

Interrupts and DMA Transfer ............................................................................................................................. 8

Implementation ....................................................................................................................................................... 9

UART without DMA ............................................................................................................................................... 9

UART with DMA .................................................................................................................................................... 9

Flowchart..............................................................................................................................................................10

Conclusion.............................................................................................................................................................10

References..............................................................................................................................................................10


• DMA: The intelligent peripheral assumes control of the system’s buses to conduct direct transfers with primary memory

Why DMA?

DMA requires an extensive amount of special hardware to manage the data transfers and to arbitrating access to the system bus. This might seem to violate our desire to use software wherever possible. However, DMA makes sense when the transfer rates exceed anything possible with software. Even the fastest loop in assembly language comes burdened with lots of baggage. A short code fragment that reads from a port, stores to memory, increments pointers, decrements a loop counter, and then repeats based on the value of the counter takes quite a few clock cycles per byte copied. Hardware DMA controller can do the same with no wasted cycles and no CPU intervention.

DMA transfer Types

DMA was invented basically to move data between I/O to memory and also for memory to memory. Important transfer types are listed in this section.

Synchronous DMA

Traditional Synchronous DMA moves a byte or word at a time between system memory and a peripheral, handshaking with the I/O port for each transfer. This sort of transfer recognizes that the port may not always be in a ready condition; the handshaking is a hardware mechanism to throttle the transactions.

With this sort of transfer, the program sets up the controller and then carries on, obvious to the state of the DMA transaction. The hardware moves one byte or word between memory and I/O each time the I/O port signals it is ready for another transaction. On each read indication, the DMA controller asserts Bus Request, waits for a Bus Acknowledge in response, and then takes over the bus for a single cycle. Then, the DMA controller goes idle again, waiting for another ready signal from the port. Thus, the program

Introduction

Dynamic memory access is used to transfer data from to/from internal memory, internal peripheral or external devices independent of CPU. This application note discusses about the features of FR series DMAC, various transfer modes, priority, and DMA request resources and their implementation. The sample project file at the end of the application note, details the implementation of UART communication using DMAC using block transfer mode.

Overview

DMA is nothing more than a way to bypass the CPU to get to system memory and/or I/O. DMA is usually associated with an I/O device that needs very rapid access to large chunks of RAM.

Direct memory access allows for the high-speed data transfer without going through the CPU. This frees up the CPU to perform other operations thus speeding up overall computing operations.

Fujitsu FR series Micro controllers have up to 8 on chip DMA controllers supporting different transfer modes. More details are given in below sections.

I/O Transfer Methods

During a program’s execution, the micro controller constantly Reads from or Writes to memory locations. The program may also call on the micro controller to Read from or Write to one of the system’s I/O devices. Regardless of how the peripheral is connected to the system (serial or parallel), one of four methods may be used to initiate data transfer between the system and the peripheral. These four methods are listed as follows:

• Polling: The CPU examines the status of the peripheral under program control.

• Programmed I/O: The CPU alerts the designated periph-eral by applying its address to the system’s address bus.

• Interrupt-driven I/O: The peripheral alerts the CPU that it is ready to transfer data.


2


and DMA cycles share bus cycles, with the controller winning any contest for control of the bus. Sometimes this is called “Cycle Stealing”.

Cycle stealing DMA is more complex to implement than Halt DMA, because the DMA controller must have the intelligence to sense the periods of time when the system buses are open.

Cycle stealing DMA can be implemented as single cycle stealing, where the CPU is halted for a single clock cycle—while the DMA controller transfers a single byte—or as full cycle stealing, where the CPU is not stopped and the DMA controller can seize the buses any time the when the micro controller is not using them.

It has following modes: Single/block transfer Demand transfer

Single/Block Transfer

It is also sometimes referred as Step transfer. A single byte (or word) is transferred. The DMA must release and re-acquire the bus for each additional byte. Devices that cannot transfer the entire block of data immediately commonly use this. The peri-pheral will request the DMA each time it is ready for another transfer.

Once the DMA acquires the system bus, an entire block of data is transferred, up to a maximum of 64K. If the peripheral needs additional time, it can assert the READY signal. READY should not be used excessively, and for slow peripheral transfers, the Single Transfer Mode should be used instead.

Demand Transfer

The difference between Block and Demand is the once a Block transfer is started, it runs until the transfer count reaches zero. DRQ only needs to be asserted until DACK is asserted. Demand Mode will transfer one more byte until DRQ is de-asserted, then when DRQ is asserted later, the transfer resumes where it was suspended

Advanced micro controllers offer optimized DMA transfer capabilities because they possess the capability to load several instructions and data internally (called queuing) and work for an extended period of time without the need to access the bus system. The CPU and DMA controller can have access to the buses for varying lengths of time, as long as the DMA controller does not hold them for too many consecutive clock cycles.

Burst Mode DMA

The crudest and simplest DMA method is referred to as HALT, or Burst Mode DMA, because the DMA controller takes control of the bus system and transfers a complete block of data to or from memory in a single burst. While the transfer is in progress, the CPU sits idle, performing No Operation (NOP) instructions to keep its internal registers refreshed

Burst Mode DMA, in contrast to Synchronous DMA, generally assumes that the destination and source addresses can take transfers as fast as the controller can generate them. The program sets up the controller, and then (perhaps after a single ready indication from a port occurs), the entire source block is copied to the destination. The DMA controller gains exclusive access to the bus for the duration of the transfer, during which time the program is effectively shut down. Burst mode DMA can transfer data very rapidly indeed.

Flyby DMA

Flyby DMA feature generally is not supported on many micro controllers. The DMA controller gains access to the bus and puts the source or destination address out. Then, it initiates what are in effect a read and a write cycle simultaneously. The data is read from the source address, and written to the destination, at the same time. This implies that either the source or destination does not require an address, since it is very unlikely that both would use the same. An example might be copying data from memory to an IO port — the source address (a pointer to memory) increments on each transfer, while the destination is always the same IO.

Flyby transactions are very fast since the read/write cycle pair is reduced to a single cycle. Both

Burst and Synchronous types

(Single/Block or Demand) transfers can be supported using Flyby transfer.

Operation of General DMAC

When the peripheral device has data ready to be transferred, it sends a DMA request (DREQ) signal to a DMA controller, which in turn, sends a HOLD input signal to the CPU. The CPU finishes executing the instruction on which it is currently working and places its address and data pins in a high-impedance state (floating), effectively disconnecting the CPU from the buses. At this time, the CPU issues a bus available (BA) or hold acknowledge (HLDA) signal to the DMA controller. The DMA controller, in turn, issues a DMA acknowledge (DACK) to the peripheral, along

Application Note

Fujitsu Microelectronics, America Inc.

3

with the beginning address of the primary memory block to be used, and the necessary R/W and enable signals for the data transfer to begin. When a DMA transfer request is accepted, DMA issues a transfer request to the bus controller. Bus controller passes the right to use the internal bus to DMA at a break in bus operation and DMA transfer starts.

Features of FR Family DMAC

DMAC features of FR30, FR50 and FR65E device series of FR family micro controllers are listed in the below

Table 1.

Table 1: Features of FR DMAC

From the above

Table 1

, it can be observed that unlike FR30 series, FR50 and FR65E series are capable of

Fly by transfer mode

with external memory to memory and also external memory to IO data transfer types.

DMAC Features FR30 Series FR50 Series FR 65E series Remarks

Number of DMAC channels on different devices of the series

Min 5CH and Max 8CH

Max 5CH Max 5CH

Data Transfer modesAnd Transfer Types

3 transfer modes: 1) Block/step 2) Burst 3) Continuous

One Transfer Type: 1) 2 cycle transfer

3 transfer modes: 1) Burst2) Demand3) Block/step

Two Transfer Types1) 2 cycle transfer a) Burst b) Demand c) Block/step2) Fly-by Transfer:

a) Burst b) Demand c) Block/step

3 transfer modes: 1) Burst2) Demand3) Block/step

Two Transfer Types1) 2 cycle transfer a) Burst b) Demand c) Block/step2) Fly-by Transfer:

a) Burst b) Demand c) Block/step

Flyby transfer is a special feature of FR50 and FR65E series. It is supported by only 3 CH: 0, 1, 2They support 1) External memory to external IO 2) External memory to memory transfers.

Channel SelectionMethods

1) Fixed Mode 1) Fixed Mode2) Alternation (or rotation) Mode

1) Fixed Mode2) Alternation (or rotation) Mode

DMA Transfer During Sleep mode

Not possible Yes, Possible Yes, Possible

External transfer Request channels

3ch 1ch to 3ch depending on the device

1ch to 3ch depending on the device

DMA request Resources

1) Ext DMA transfer requests2) PWM interrupt request3) UART TX, RX interrupt request4) A/D converter interrupt request5) 16 bit reload timer interrupt request

1) Ext DMA transfer requests2) External interrupt requests3) UART TX, RX interrupt request4) A/D converter interrupt request5) 16 bit reload timer interrupt request6) SIO interrupt request7) I2C interrupt request

1) Ext DMA transfer requests2) External interrupt requests3) UART TX, RX interrupt request4) A/D converter interrupt request5) 16 bit reload timer interrupt request


4


Operation of FR Series DMAC

Every DMA transfer starts with the software programming the DMA controller, the device that manages these transactions. The code must typically set up destination and source pointers to tell the controller where the data is coming from, and where it is going. A counter must be programmed to track the number of bytes in the transfer. Finally, numerous bits setting the DMA mode and type must be set. These may include source or destination type (I/O or memory), action to take on completion of the transaction (generate an interrupt, restart the controller, etc.), wait states for each CPU cycle, etc.

Now the DMA controller waits for some action to start the transfer. Perhaps an external I/O device signals it is ready by toggling a bit. Sometimes the software simply sets a “start now” flag also called as ‘DENB’. Regardless, the controller takes over the bus and starts making transfers.

Each DMA transfer looks just like a pair of normal CPU cycles. A memory or I/O read from the DMA source address is followed by a corresponding write to the destination. The source and destination devices cannot tell if the CPU is doing the accesses or if the DMA controller is doing them.

During each DMA cycle the CPU is waiting patiently for access to the bus, but cannot perform any useful computation during the transfer. The DMA controller is the bus master. It has control until it chooses to release the bus back to the CPU.

Depending on the type of DMA transfer and the characteristics of the controller, a single pair of cycles may terminate to allow the CPU to run for a while, or a complete block of data may be moved without bringing the processor back from the land of the idle.

Once the entire transfer is complete the DMA controller may quietly go to sleep, or it may restart the transfer when the I/O is ready for another block, or it may signal the controller using interrupt that the action is complete.

To summarize, the micro controller programs the DMA controller with parameters about the transfers, the controller tri-states the CPU and moves data over the CPU bus, and then when the entire block is done the controller signals completion via an interrupt.

Above explained operation is shown using state diagram in

Figure 1

below.

Figure 1.

Not Enable

Not Enable

Interruptassertion

Enable

Enable

DMACT = 0

Enable &check for

DMACT > 0

Idle

Stop

Operation End

Application Note


5

Features of FR30 Series

Transfer Modes of FR30 Series

FR30 Series supports the following data transfer types as described in

Table-1

1. Block/Step transfer

2. Burst Transfer

3. Continuous Transfer

Block/step transfer method is synchronous data type transfer as explained in section

Synchronous DMA.

During Single/Block transfer, DMA transfer is performs once per one transfer request. Transfer request generally referred, as DREQ can be an edge or level sensitive. Each time a DMA transfer is performed, the bus privilege is passed to the CPU. As the name indicates, transfer unit is determined by block size. Larger the block, higher the DMAC transfer rate but lower the CPU throughput.

In Burst transfer method as explained in section

Burst Mode DMA,

DMA transfer is performed as often as specified transfer count for one transfer request DREQ either level or edge sensitive. Once the transfer register count becomes zero, the DMA transfer gets completed and the bus privilege is passed to the CPU.

In Continuous Transfer method, DMA transfer is performed while the transfer request DREQ maintains an active level. DREQ can be only level sensitive in this case. During this mode, precaution should be taken about the DMA transfer overrun. During transfer destination access, deassert the DREQ before the DACK signal rise.

Addressing Modes

32-bit full addressing with transfer address increment, decrement or fixed can be selected using software. Transfer source /destination address is incremented or decremented in byte, half word and word sizes.

Transfer Type

DMAC uses normal transfer method by using a read operation and a write operation. Data is read from an address in the transfer source register and written to another address in the transfer destination register. It is also called two-cycle transfer,

DMAC Block Diagram of FR30 Series

For detailed DMA Controller operation and register configuration, please refer to the device hardware manual. FR30 series DMAC block diagram is shown for reference in

Figure 2.

Figure 2.

Edge/leveldetect circuitDREQ0-2

Internal resourcetransfer request

Data buffer

Sequencer

Switcher

33

DACK0-2EOP0-2

Interrupt request

Data bus

3

8

3

5

DPDP

DACSR

DATCR

DMACT

SADR

DADR

BLK DEC

INC/DEC

Mode

BLK


6


Operation

The DMA controller supports multiple channels, each of which can be programmed independently. Each channel has a dedicated DMA request line and channel registers, and can be configured to different priority settings. When the DMA controller consists of multiple channels, an internal arbiter is provided with the core to grant bus ownership to one channel at a time according to the priority settings. Each channel contains source and destination address registers, control register, and transfer count register. The channel’s DMA operation is specified in the control register, and the number of words to transfer is specified in the transfer count register.

FR30 series, supports following transfer source and destination address mode specification.

1. Transfer source address incremented/decremented to Destination address incremented/decremented: This is also called as memory to memory data transfer

2. Transfer source address incremented/decremented to Destination addressFixed: This is called as memory to IO transfer

3. Transfer source address incremented fixed to Destination source address incremented/decremented: This is referred as IO to memory data transfer

4. Transfer Source address fixed to destination source address fixed: This is called as IO-to-IO data transfer.

Special registers are meant for specifying above transfer addresses, transfer data size, transfer count and block sizes as shown in above bock diagram.

FR 30 series devices have three channels of external transfer request input pins and external transfer request acceptance/ transfer completion output pins among 5 or 8 DMA channels. External devices can thus request/acknowledge DMA transfer.

Using FR series, data transfer to/from

External or internal

memory/IO to

Internal

memory/IO is possible. But Data transfer to/from

External

memory/IO to

External

memory/IO is not possible unlike FR50 and FR65E series.

Table 2: FR30 Series Transfer Direction

Channel Priority

FR30 series has only fixed mode channel selection method. Once the DMAC is activated by a DREQ of one particular channel, a DMA transfer request occurring for another channel is suspended until the previous transfer in progress is completed.

Hence the priority must be set for the channels before starting the transfer. Channel number fixes this order of priority. Lower the channel number, higher the priority.

Example: CH0 has high priority than CH1, CH2, CH3, and CH4

Priority decreases from CH0 to CH4.

Features of FR50 and 65E Series

Data Transfer Modes in FR50 and FR65E

Data transfer modes in these series are:

1. Demand Transfer

2. Block/Step transfer

3. Burst Transfer

Demand and Block/step transfers are categories of synchronous transfer as explained in section

Synchronous DMA

.

Single/Block Transfer

.

For burst transfer refer to section

Burst Mode DMA

.

Addressing Modes

Series support 32-bit full addressing with increment/decrement/fixed modes.

Specifies transfer address for 2 cycle and also flyby transfer.

Transfer source address Direction

Transfer Destination address

External Area (memory/IO)

To Internal IO


To Internal memory

Internal IO To External Area (memory/IO)

Internal memory To External Area (memory/IO)

Application Note


7

Transfer Types:

FR50 and FR65E series have a special feature by having two transfer types:

1. Two Cycle transfer (Normal Transfer)

2. Fly by transfer: External Memory to IO External IO to Memory

As explained in earlier section

Transfer Type

, FR30 series supports normal transfer also called as two cycle transfer.

In addition to this normal transfer method, FR50 and FR65E series support ‘Fly-by transfer’.

Flyby Transfer

As explained in section

Flyby DMA,

implementation of

Flyby DMA is found rarely in many micro controllers. Fujitsu FR50 and FR65E series support this DMA transfer type. It has following advantages:

• Fast data transfer, requires only single cycle for read/write

• Flyby transfer supports Burst and synchronous data transfer modes

• Provides a mechanism for external memory to IO and IO to memory access.

Flyby is a way to move

data directly

from the source of the data to its destination, without having this data pass

through

the controlling device. While the source drives the data onto the data bus, the destination immediately latches it into its buffers/memory. The data does not pass through the DMAC therefore at least

one half

of the address bus bandwidth is saved. Flyby cycles are requested by the DMA channel, and controlled by the memory unit.

This method provides a limitation in the sense that DMA can only move data between devices (I/O ports) and memory

DMAC Block Diagram of FR50 and FR65E Series

Figure 3.

DMA transfer requestto bus controller

Read

AccessAddress

Write-back

Writ

e-ba

ck

Write-back

DDNO

Read/writecontrol

Counter

Counter

DMA startcause selection

circuit andrequest

acceptancecontrol

Priority circuit

X-b

us

Bus

con

trol

sec

tion

IRQ[4:0]

Peripheral start request/stop input

To transfer controller

Clear peripheral interrupt

External pin start request/stop input

MCLREQ

Statustransistion circuit

DMA control

DMAC 5-channel block diagram

DSAD 2-step register SADRSADM, SASZ[7:0]

DDAD 2-step register DADRDADM, DASZ[7:0]

DSS[3:0]

ERIR, EDIR

TYPE, MOD, WS

Buffer

Buffer

Selector

Selector

BLK register

DDNO register

DTC 2-step register DTCR

Write

Tobuscontroller

Sec

tor

Sec

tor

Cou

nter

buf

fer

Cou

nter

buf

fer

Add

ress

cou

nter

Sec

tor

Bus

con

trol

sec

tion


8


Operation

DMA controller block of FR50 and FR65E series is a multifunctional DMAC that controls high-speed data transfer. Each transfer channel can individually specify several functions. When activation has been enabled, a channel doesn’t start a transfer operation until it receives a transfer request. Once a channel receives, a transfer request, it issues a DMA transfer request to the bus controller. Then it gets the right to use the bus from bus controller and starts transfer. Data is transferred in the sequence defined by the type of mode set for that corresponding channel.

FR50 and FR65E series, support following transfer source and destination address mode specification.

1. Transfer source address ‘incremented/decremented’ to Destination address ‘incremented/decremented’: This is also called as memory to memory data transfer

2. Transfer source address ‘incremented/decremented’ to Destination address ‘Fixed’: This is called as memory to IO transfer

3. Transfer source address ‘fixed’ to Destination source address ‘incremented/decremented’: This is referred as IO to mem-ory data transfer

4. Transfer Source address ‘fixed’ to destination source address ‘fixed’: This is called as IO-to-IO data transfer.

Special registers are meant for specifying above transfer addresses, transfer data size, transfer count and block sizes as shown in above bock diagram.

FR 50 and FR65E series devices have three channels of external transfer request input pins and external transfer request acceptance/ transfer completion output pins among 5 DMA channels. External devices can thus request/acknowledge DMA transfer.

Data transfer to/from

External or internal

memory/IO to

External or

Internal

memory/IO is possible unlike FR30 series

Table 3: FR50/FR65E Transfer Direction

Please note that in demand type of data transfer, transfer area can only be external area.

And in this mode, transfer read can be memory to IO and write can be IO to memory only.

Channel Priority

Channel priority as explained in

Table 1

is of 2 types. FR50 and FR65E series have an additional method called Alternation or Rotation mode.

Initially as in fixed mode, CH0 and CH1 have same priority as in fixed mode (that is CH0>CH1). Later at the end of each transfer operation, the priority of the channel will be reversed as CH1>CH0. This type of rotation method of priority setting is very effective when continuous or burst types of data transfers are used.

Interrupts and DMA Transfer

During DMA transfer, interrupts are generally not accepted until the transfer is complete.

If DMA transfer request occurs during interrupt processing, the transfer request has high priority and interrupt processing is stopped until DMA transfer gets completed. If in any case, non-maskable interrupt or interrupt with high priority occurs, DMAC temporarily cancels the transfer request until the interrupt request is cleared.

Transfer source address Direction

Transfer Destination address


To Internal IO


To Internal memory

Internal IO To External Area (memory/IO)

Internal memory To External Area (memory/IO)


To External Area (memory/IO)

Application Note


9

Implementation

The downloadable sample program provided along with this application note will give us the idea about the capability and advantages of DMA transfer. The following example will explain the differences between serial IO transfer with and without a DMA controller.

UART without DMA

In standard UART receive operation, the bits are sampled in the middle of the bit and are loaded in to the shift register. Upon completion, the bits will be latched to the receive buffer register and a flag will be raised to signal an interrupt. An ISR serviced by the CPU is then used to move the data from the receive buffer register into memory. A programmed CPU routine to read bytes one at a time from the controller wastes CPU time.

In such situations DMA is useful to free CPU from this low level work.

UART with DMA

When DMA is used, the CPU supplies the DMA controller with three types of information.

First the memory addresses of the source of the transfer are copied in to the source pointer register. Then the destination address for the transfer is copied into destination pointer register. Finally the number of bytes to be transferred will need to be loaded into the count register of DMA. A DMA request factor also should be specified. Once the DMA is active, data transfer starts every time a DMA transfer request signal occurs.

Just as with the standard UART receive operation, the bits are sampled and loaded into the receive buffer register and a flag will be raised. This time however, the DMA controller will be serviced and the byte in the receive buffer register is copied into memory specified by the DMA destination address depending on the application, the DMA address is then either incremented or stays fixed and the DMA count is decremented. This continues until the DMA count becomes zero at which times the DMA controller causes an interrupt. When the CPU starts up again, it doesn’t need to copy the block to the memory as it is already done by the DMA.

This method demonstrates the DMA transfer from and to internal IO (UART) to internal memory (RAM) area as shown in below

Figure 4

using MB91F362 device of FR50 family.

Figure 4.

This method makes use of two-cycle block transfer method with fixed channel priority using 16-bit width and fixed addressing

mode. Sample project file is provided along with this application note.

Read cycle

DMAC

Internal RAM area internal I/O area transfer

RAM I/OROM or RAM

CP

U

SD

RA

M I/

FE

xten

ded

Bus

Inte

rfaceMB91xxx

Buscontroller

Data bufferD-bus

I-bus X-bus

F-bus

Write cycle

DMAC

RAM I/OROM or RAM

CP

U

SD

RA

M I/

FE

xten

ded

Bus

Inte

rfaceMB91xxx

Buscontroller

Data bufferD-bus

I-bus X-bus

F-bus


10


Flowchart

Conclusion

FR series micro controllers have fully featured on chip DMA controller that supports different transfer modes including flyby mode.

References

1) MCU Product CD ROM

2) FMA website http://www.fma.fujitsu.com/

Main ( )

DMACInit ( )

UARTInit ( )

Transmitgreetings

Endless loop

DMACInit ( )

Initialize DMACR forbyte transfer

Set DMACARegister for UART0 Txand RX interrupt, block

size, transfer count

Set DMACB forsource/destinationaddresses, type of

transfer and reload count

Enable DMAC

Set DMA interrupt level

Return

UARTInit ( )

Set baud rate, databytes, parity, stop bits

Set UART0 controlregister for interrupt ontransmit buffer empty

Set control register toenable transmission

and reception

Return

Application Note


11

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MCU-AN-20976-5/2003

Documents

FR Series MCUs with on-chip DMAC - Fujitsu Global · FR Series MCUs with on-chip DMAC • DMA: The intelligent peripheral assumes control of the system’s buses to conduct direct