Fractional-ordermemristiveneuralsynapticweighting

862 Pu et al. / Front Inform Technol Electron Eng 2021 22(6):862-876

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Fractional-order memristive neural synapticweightingachievedby pulse-based fracmemristor bridge circuit∗

Yifei PU1, Bo YU1,2, Qiuyan HE†‡1, Xiao YUAN†‡3

1College of Computer Science, Sichuan University, Chengdu 610065, China2School of Physics and Engineering Technology, Chengdu Normal University, Chengdu 611130, China

3College of Electronics and Information Engineering, Sichuan University, Chengdu 610065, China†E-mail: [email protected]; [email protected]

Received Feb. 23, 2020; Revision accepted Aug. 23, 2020; Crosschecked May 8, 2021

Abstract: We propose a novel circuit for the fractional-order memristive neural synaptic weighting (FMNSW).The introduced circuit is different from the majority of the previous integer-order approaches and offers importantadvantages. Since the concept of memristor has been generalized from the classic integer-order memristor to thefractional-order memristor (fracmemristor), a challenging theoretical problem would be whether the fracmemristorcan be employed to implement the fractional-order memristive synapses or not. In this research, characteristics ofthe FMNSW, realized by a pulse-based fracmemristor bridge circuit, are investigated. First, the circuit configurationof the FMNSW is explained using a pulse-based fracmemristor bridge circuit. Second, the mathematical proof ofthe fractional-order learning capability of the FMNSW is analyzed. Finally, experimental work and analyses of theelectrical characteristics of the FMNSW are presented. Strong ability of the FMNSW in explaining the cellularmechanisms that underlie learning and memory, which is superior to the traditional integer-order memristive neuralsynaptic weighting, is considered a major advantage for the proposed circuit.

Key words: Fractional calculus; Fracmemristor; Fracmemristance; Fractional-order memristor; Fractional-ordermemristive synapses

https://doi.org/10.1631/FITEE.2000085 CLC number: TP183; TN6

1 Introduction

Neural synaptic weight refers to the influencestrength of a connection between two neurons. Theterm is ususally used in neuroscience and artificialbrain-inspired neural networks, as described in Iyeret al. (2013). In biological neuroscience, signal trans-mission is performed by interconnected networks ofnerve cells or neurons, which resembles the trans-mission function in the computational case. The

‡ Corresponding authors* Project supported by the National Key Research and Develop-ment Program of China (No. 2018YFC0830300) and the NationalNatural Science Foundation of China (No. 61571312)

ORCID: Yifei PU, https://orcid.org/0000-0003-2975-4976; Qiu-yan HE, https://orcid.org/0000-0002-4983-778X; Xiao YUAN,https://orcid.org/0000-0003-3003-0326c© Zhejiang University Press 2021

changes occurring in synaptic weight are well-knownas synaptic plasticity, which is the ability of synapsesto become stronger or weaker over time in responseto fluctuations in their recent patterns of activity(Hughes, 1958). Hebbian theory is an original at-tempt to explain synaptic plasticity, which is theadaptation of brain neurons during the learning pro-cess (Hebb, 1949). One of several phenomena un-derlying synaptic plasticity is long-term potentiation(LTP), which is a long-lasting increase in synapticweight, as explained in Bliss and Collingridge (1993)and Cooke and Bliss (2006). Long-term depression(LTD) is the opposing process to LTP, which wasdiscussed in Massey and Bashir (2007). In artificialneural networks, the vector of inputs and that ofoutputs are interconnected with synaptic weights.

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Neurons that fire together wire together (Hebb,1949). A number of efficient learning rules suchas Hebb’s rule (Hebb, 1949; Magee and Johnston,1997), Oja’s rule (Oja, 1982), radial basis functions(Powell, 1977), and the backpropagation algorithm(Battiti, 1992) can be used to change neural synap-tic weights. As a number of theoretical and ex-perimental problems became known, correspondingcomputational modified models have been suggestedto learn the relationship between biological neurons.For instance, a supervised error-backpropagation al-gorithm was introduced for a network of spiking neu-rons that encoded information in the timing of indi-vidual spike times (Bohte et al., 2002). A number ofstochastic computational elements used in artificialneural networks were examined in Brown and Card(2001a, 2001b). A content-addressable memory sys-tem was provided based on the aspects of neurobiol-ogy but readily adapted to integrated circuits in Hop-field (1982). In dual whole-cell voltage recordingsfrom pyramidal neurons, the coincidence of postsy-naptic action potentials and unitary excitatory post-synaptic potentials was explored in Markram et al.(1997). In addition, for dissociated rat hippocam-pal neurons, persistent potentiation and depressionof glutamatergic synapses were induced by corre-lated spiking of presynaptic and postsynaptic neu-rons (Bi and Poo, 1998). Furthermore, a very-high-performance Viterbi decoder with a circularly con-nected two-dimensional analog cellular neural net-work cell array was disclosed in Kim et al. (2005).Weight limitation constraints were applied to thespike time error-backpropagation algorithm for tem-porally encoded networks of spiking neurons in Wuet al. (2006). Also, synapses in a spiking neural Psystem were endowed with integer weight denotingthe number of synapses for each pair of connectedneurons in Pan et al. (2012). However, due to thelack of a proper device to implement the synapses,research in this area has only had limited successpractically.

To alleviate the explained problem, the greatpotential for exploiting the applications of the fourthmissing circuit element, memristor (Chua, 1971,1980a, 2003, 2011, 2012; Chua and Kang, 1976;Strukov et al., 2008; Borghetti et al., 2010), to neuralnetworks has been investigated by many researchers(Snider, 2007; Jo et al., 2010; Adhikari et al., 2012,2014, 2015; Kim et al., 2012; Sah et al., 2012; Li

et al., 2013; Wang et al., 2015; Yang et al., 2018;Zhang CX et al., 2018). Memristor was originally en-visioned (Chua, 1971) and then generalized to mem-ristive systems (Chua and Kang, 1976), by circuittheorist Chua, as a missing nonlinear passive two-terminal electrical component (Chua, 1980a). Thiscomponent has the non-volatility property as indi-cated in Chua (2003, 2011, 2012), Strukov et al.(2008), Borghetti et al. (2010), and Prodromakiset al. (2012). Symbol denotes the memris-tor. The memristor is a new nonlinear circuit ele-ment that has the properties of memory and sim-ilar synapse. Zhang P et al. (2019) proposed ananochannel-based interfacial memristor to emulatethe analog weight modulation of synapses. Further-more, Krishnaprasad et al. (2019) introduced an elec-tronic synapse with basic synaptic behaviors, whichwas realized with MoS2/graphene memristors. Anartificial synapse with tunable synaptic behavior onthe basis of a solution-processed memristor was ex-plained in Zhou et al. (2019). Fu et al. (2020) pro-posed a type of diffusive memristor with the proteinnanowires harvested from the bacterium to simulatenerve synapses with low power. Snider (2007) in-troduced a memristor-based self-organized networkusing dedicated connections for inhibitory weighting.Kim et al. (2012) proposed a memristor bridge circuitconsisting of four identical memristors to performzero, negative, and positive synaptic weightings. Ad-hikari et al. (2012) offered a novel analog hardwarearchitecture of a memristor bridge synapse-basedmultilayer neural network and its learning scheme.Sah et al. (2012) proposed a simple and compactmemristor-based bridge circuit that was able to carryout signed synaptic weighting in neuron cells. Liet al. (2013) presented a memcapacitor bridge circuitconsisting of four identical memcapacitors. Adhikariet al. (2014) proposed a learning architecture formemristor-based multilayer neural networks. Theyalso proposed a memristor-based circuit architecturefor multilayer neural networks (Adhikari et al., 2015).Wang et al. (2015) introduced a spintronic memristorbridge synapse circuit. Yang et al. (2018) discussedthe excitatory and inhibitory actions of a memristorbridge synapse. In the essence of mathematics, theaforementioned memristor bridge synapses were ofinteger-order memristive neural synaptic weightings.

At present, fractional calculus has becomea key novel branch in mathematical analysis as


discussed in Oldham and Spanier (1974) and Pod-lubny (1998). However, the application of frac-tional calculus to neural networks, especially to spik-ing neural networks, is an emerging discipline ofresearch. Fractional calculus has evolved to be apromising mathematical method for physical scien-tists and engineers. Some remarkable results andideas have proved that fractional calculus can bea useful tool in many scientific fields such as diffu-sion processes (Özdemir and Karadeniz, 2008), vis-coelasticity theory (Koeller, 1984), fractal dynamics(Rossikhin and Shitikova, 1997), fractional control(Podlubny et al., 2002), image processing (Pu et al.,2018b), fractor (Pu, 2016a, 2016b), fracmemristor(Fouda and Radwan, 2013, 2015; Yu and Wang, 2015;Yu et al., 2015; Pu and Yuan, 2016; Shi and Hu, 2017;Pu et al., 2018a), and neural networks (Pu, 2016c;Pu et al., 2017a, 2017b). The application of frac-tional calculus in neural networks is mainly due to itsinherent advantages such as long-term memory, non-locality, and weak singularity. Important propertiesof fractional calculus were discussed in Oldham andSpanier (1974) and Podlubny (1998). The basic fea-ture of fractional calculus has extended the conceptsof integer-order difference and Riemann sums. It isworth underlining that characteristics of fractionalcalculus are considerably different from those of clas-sic integer-order calculus. For instance, fractionaldifferential, except based on the Caputo definition, ofa Heaviside function is nonzero, whereas its integer-order differential must be zero (Oldham and Spanier,1974; Podlubny, 1998). From Chua’s axiomatic cir-cuit element system (Chua, 1971, 1980a, 2003, 2011,2012; Chua and Kang, 1976) and according to con-stitutive relation, logical consistency, axiomatic com-pleteness, and formal symmetry, it can be assumedthat there should be a capacitive and an inductivefractional-order memristor corresponding to a ca-pacitive and an inductive fractor, respectively (Pu,2016a, 2016b). The concept of the memristor wasgeneralized preliminarily from classic integer-ordermemristor to fractional-order memristor (Fouda andRadwan, 2013, 2015; Yu and Wang, 2015; Yu et al.,2015; Pu and Yuan, 2016; Shi and Hu, 2017; Puet al., 2018a). There are two types of fractional-order memristor, i.e., the capacitive fractional-ordermemristor and the inductive fractional-order mem-ristor (Pu and Yuan, 2016). The “fractional-ordermemristor” and the “fractional-order memristance”

are abbreviated as “fracmemristor” and “fracmemris-tance,” respectively (Pu and Yuan, 2016). Electricalproperties of the capacitive fracmemristor fall in be-tween those of the capacitor and those of the mem-ristor, as explained in Pu and Yuan (2016) and Puet al. (2018a). Similarly, electrical properties of theinductive fracmemristor fall in between those of theinductor and those of the memristor (Pu and Yuan,2016; Pu et al., 2018a). Then, we combine the sym-bol of the capacitor and that of the memristor todenote the fracmemristor as symbol . Further-more, denote the positive incremental fracmemris-tor and negative one as and , respectively.In Pu and Yuan (2016) the generic fractional-orderdriving-point impedance functions of an arbitrary-order capacitive and inductive fracmemristor in theirnatural implementations were derived, respectively.Furthermore, Pu et al. (2018a) discussed the pro-posal for the first preliminary attempt of a fea-sible hardware achievement for an arbitrary-orderfracmemristor and the recognition of the fingerprintof the fracmemristor. Therefore, based on the afore-mentioned studies on the fracmemristor (Fouda andRadwan, 2013, 2015; Yu and Wang, 2015; Yu et al.,2015; Pu and Yuan, 2016; Shi and Hu, 2017; Pu et al.,2018a), a challenging theoretical problem would bewhether the fracmemristor can be applied to achievethe fractional-order memristive synapses or not. Inthis research, the fractional-order memristive neu-ral synaptic weighting (FMNSW) is introduced tobe achieved by a pulse-based fracmemristor bridgecircuit.

2 Backgrounds

This section presents a brief introduction to thenecessary theoretical background for fractional cal-culus, memristor, and fracmemristor.

First, the commonly used fractional calculusdefinitions in Euclidean measure are Grünwald-Letnikov, Riemann-Liouville, and Caputo (Old-ham and Spanier, 1974; Podlubny, 1998). In thisstudy, we adopt mainly the Grünwald-Letnikov de-fined fractional calculus as follows. The Grünwald-Letnikov definition of fractional calculus for causalsignal f(x) is given as

G−LaD

vxf(x) =


limN→∞

{(x − a)−v

Γ(−v)N−v

N−1∑k=0

Γ(k − v)

Γ(k + 1)f

(x− k

x− a

N

)},

(1)

where f(x) is a differintegrable function (Oldhamand Spanier, 1974; Podlubny, 1998), [a, x] is durationof f(x), N is the number of partitions of the duration,v is an arbitrary real number, Γ(α) =

∫∞0

e−xxα−1dx

is the Gamma function, and G−LaD

vx denotes the

Grünwald-Letnikov defined fractional differential op-erator. The Grünwald-Letnikov defined fractionalcalculus is readily calculated, which is related onlyto the discrete sampling value f (x− k(x− a)/N)

of f(x) and not to the derivative or integral valueof f(x). If f(x) is a causal signal and its frac-tional primitives are zero, the Fourier transform ofthe v-order fractional differential operator (Oldhamand Spanier, 1974; Podlubny, 1998) is described asF[G−L

0Dvxf(x)

]= (jω)vF [f(x)], where F(·) denotes

the Fourier transform, j presents the imaginary unit,and ω denotes an angular frequency. In this study,equivalent notations Dv

x = G−L0D

vx are used in an

interchangeable manner.Second, the memristor, M , completes the set of

relations with (Chua, 1971)

φ [q(t)] = M [q(t)] q(t), (2)

where φ, q, and t denote the magnetic flux, quantityof electric charge, and time variable, respectively.The slope of this function is called the memristance,r(q), which is similar to variable resistance (Chua,1971), expressed as

vin(t) =dφ(q)

dqiin(t)

=

[M(q) + q

dM(q)

dq

]iin(t)

= r(q)iin(t) = h(q) ∗ iin(t), (3)

where vin(t) and iin(t) denote instantaneous values ofthe input voltage and input current of a memristor,respectively. The symbol “∗” denotes convolution,r(q) = [M(q) + qdM(q)/dq] and h(q) denote mem-ristance and transmission function of a memristor,respectively, where q(t) = I−1

t iin(t) =∫ t

0iin(t)dt.

Then, we will have r(q) = (h(q) ∗ iin(t))/iin(t). Fur-thermore, the small-signal behavior method is an effi-cient approach for studying a resistive nonlinear net-work, as discussed in Chua (1978a, 1978b, 1980b).

Eq. (3) indicates that in the case of small-signal be-havior, the Laplace transform of vin(t) = r(q)iin(t)

is Vin(s) =1

2π· L{r [q(t)]} ∗ Iin(s), where L{ } rep-

resents the Laplace transform and s denotes a com-plex variable of the Laplace transform. Thus, inEq. (3), the Laplace transform of vin(t) = h(q)∗iin(t),Vin(s) = H(s)Iin(s), achieves a multiplication in theLaplace transform domain, where H(s) = L{h [q(t)]}is reactance of the memristor (Pu et al., 2018a). Foran arbitrary-order capacitive or inductive fracmem-ristor in their natural implementations, the genericfractional-order driving-point impedance functionwas derived (Pu and Yuan, 2016; Pu et al., 2018a),given as

FMc−v = FMc

−(η+p)

=Vin(s)

Iin(s)= c−v [H(s)]

1−ps−v, (4)

FMlv = FMl

η+p

=Vin(s)

Iin(s)= lv [H(s)]

1−psv, (5)

where FMc−v and FMl

v represent the fractional-orderdriving-point impedance function of a purely idealv-order capacitive fracmemristor and that of an in-ductive fracmemristor, respectively, and c and l arecapacitance and inductance, respectively. rc−v(q) =

cvL−1{[H(s)]1−p} and rlv(q) = lvL−1{[H(s)]1−p} arerespectively capacitive fracmemristance and induc-tive fracmemristance, where L−1{ } is the inverseLaplace transform. v = η + p is a non-negative realnumber, η is a non-negative integer, and 0 ≤ p ≤ 1.Note that, if v = 0, then η = 0 and p = 0. Eqs. (4)and (5) identically degenerate to the driving-pointimpedance function of the resistor. Furthermore, ifv is a positive integer, then η = v − 1 and p = 1.Eqs. (4) and (5) degenerate to the driving-pointimpedance function of the capacitor and that of theinductor, respectively. In addition, if 0 < v < 1,then η = 0 and 0 < p < 1. Eqs. (4) and (5) representthe v-order (0 < v < 1) driving-point impedancefunction of the capacitive fracmemristor and that ofthe inductive fracmemristor, respectively. In addi-tion, if v > 1 is a positive fraction, then η = [v]

and 0 < p < 1, where [ ] is the rounding opera-tion. Eqs. (4) and (5) represent the correspondingv-order (v > 1) driving-point impedance function ofthe capacitive fracmemristor and that of the induc-tive fracmemristor, respectively.


3 Fractional-order memristive neuralsynaptic weighting

In this section, the FMNSW achieved by a pulse-based fracmemristor bridge circuit is implemented.

To implement the FMNSW and to start with,the corresponding pulse-based fracmemristor bridgecircuit should be achieved. The pulse-basedfracmemristor bridge circuit can be obtained by twov-order oppositely incremental capacitive fracmem-ristors (FM1

1 and FM12) with the same circuit param-

eters (Fig. 1).In Fig. 1, the input voltage v1in(t) is a positive or

negative pulse signal that inputs at the input port ofa pulse-based fracmemristor bridge circuit. Two in-tegrated operational amplifiers A1

1 and A12 construct

two identical voltage-to-current converters in phaseinput mode. FM1

1 is a negative incremental fracmem-ristor, while FM1

2 is a positive one. Hence, whetherthe polarity of v1in(t) is positive or negative is not im-portant, and the fracmemristance variation tendencyof FM1

2 is in the opposite direction of FM11. There-

fore, according to Kirchhoff’s current law (KCL) andKirchhoff’s voltage law (KVL), from Fig. 1 the fol-lowing relationships are derived:

i1in(t) = i2in(t) =v1in(t)

rs, (6)

I1in(s) = L{i1in(t)} = I2in(s) = L{i2in(t)}, (7)

vFM11(t) = v0 − L−1{c−v [H(s)]

1−ps−vI1in(s)}, (8)

vFM12(t) = v0 + L−1{c−v [H(s)]

1−ps−vI1in(s)}, (9)

v1A(t) = vFM11(t) + v1in(t), (10)

v1B(t) = vFM12(t) + v1in(t), (11)

where v0 is an initial voltage drop across FM11 or

FM12. Thus, from Eqs. (6)–(11), the output voltage

v1out(t) of a pulse-based fracmemristor bridge circuitis equal to the potential difference between point B

and point A, given as

v1out(t) = v1B(t)− v1A(t)

= 2L−1{c−v [H(s)]1−p

s−vI1in(s)}. (12)

Eq. (12) implies that since H(s) = L{h [q(t)]}is reactance of the memristor constituting an in-cremental capacitive fracmemristor, the synapticweight of a pulse-based fracmemristor bridge cir-cuit is a nonlinear function with long-term memory.

In artificial neural networks, the synaptic weight ofa pulse-based fracmemristor bridge circuit obtainsfractional-order memristive nonvolatile weight stor-age. The fracmemristor bridge synapse is composedof two incremental capacitive fracmemristors withopposite operations. By applying a programmedpulse signal v1in(t), the output voltage v1out(t) of apulse-based fracmemristor bridge circuit can be setto a desired value, which can be expressed as

v1out(t)

⎧⎪⎨⎪⎩

> 0, L−1{c−v [H(s)]1−p

s−vI1in(s)} > 0,

= 0, L−1{c−v [H(s)]1−p

s−vI1in(s)} = 0,

< 0, L−1{c−v [H(s)]1−p

s−vI1in(s)} < 0.

(13)In the first step, to provide a transparent discus-

sion, in Fig. 1, the pulse-based fracmemristor bridgecircuit is implemented using two v-order oppositelyincremental capacitive fracmemristors with identicalcircuit parameters. However, in an actual circuit, thecircuit parameters (rp and rs) of these two v-order in-cremental capacitive fracmemristors can be different.Hence, in this case, i1in(t) = v1in(t)/rs1 and i2in(t) =

v1in(t)/rs2 are derived, where rs1 and rs2 are the biasresistances of FM1

1 and FM12, respectively. Then, we

have vFM11(t) = v0 − L−1{c−v [H(s)]

1−ps−vI1in(s)}

and vFM12(t) = v0 + L−1{c−v [H(s)]

1−ps−vI2in(s)}.

In a similar way for deriving Eq. (12), weobtain v1out(t) = L−1{c−v [H(s)]

1−ps−vI2in(s)} +

L−1{c−v [H(s)]1−p

s−vI1in(s)}.In the second step, weighted signals of a biolog-

ical synapse are summed in each unit. In a simi-lar way for biological synapses, by applying a pulse-based fracmemristor bridge circuit, the fracmemris-tor bridge synaptic circuit can be achieved (Fig. 2).

rs i1inFM1

1

rp

rp

v1in v1

out

v1A

A

vFM11

A11

A12

rsi1in

FM12 B

v1BvFM2

1

+

+

+

−

−

−

Fig. 1 Pulse-based fracmemristor bridge circuit


In Fig. 2, A11, A1

2, A13, and A1

4 are four integratedoperational amplifiers, of which A1

3 constructs a sub-tractor and A1

4 gives a voltage-to-current converterin reversed-phase input mode. rL is a load resistor,and i1L is load current that flows through rL. Thus,from Fig. 2, under individual effect of v1A and v1B, weobtain

v13(t) =rfrt

[v1B(t)− v1A(t)

]. (14)

As for A14, from Eqs. (12) and (14), it can be

written as

i1L(t) = i11(t) =v13(t)

r11

=1

r11

rfrt

[v1B(t)− v1A(t)

]=

rfr11rt

v1out(t). (15)

From Eq. (15), load current i1L(t) dependsmerely on v1B(t)− v1A(t), and has nothing to do withthe load resistor rL. Therefore, the fracmemristorbridge synaptic circuit implements a differential cur-rent source in practice.

In the third step, a biological neuron consists ofmultiple synapses and one activation unit. Similarto biological neurons, by applying the fracmemris-tor bridge synaptic circuit, the fracmemristor bridgeneuron circuit can be implemented (Fig. 3).

In Fig. 3, FM11, FM

12, A1

1, A12, A1

3, and A14 con-

struct the first fracmemristor bridge synaptic circuit.FMn

1 , FMn2 , An

1 , An2 , An

3 , and An4 construct the nth

fracmemristor bridge synaptic circuit, and the inte-grated operational amplifier An+1 achieves a cell biascircuit. vb(t) is a cell bias voltage (voltage sourcebiasing pulse), and iL(t) is the load current thatflows through rL. Thus, from Fig. 3 and Eq. (15),

rs

rs

v1in

i1in

rprp

i1in

FM11

FM12

A

B

v1A

v1B

vFM11

vFM21

A11

A12

+

+−

−

rt

rf

rt rf

A13

A14

r11r1

2

v13

i11

i1L

rL

Fig. 2 Fracmemristor bridge synaptic circuit

according to KCL, it can be written as

iiL(t) = ii1(t) =vi3(t)

ri1

=1

ri1

rfrt

[viB(t)− viA(t)

]=

rfri1rt

viout(t), (16)

inL(t) = in1 (t) =vn3 (t)

rn1

=1

rn1

rfrt

[vnB(t)− vnA(t)] =rf

rn1 rtvnout(t), (17)

in+1L = in+1

1 =vb(t)

rn+11

, (18)

where i ∈ [1, n] is a positive integer. From Fig. 3 andEqs. (15)–(18), it can be observed that the outputcurrents, weighted separately by each fracmemristorbridge synapse, are gathered to flow through the loadresistor rL. Therefore, it follows as

iL(t) =

n∑i=1

iiL(t) + in+1L (t), (19)

vout(t) = rLiL(t) = rL

(n∑

i=1

iiL(t) + in+1L (t)

). (20)

In the fourth step, a common architecture of bi-ological neural networks is simply the repeated con-nections of each neuron. Similar to biological neural

rs

rs

v1in rprp

FM11

FM12

A11

A12

A

B

v1A

v1B

rt

rt

rf

A13

A14

v13

i11

r11r1

2rf

vb

in+11

i1LinL

r n+11

in+1L

An+1 rL vout

+

−

r n+12

vnin

rs

rs

rprp

FMn1

FMn2

vnA

A

An1

An2

Bvn

B

rf

rt

rt rf

v n3

i n1

r n1r n

2

An3

An4

... iL

Fig. 3 Fracmemristor bridge neuron circuit


networks, by applying the fracmemristor bridge neu-ron circuit, the architecture of the fractional-ordermemristive neural networks circuit can be achieved(Fig. 4).

Fig. 4 illustrates that for the fractional-ordermemristive neural networks circuit, the output ofeach neuron is connected to another fracmemristorbridge neuron circuit. It is worth underlining thatin a fractional-order memristive neural network, allfracmemristor bridge synaptic circuits operate onlyduring the pulse width period of vb(t).

Neuron 1 ...

Neuron 2 ...

Neuron 3 ...

Fig. 4 Architecture of fractional-order memristiveneural networks circuit

4 Experimental tasks and analyses

In this section, electrical characteristics of thepulse-based fracmemristor and memristor bridge cir-cuit are compared. Then, different synaptic be-haviors such as short- and long-term memory, LTPand LTD, and non-associative learning are better ex-plained using the pulse-based fracmemristor bridgecircuit.

4.1 Electrical characteristics of pulse-basedfracmemristor bridge circuit

Electrical characteristics of a pulse-basedfracmemristor bridge circuit are compared and an-alyzed below.

In Fig. 1, a current-controlled capacitivefracmemristor is taken as an example to analyze theelectrical characteristics of a pulse-based fracmem-ristor bridge circuit. It is assumed that the in-put causal current across the memristor constitut-ing an incremental capacitive fracmemristor, whichis the same as the current across this incrementalcapacitive fracmemristor, is given over one period asfollows:

i1in(t) =v1in(t)

rs=

{A0, 0 < t ≤ T1,

0, T1 < t < T,(21)

where A0 is the amplitude of the pulse signal. Thisinput current is periodic with fundamental period T ,fundamental frequency f0 = 1/T , and fundamentalangular frequency w0 = 2π/T . Therefore, in thecase of small-signal behavior, from Eq. (21), the cor-responding Fourier transform will be

I1in (jw) = F{i1in(t)}

=

+∞∑k=−∞

2A0

ksin

(kw0T1

2

)e

−jwT12 δ(w − kw0),

(22)where δ(·) is the impulse function.

The quantity of electric charge across an incre-mental capacitive fracmemristor is equal to the one-order integral of the input current:

q(t) = I−1t i1in(t). (23)

Furthermore, from Eq. (21), the v-order frac-tional integral of i1in(t) can be derived as follows:

D−vt i1in(t) =

A0tv

Γ(1 + v)

+N∑

k=1

A0(−1)k(t− kT/2)v

Γ(1 + v)u

(t− kT

2

), (24)

where u(t) is the Heaviside function. In addition,it is assumed that the memristance of the positiveincremental memristor used in a positive incrementalcapacitive fracmemristor is given as

r[q(t)] = K1 +K2q(t), (25)

where K1 and K2 are constants. Thus, from Eqs. (3)and (25), the instantaneous input voltage of thismemristor can be derived as

vin(t) = r(q)i1in(t) = h(q) ∗ i1in(t), (26)


where vin is input causal voltage across the memris-tor, and r(q) = (h(q) ∗ i1in(t))/i

1in(t). It is assumed

that the initial value of electric charge of this mem-ristor is equal to zero. Then, the Fourier transformof Eq. (26) can be derived as follows:

Vin(jw) = H(jw)I1in(jw) ⇔ H(jw) =Vin(jw)

I1in(jw), (27)

where reactance of this memristor is equal toH(jw) = F{h(q)}. Substituting Eq. (27) into Eq. (4)with s = jw, the voltage-current relationship equa-tion of a v-order incremental capacitive fracmemris-tor can be expressed as

VFM1i(t) = c−vF−1{[H(jw)]1−p} ∗ [D−v

t i1in(t)], (28)

where F−1 is the inverse Fourier transform.There is a possibility to make the input current

be equal to Eq. (21) by choosing an appropriate volt-age source and resistance. We set the fundamentalfrequency f0 = 5 Hz, A0 = 10−5 A, rs = 1000 Ω,K1 = 2000, and K2 = 5× 107. The voltage of a half-order positive incremental capacitive fracmemristoris presented in Fig. 5.

When v = 0, then p = 0, and the positive incre-mental capacitive fracmemristor becomes a specialcase, which is a positive incremental memristor. Thevoltage of a positive incremental memristor is pre-sented in Fig. 6.

It is assumed that the memristance of the nega-tive incremental memristor used in a negative incre-mental capacitive fracmemristor is as follows:

r [q(t)] = K1 −K2q(t). (29)

Voltage(mV)

0 200 400 600 800 1000Time (ms)

Inputcurrent(μA)

30

20

10

0

−10

−20

−30

150

100

50

0

−50

−100

−150

Fig. 5 Voltage of a positive incremental capacitivefracmemristor of half-order. Red corresponds to theright vertical axis and blue corresponds to the leftvertical axis. References to color refer to the onlineversion of this figure

The voltages of a negative incremental capaci-tive fracmemristor of half-order and the negative in-cremental memristor can be gained in a similar way,as shown in Figs. 7 and 8, respectively.

Therefore, the output voltage of a pulse-basedfracmemristor bridge circuit can be obtained, whichis demonstrated in Fig. 9.

Similarly, the output voltage of a pulse-basedmemristor bridge circuit can be obtained as shownin Fig. 10.

The pulse-based memristor bridge circuit real-izes linear weighting on the input signal, whereasthe pulse-based fracmemristor bridge circuit yieldsnonlinear weighting operation, which is more appro-priate for explaining the neural synaptic weighting.In addition, circuit parameters can be adjusted to

Voltage(mV)

0 400 800 1200 1600 2000Time (ms)

Inputcurrent(μA)

30

20

10

0

−10

−20

−30

30

20

10

0

−10

−20

−30

Fig. 6 Voltage of a positive incremental memristorof half-order. Red corresponds to the right verticalaxis and blue corresponds to the left vertical axis.References to color refer to the online version of thisfigure

Voltage(mV)

0 200 400 600 800 1000Time (ms)

Inputcurrent(μA)

30

20

10

0

−10

−20

−30

150

100

50

0

−50

−100

−150

Fig. 7 Voltage of a negative incremental capacitivefracmemristor of half-order. Red corresponds to theright vertical axis and blue corresponds to the leftvertical axis. References to color refer to the onlineversion of this figure

870 Pu et al. / Front Inform Technol Electron Eng 2021 22(6):862-876Voltage(mV)

0 400 800 1200 1600 2000Time (ms)

Inputcurrent(μA)

30

20

10

0

−10

−20

−30

30

20

10

0

−10

−20

−30

Fig. 8 Voltage of a negative incremental memristorof half-order. Red corresponds to the right verticalaxis and blue corresponds to the left vertical axis.References to color refer to the online version of thisfigure

6

4

2

9×10−16

−2

−4

−6

Outputvoltage(mV)

0 200 400 600 800 1000Time (ms)

Inputvoltage(mV)

30

20

10

0

−10

−20

−30

Fig. 9 Output voltage of a pulse-based fracmemristorbridge circuit with v1

in(t) = 10 mV, rp = 1000 Ω, andrs = 1000 Ω. Red corresponds to the right verticalaxis and blue corresponds to the left vertical axis.References to color refer to the online version of thisfigure

change the outputs. For instance, when the resis-tance rs is reduced to 100 Ω, the current flowingthrough the fracmemristor increases, and the over-all output voltage of this pulse-based fracmemristorbridge circuit increases, as demonstrated in Fig. 11.

The output current of a fracmemristor bridgesynaptic circuit is equal to i1L(t) = rfv

1out(t)/(r

11rt),

and the output current wave is similar to the outputvoltage of the corresponding pulse-based fracmem-ristor bridge circuit.

4.2 Simulation of different synaptic behaviors

4.2.1 Short- and long-term memories

Different synaptic behaviors can be simulatedby changing amplitude A, width W , and time

300

200

100

0

−100

−200

−300

Outputvoltage(μV)

0 2 4 6 8Time (s)

Inputvoltage(mV)

30

20

10

0

−10

−20

−30

Fig. 10 Output voltage of a pulse-based memristorbridge circuit with v1

in(t) = 10 mV, rp = 1000 Ω, andrs = 1000 Ω. Red corresponds to the right verticalaxis and blue corresponds to the left vertical axis.References to color refer to the online version of thisfigure

15

10

5

0

−5

−10

−15

Outputvoltage(mV)

0 200 400 600 800 1000Time (ms)

Inputvoltage(mV)

30

20

10

0

−10

−20

−30

Fig. 11 Output voltage of a pulse-based fracmemris-tor bridge circuit with v1

in(t) = 10 mV, rp = 1000 Ω,and rs = 100 Ω. Red corresponds to the right verti-cal axis and blue corresponds to the left vertical axis.References to color refer to the online version of thisfigure

interval T of the input pulse (Fig. 12).Figs. 12a–12c show examples of A=10 mV,

W=2 ms, where time interval T is 198, 98, and 48 ms,respectively. After the first pulse input, the synapticweight reaches a certain value rapidly. However, be-fore the next pulse is input, the synaptic weight willspontaneously decay to a lower state exponentially.This phenomenon can be explained as the short-termplasticity behavior of synapses, similar to the short-term memory process of biological brains. For or-dinary people, if something is learnt once only, thatwill be forgotten soon, but a little impression will bekept. With continuous input of pulses, the synapticweight keeps increasing continually. Through con-tinuous learning, we are more impressed with that


10

8

6

4

2

0

Outputvoltage(mV)

0 200 400 600 800Time (ms)

Inputvoltage(mV)

20

16

12

8

4

0

(a)10

8

6

4

2

0

Outputvoltage(mV)

0 200 400 600 800Time (ms)

Inputvoltage(mV)

20

16

12

8

4

0

10

8

6

4

2

0

Outputvoltage(mV)

0 200 400 600 800Time (ms)

Inputvoltage(mV)

20

16

12

8

4

0

60

40

20

0

Outputvoltage(mV)

0 100 200 300 400Time (ms)

Inputvoltage(mV)

30

20

10

0

Outputvoltage(mV)

0 100 200 300 400Time (ms)

Inputvoltage(mV)

30

20

10

0

60

40

20

0

Outputvoltage(mV)

0 100 200 300 400Time (ms)

Inputvoltage(mV)

30

20

10

0

60

40

20

0

20

15

10

5

0

Outputvoltage(mV)

0 0.5 1.0 1.5 2.0Time (s)

Inputvoltage(mV)

30

25

20

15

10

5

0

20

15

10

5

0

Outputvoltage(mV)

0 0.5 1.0 1.5 2.0Time (s)

Inputvoltage(mV)

30

25

20

15

10

5

0

20

15

10

5

0

Outputvoltage(mV)

0 0.5 1.0 1.5 2.0Time (s)

Inputvoltage(mV)

30

25

20

15

10

5

0

(b) (c)

(d) (e) (f)

(g) (h) (i)

Fig. 12 Different synaptic behaviors with different amplitudes A, widths W , and time intervals T of the inputvoltage: (a) A =10 mV, W =2 ms, T =198 ms; (b) A =10 mV, W =2 ms, T =98 ms; (c) A =10 mV, W =2 ms,T =48 ms; (d) A =10 mV, W =10 ms, T =40 ms; (e) A =10 mV, W =36.67 ms, T =40 ms; (f) A =10 mV,W =60 ms, T =40 ms; (g) A =4 mV, W =2.5 ms, T =247.5 ms; (h) A =10 mV, W =2.5 ms, T =247.5 ms; (i)A =20 mV, W =2.5 ms, T =247.5 ms. Red corresponds to the right vertical axis and blue corresponds to theleft vertical axis. References to color refer to the online version of this figure

knowledge point. By decreasing the input pulse in-terval, decay time of synaptic weight decreases. Thehigher the frequency of stimulation, the more thesynaptic weight increases. After the last pulse in-puts, the synaptic weight is almost constant aftera certain period of decay. In the same period, if aknowledge point is reviewed multiple times, one willbe more impressed with that knowledge point. Mul-tiple reviews in the same period can lead to a transi-tion from short-term memory to long-term memory.

Figs. 12d–12f show examples of A=10 mV,T=40 ms, for various widths as 10, 36.67, and 60 ms.Since the decay time is the same, the synaptic weightincreases as the input pulse width increases. By in-creasing the input pulse width, the learning timebecomes longer. In the same period, increasing the

learning time can lead to a transition from short-term memory to long-term memory.

Figs. 12g–12i show examples of W=2.5 ms,T=247.5 ms, for various amplitudes as 4, 10, and20 mV. With the increase of input pulse amplitude,the synaptic weight increases. With the same du-ration and frequency, the synaptic weight increaseswith the increase of amplitude. Increasing the ampli-tude of the input pulse resembles the enhancementof learning intensity. In the same period, enhancingthe learning intensity can also lead to a transitionfrom short-term memory to long-term memory.

4.2.2 LTP and LTD

In neuroscience, LTP of synaptic transmissionwas discovered by Bliss and Lømo (1973) in the


dentate area of a rabbit. LTP describes the long-lasting increase of the synaptic weight. LTD, as theopposite of LTP, produces a long-lasting decrease inthe synaptic weight. As learning and memory are en-coded by modification of the synaptic weight, LTPand LTD are widely considered as two major cellularmechanisms that underlie learning and memory.

At present, many LTP studies conduct an in-vestigation to develop methods to enhance LTP toimprove learning and memory. In addition, LTP is asubject of clinical research, for example, in the areasof Alzheimer’s disease and addiction medicine. Theresults of this study prove that we can achieve thepurpose of LTP or LTD by means of the pulse-basedfracmemristor bridge circuit, as shown in Figs. 13and 14.

Applying a positive voltage pulse strengthensthe output voltage of a pulse-based fracmemristorbridge circuit gradually, which leads to the LTP ofthe synapse weight. On the other hand, a negativevoltage pulse input weakens the output voltage of thepulse-based fracmemristor bridge circuit gradually,which leads to the LTD of the synapse weight. Whenthe duty cycle of the input voltage pulse is equal to50%, the output voltage almost returns to its startingvalue after a period (Fig. 13). When the duty cycleof the input voltage pulse is equal to 70%, the overalloutput voltage increases (Fig. 14).

4.2.3 Habituation and sensitization

The pulse-based fracmemristor bridge synapticcircuit can unfold the non-associative learning pro-cesses well. One of the non-associative learning pro-cesses is habituation. When a harmless stimulus isrepeatedly applied to a person or an animal, thedegree of response is progressively weakened, as de-picted in Fig. 15.

Humans and animals can learn not to respondto many meaningless stimuli with the help of habit-uation. We may habituate to an environment withrepeated noises when we learn that these have noconsequences (Fennell, 2012). The Nobel laureateEric R. Kandel had observed that repeated stimuliof the siphon of a sea slug Aplysia led to progres-sively less contraction of the gill-withdrawal musclesand that the response was steadily weakening (Kan-del, 2007; Chua, 2013).

Another non-associative learning process is sen-sitization (Shettleworth, 2009). Sensitization often

is featured by an enhancement of response to a weakstimulus after an intense harmful stimulus, as pre-sented in Fig. 16. For example, humans usually feelnothing when touching the finger. However, afterour finger is hit with a hammer or pinched with aplier, the response of touching the finger is amplifiedbecause we feel the pain and become more sensitiveto touching the finger.

Sensitization helps humans and animals learn toavoid noxious stimuli. After weakening the responseby repeatedly touching the siphon of a sea slugAplysia, Eric R. Kandel and his colleagues employednoxious electrical stimuli to stimulate the siphon,which led the gill-withdrawal response to reappear.

15

10

5

0

−5

−10

−15

Outputvoltage(mV)

100 140 180 220 260 300Time (ms)

15

10

5

0

−5

−10

−15

Inputvoltage(mV)

Fig. 13 Output voltage of a pulse-based fracmem-ristor bridge circuit with the duty cycle of the inputvoltage pulse equal to 50%. Red corresponds to theright vertical axis and blue corresponds to the leftvertical axis. References to color refer to the onlineversion of this figure

20

10

0

−10

−20

Outputvoltage(mV)

100 150 200 250 300Time (ms)

15

10

5

0

−5

−10

−15

Inputvoltage(mV)

Fig. 14 Output voltage of a pulse-based fracmem-ristor bridge circuit with the duty cycle of the inputvoltage pulse equal to 70%. Red corresponds to theright vertical axis and blue corresponds to the leftvertical axis. References to color refer to the onlineversion of this figure


3

2

1

0

Outputvoltage(mV)

0 10 20 30 40Time (ms)

Inputvoltage(mV)

3

2

1

0

Fig. 15 Habituation explained by the pulse-basedfracmemristor bridge circuit. Red corresponds to theright vertical axis and blue corresponds to the leftvertical axis. References to color refer to the onlineversion of this figure

10

5

0

Outputvoltage(mV)

0 4 8 12Time (ms)

Inputvoltage(mV)

20

15

10

5

0

Fig. 16 Sensitization explained by the pulse-basedfracmemristor bridge circuit. Red corresponds to theright vertical axis and blue corresponds to the leftvertical axis. References to color refer to the onlineversion of this figure

After this sensitization, a light touch to the siphonproduced a strong gill-withdrawal response and thistype of phenomenon lasted several days (Squire andKandel, 2003).

4.2.4 Neural signals

For a pulse-based fracmemristor bridge circuit,the fundamental frequency of the input voltage canbe altered to produce what is needed. For instance,when the fundamental frequency is f0 = 40 Hz, inthe positive voltage pulse interval, the output volt-age of the pulse-based fracmemristor bridge circuitis demonstrated in Fig. 17, which can be applied toexplain the action potential of a neuron.

According to Fig. 17, when the input voltage isequal to zero, namely, there is no input voltage, the

600

400

200

0

−200

−400

−600

Outputvoltage(μV)

200 250 300 350 400Time (ms)

Inputvoltage(mV)

30

20

10

0

−10

−20

−30

Fig. 17 Output voltage of a pulse-based fracmem-ristor bridge circuit with the fundamental frequencyf0 = 40 Hz. Red corresponds to the right verticalaxis and blue corresponds to the left vertical axis.References to color refer to the online version of thisfigure

output voltage gradually decreases but cannot decayto zero. For a stable system, its response approachesa steady state eventually. Thus, it is reasonable forthe output voltage of the pulse-based fracmemristorbridge circuit to reach a steady state without in-put voltage, which also proves that this circuit hasmemory.

5 Conclusions

In this study, the FMNSW using a pulse-basedfracmemristor bridge circuit was investigated anddiscussed in detail. Electrical characteristics of apulse-based fracmemristor bridge circuit can be usedto explain the cellular mechanisms that underlielearning and memory such as LTP, LTD, habitua-tion, and sensitization. This application is consid-ered as a major advantage.

In addition, pulse-based fracmemristor bridgecircuit could be employed to produce an appropri-ate signal for the brain-computer interface, which issuperior to the traditional integer-order memristiveneural synaptic weightings. It is difficult for patientswith diseases such as paraplegia and myasthenia tomove and communicate. Specific brain neural signalscan be produced by the pulse-based fracmemristorbridge circuit to control the body of the patient tohelp move or communicate like a healthy person. Asthe signal produced by the pulse-based fracmemris-tor bridge circuit is very similar to the brain neuralsignal, this kind of control conforms very well to thenatural physiology.


The study is a preliminary work on the appli-cation of fracmemristor in fractional-order memris-tive synapses. Solving other related problems willbe the topic for future studies. For instance, thisresearch discussed solely the half-order pulse-basedfracmemristor bridge circuit. Therefore, arbitrary-order pulse-based fracmemristor bridge circuits andinvestigating ways to use arbitrary-order pulse-basedfracmemristor bridge circuits to describe synapticbehaviors need to be analyzed in future work.

ContributorsYifei PU designed the research. Bo YU and Qiuyan HE

processed the data. Yifei PU and Qiuyan HE drafted the

manuscript. Bo YU and Xiao YUAN helped organize the

manuscript. Yifei PU, Bo YU, Qiuyan HE, and Xiao YUAN

revised and finalized the paper.

Compliance with ethics guidelinesYifei PU, Bo YU, Qiuyan HE, and Xiao YUAN declare

that they have no conflict of interest.

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