Frank Lehner U Zurich Characterization of inner layer sensors DØ Inner Layer Sensor Production Readiness Review FNAL, 8/8/2003 M. Demarteau, R. Demina,

Frank LehnerU Zurich

DD Characterization of inner layer sensors

DØ Inner Layer Sensor Production Readiness Review

FNAL, 8/8/2003

M. Demarteau, R. Demina, S. Korjenevski, F. Lehner, R. Lipton, H.S. Mao, B. McCarthy, R. Smith


DD L0/L1 Sensor Layout

p+n single-sided on 6’’ wafer

AC coupling, polysilicon biased, single guard

Radiation hard Layer 0: ~1.2·1013 1

MeV n/cm2/fb-1

Readout strips L0: 256 R/O strips w/

intermediate traces and 25 m pitch

L1: 384 R/O strips w/ intermediate traces and 29 m pitch


DD L0/L1 Sensor Specs

overview of sensor specifications

Specification L0 L1

Wafer 320±20m,warp<50m

320±20m,warp<50m

Depletion Voltage 40< Udep<300 V 40< Udep<300 V

Leakage Current <100nA/cm2 <100nA/cm2

Junction Breakdown

>700V >700V

Implant width 6m 7m

Aluminum resistance

< 30 /cm < 30 /cm

Coupling Capacitance

>10 pF/cm > 10 pF/cm

CC breakdown >100V >100V

Interstrip cap <1.2 pF/cm <1.2 pF/cm

R Polysilicon 0.8 ± 0.3 M 0.8 ± 0.3 M

Active length (mm)

77.360 77.360

Active width (mm) 12.800 22.272

Cut length (mm) 79.400 79.400

Cut width (mm) 14.840 24.312

R/O (strip) pitch 50 (25) 58 (29)

Defective strips <1% <1%


DD HPK wafer layout for L0/L1

HPK 6’’-wafer layout

4 sensors/wafers for L1

4 test structures on wafer

receive one “half moon” adjacent to long side of sensor

test structure used for evaluation and cross checks of electrical properties


DD HPK layer 1 production

Procurement strategy: ordered only layer 1 prototypes for qualification layer 0 very similar, but detailed drawings were not ready

so early due to complicated layout w/ analog cable 10 prototypes for layer 1 ordered in April 2002,

shipped to FNAL in Sept 2002 extensively tested 3 of them irradiated

3 more prototypes ordered in May 2003, shipped to FNAL in July 2003

testing results included in PRR document/talk rough estimate of “yield”, based on serial

numbering ~54%, lower than for outer layer sensors (~70%)

HPK QA: 2 (out of 13) had one defect, 1 (out of 13) had two defects


DD Layer 1 – Testing Results

Outline: test structure measurements

Coupling Capacitors and CC breakdown Resistances Strip capacitances MOS flatband

layer 1 sensors depletion voltages Leakage currents Capacitances Resistances defect channels


DD Layer 1 test structure – Coupling Capacitors

test structure for CC w/ exact same length than real strips

“real” capacitance value extracted at low frequency limit due to low-pass filter

115 pF or 14.8 pF/cm - within specs CC breakdown ~220V CC breakdown on “baby” detector

>170V

Coupling Capacitor L1 teststructure

0

20

40

60

80

100

120

0.1 1 10 100 1000 10000

Frequency (kHz)

C (

pF

)

CC1

CC2

CC3

CC4

Coupling Capacitor Breakdown

-5000

-4000

-3000

-2000

-1000

0

1000

0 50 100 150 200 250 300Voltage (V)

I (n

A)

CC1

CC2

CC3


DD Layer 1 test structure – implant and aluminum resistance

implant resistance on two different test

structures (e.g. N-LW20)

130 K/cm Al resistance

meander like trace ~35 /cm

on “baby” detector ~22.1 /cm (within specs)

p-implantR=2605 Ohm, length=0.02 cm

R/cm=130kOhm/cm

-3.E-04

-2.E-04

-1.E-04

0.E+00

1.E-04

2.E-04

3.E-04

-0.60 -0.40 -0.20 0.00 0.20 0.40 0.60

U (V)

I (A

)

Aluminium Trace LW6000

-3.E-04

-2.E-04

-1.E-04

0.E+00

1.E-04

2.E-04

3.E-04

-0.06 -0.04 -0.02 0.00 0.02 0.04 0.06

U (V)

I (A

)


DD Layer 1 test structure – polysilicon resistance R_poly

measured on baby detector as well as on polysilicon resistor arrays

measurement on intermediate strips provide directly value for R_poly, R/O strips give R_poly+R_implant

R_poly: 0.7 ± 0.1 M

Rpoly on baby sensor

-1.5E-05

-1.0E-05

-5.0E-06

0.0E+00

5.0E-06

1.0E-05

1.5E-05

-5 -4 -3 -2 -1 0 1 2 3 4 5U (V)

I (A

)

strip 1

strip 2

strip 3

strip 4

PSn30

-6.00E-06-4.00E-06-2.00E-060.00E+002.00E-064.00E-066.00E-068.00E-06

-5 -4 -3 -2 -1 0 1 2 3 4 5

U (V)

I (A

)

PS30_1

PS30_3

PSH30_1

PSH30_2

PSH30_3

PSH30_long_1

PSH30_long_3

PSH30_long_5


DD Layer 1 test structure – strip capacitance

total (load) strip capacitance measured on baby detector (7 R/O strips over full length)

total (load) capacitance includes both neighbors and the backplane

important to understand since noise in preamp depends on capacitive load

determined to be 1.1 pF/cm at 1 MHz (the relevant frequency for SVX4)

capacitance value is constant already at a bias of 10 V

Total strip capacitance (pF)

0

2

4

6

8

10

1 10 100 1000Frequency (kHz)

CL (

pF

)Total strip capacitance

0

5

10

15

20

0 30 60 90 120bias (V)

CL (

pF

)

1kHz

2kHz

5kHz

10kHz

20kHz

50kHz

100kHz

200kHz

500kHz

1MHz


DD Layer 1 test structure – interstrip capacitance

largest contribution to total strip capacitance for fine pitch detectors is from R/O strip neighbors

measured on baby detector (at 1 MHz):

0.39 pF/cm to one neighbor

0.79 pF/cm to both neighbors

our spec calls for <1.2 pF/cm for both neighbors

Interstrip capacitance

01234567

1 10 100 1000

Frequency (kHz)

Cin

t (p

F)

Cint both

Cint both

Cint one neighbor


DD Layer 1 test structure – MOS flatband

test structures have a 0.5 mm2 pMOS (metal/oxide/silicon)

have measured the CV characteristics to determine the flatband

CV curve looks like expected for MOS-capacitors

large positive gate Voltage: accumulation region, majority carriers (n) accumulate under gate

negative gate voltage: inversion region, minority carriers invert the region at interface

transition happens at ~-2V (ideally at 0V)

fixed oxide charge shifts the flatband by V=Q/C => Q<10-11 1/cm2

small amount of oxide charge

MOS-FI structure

0

5

10

15

20

25

30

35

-15 -10 -5 0 5 10 15 20

gate voltage (V)

cap

acita

nce

(pF

)

L2-63/64

L2-62

L1-6/7


DD Layer 1 silicon sensors

Measurements on all 13 L1 sensors I-V Leakage current

stability over longer times

C-V AC-scans DC-scans interstrip capacitances

and resistances


DD Layer 1 silicon sensors – leakage currents

measured leakage current at probe sites

all sensors (except one) have less than 80nA at U=800V

sensors have very low current densities of ~0.5 nA/cm2

no sensor showed breakdown

difference to HPK measurements less than 35nA

Nota bene: HPK uses 25±1ºC, we measure at 20±1ºC

T may cause up to 50% current change

L1 sensors - IV

0

50

100

150

200

250

300

0 100 200 300 400 500 600 700 800

bias (V)

I (n

A)

L1-1

L1-3

L1-4

L1-6

L1-7

L1-9

L1-11

L1-12

L1-13

L1-20

L1-21

L1-22

L1-24

HPK - Our Measurement

-150

-100

-50

0

50

100

150

200

0 100 200 300 400 500 600 700 800

Bias Voltage (V)

I

(nA

)

1

3

4

6

7

9

11

12

13

20

21

22

24


DD Layer 1 silicon sensors – leakage current stability

setup at FNAL allows long term biasing of up to 7 ladders with current, temp & humidity monitoring

sensors kept for 96h at various N2 flow rates at bias voltage of 300V

no runaway or long term drift is observed

currents drop in beginning follows dew point decrease

stability test will be part of QA program for sample of sensors

Long Term Stability Layer 1 sensors at Vbias = 300 V

10

100

1000

10000

0.0E+00 5.0E+04 1.0E+05 1.5E+05 2.0E+05 2.5E+05 3.0E+05 3.5E+05

Elapsed Time (s)

I (n

A)

L1-09

L1-03

L1-07

L1-04

-50

-40

-30

-20

-10

0

10

20

30

0.0E+00 5.0E+04 1.0E+05 1.5E+05 2.0E+05 2.5E+05 3.0E+05 3.5E+05

Elapsed Time (s)

T (

0 C)

Temp

Dew Point


DD Layer 1 silicon sensors – depletion voltage

FDV from 1/C2 vs bias

have used so far for L1 sensors “straight line” fits

HPK uses 2%-rule: FDV is taken at the

lowest voltage point where change in 1/C2 is less than 2%

correlation between us and HPK

2% rule estimates FDV systematically ~20V higher

we will adopt 2% rule at our probing sites

also requested to HPK to send us “raw capacitance” values to cross check our results

C - 2 vs Voltage

0

500

1000

1500

2000

2500

3000

0 50 100 150 200 250 300

Bias Voltage (V)1/

C2 (

1/p

F)2

* 1

E9

L1_001

L1_003

L1_004

L1_006

L1_007

L1_009

L1_011

L1_012

L1_013

L1_020

L1_021

L1_022

L1_024

Vdepl=105-130V

90

100

110

120

130

140

150

160

90 100 110 120 130

Depletion Voltage CV Scan (V)

De

ple

tio

n V

olt

ag

e H

PK

(V

)


DD Layer 1 silicon sensors – AC scan

We performed AC scans on all 13 L1 sensors

LCR frequency 10-100 kHz

measure dielectric currents through capacitor up to 80V

dielectric currents < 100pA

in total found 4 pinholes and two opens out of 13 sensors

Idielec, Layer 1, Sensor 13

0

20

40

60

80

100

120

140

160

180

200

0.051 0.056 0.061 0.066 0.071 0.076 0.081 0.086 0.091 0.096 0.101 0.106 0.111 0.116

Idiel (nA)

Nu

mb

er o

f st

rip

s

AC Scan, Layer 1, Sensor 13

0

10

20

30

40

50

60

70

80

0 50 100 150 200 250 300 350

Strip Number

Cc

(pF

)


DD Layer 1 silicon sensors – DC scan

performed DC scan on strips

average leakage current/strip is 40pA

no leaky strips (>10nA) observed

use also DC scan to measure poly resistors

“intermediate” strips give value for R_poly

R/O strips give series of R_poly and R_implant

both values are consistent with test structure measurements

interstrip resistance on sensors evaluated – found to be O(G)

Ileak for all 10 Layer 1 sensors

0

200

400

600

800

1000

1200

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09 0.

1

0.11

0.12

0.13

0.14

0.15

0.16

0.17

0.18

0.19 0.

2

0.21

0.22

0.23

0.24

0.25

0.26

0.27

1 3

I leak/strip (nA)

Nu

mb

er

of

Str

ips Average leakage per strip is 0.04 nA

14 strips leakage at 1 nA

Polysilicon Resistor, Layer 1, Sensor 13

0

50

100

150

200

250

300

350

400

600 650 700 750 800 850 900 950 1000 1050 1100 More

Rpoly (kOhm)

Nu

mb

er o

f st

rip

s


DD Layer 1 silicon sensors – total strip capacitance

total (load) strip capacitance on L1 sensors

measured extensively on few sensors – all in agreement

total strip capacitance with respect to two neighbor R/O strips and to the backplane

at 1 MHz, the relevant capacitance is 1.1 pF/cm

in agreement to test structures

bias dependence capacitance at certain

frequency does not change above 20V bias

interstrip capacitance (to one neighbor)

determined to be 0.4 pF/cm in agreement to test

structures

Total Load Capacitance at various Vbias

0

2

4

6

8

10

12

100 1000 10000 100000 1000000Frequency (Hz)

CL (

pF

)

5v

10v

20v

30v

40v

50v

60v

70v

80v

90v

100v

110v

120v

130v

Interstrip Capacitance

0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50

1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06

Frequency (Hz)

Ci (

pF

)Ci-Ch193

Ci-Ch194


DD Layer 1 silicon sensors – overview of sensor probing

we verified in AC & DC scans that 10 out of 13 sensors had no single strip defect

we confirmed the HPK findings of in total four bad strips on three sensors

in addition, we found two bad strips on one sensor

defect rate is at the 1‰ level!


DD Layer 1 silicon sensors – mechanical measurements

measured all ten L1 sensors from Sept 2002 on optical metrology machine (OGP at FNAL)

verified mechanical dimensions of sensor to within 4 µm, cut edges extremely accurate

grid of 11 x 11 on sensor to determine flatness

average flatness for 10 sensors is 45 µm

maximum warp on sensor L1-3 is 48 µm

spec calls for 50 µm “on a best effort basis”, will reject sensors with flatness of more than 100 µm

-0 . 0 2

-0 . 0 1

0 .0 0

0 .0 1

0 . 0 2

0 .0 3

0 . 0 4

0

2 0

4 0

6 0

8 0

1 0 0

- 3 0- 2 5

- 2 0- 1 5

- 1 0- 5

0

Z D

ata

X D

ata

Y D a ta

3 D G r a p h L 1 - 0 1 s e n s o r

C o l 1 vs C o l 2 vs C o l 3

(Zmax-Zmin) distribution for 10 sensors

39

40

41

42

43

44

45

46

47

48

49

1 2 3 4 5 6 7 8 9 10Sensor #

Zm

ax

(

m)


DD Layer 2 silicon sensors – visual inspection

setup inspection station and trained technician to perform visual inspections on all new incoming sensors

check sensor edges and sides for chips/cracks

check pad cleanness look for major scratches on sensor

surface inspection time: 20-25’ per sensor,

guidelines for visual inspection exists visual inspection important part of key

test program first results on ~25 scanned L2 sensors

chips about 50% of sensors have small, and

unproblematic chips at edges up to 30 m in size

very few (2-3) have chips extending about 50 m inward

one sensor so far found with extreme damage

scratches only one major scratch deeper scratch on traces will flag sensor for

electrical (strip) tests


DD Layer 2 silicon sensors – visual inspection

cleanness: sensors rather clean

compared to Run IIa experience

several kinds of organic residue/photoresist on sensor

pads are clean and surface finish looks OK

few sensors have fiducials scratched

grading developed criteria for grading

from visual inspection: good, medium and poor

poor does not necessarily mean reject but increased attention in upcoming tests (electrical tests)


DD Layer 1 silicon sensors – summary

presented results on electrical testing on test structures and L1 silicon sensor

all important electrical parameters have been measured on both, test structures and sensors

all values are found to be consistent and in agreement with our specs

overall number of strip defects is extremely low: 1‰ (require: <1%)

good agreement between HPK and our results

mechanical results show excellent quality of cutting edge and low sensor warp

sensors are of exquisite quality in all aspects

Looking forward to probe them …

Documents

Frank Lehner U Zurich Characterization of inner layer sensors DØ Inner Layer Sensor Production Readiness Review FNAL, 8/8/2003 M. Demarteau, R. Demina,