Freescale Semiconductor, Inc. · Chip Errata DSP56306 Digital Signal Processor Mask: 0J27A Motorola SPS 306CE0J27A_2_0 pg. 1 /ng/7/17/00 6501 William Cannon Drive West, Austin, Texas

Chip ErrataDSP56306 Digital Signal Processor

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Freescale Semiconductor, Inc.n

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General remark: In order to prevent the usage of instructions or sequence of instructions that do not operate correctly, the user is encouraged to use the “lint563” program to identify such cases and use alternative sequences of instructions.This program is available as part of the Motorola DSP Tools CLAS package.

Silicon Errata

Errata Number Errata Description

Appliesto Mask

ES30

Description (added 9/3/1997):

After the BB pin output is driven high and released, the pin output voltage level may not reach VCC. The issue depends on the application board layout and the parameters of the chip process.

Workaround:

Use a restricted board layout that includes a 1 kΩ pull-up resistor connected to the BB pin with a 100 Ω resistor connected in series with, and as close as possible to, the pin. The board route from the BB pin to any component should guarantee the following parameters:

a. Route inductance < 40 nH

b. Route capacitance < 15 pF

c. Input capacitance < 8 pF

Such restrictions guarantee that when BB is driven high (deasserted), the output voltage level will be above 2.25 V at VCC = 3.3 V.

0J27A

ES33


When using the JTAG instructions SAMPLE/PRELOAD, EXTEST, and CLAMP, erroneous data may be driven out on the parallel pins and TDO. Data cannot be shifted through the Boundary Scan Register (BSR) using the SAMPLE/PRELOAD instruction. Because the BSR must be preloaded using the SAMPLE/PRELOAD instruction, the EXTEST and CLAMP instructions cannot be used for testing the board connections.

Workaround:

None available.

0J27A

Motorola SPS 306CE0J27A_2_0 pg. 1 /ng/7/17/006501 William Cannon Drive West, Austin, Texas 78735-8598 1997–1999 Motorola

For More Information On This Product,

Go to: www.freescale.com


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ES46


When a DMA controller is in a mode that clears DE (i.e., TM = 0xx), if the core performs an external access with wait states or there is a transfer stall (see Appendix B, Section B.3.4.2 in the DSP56300 Family Manual) or a conditional transfer interlock (see Appendix B, Section B.3.5.1) during the last DMA channel transfer, there will be one additional DMA word transfer.

Workaround:

There are three system-dependent workarounds for this problem. The user should test the system using these workarounds to determine which one to use in the particular system to overcome this problem. The workarounds are:

Workaround 1:

a. Prepare one additional memory word in the source and destinations buffers. This data should be ignored.

b. Activate a DMA Interrupt Service Routine (ISR) or poll the DTD bit to ensure block transfer completeness. In the DMA ISR or the handler routine after status polling, reload the values of the address registers.

Workaround 2:

a. Use a DMA mode that does not clear DE (i.e., TM = 1xx) and activate the DMA interrupt.

b. In the ISR, execute the following operations in the order listed: clear DE, update the address registers, and set DE.

Workaround3:

a. Use a DMA mode that does not clear DE (i.e., TM = 1xx).

b. Change the address mode from linear addressing to 2D or from 2D to 3D and use an offset register to update the address automatically at the end of the block.

Note: If the user can not use one of these workarounds, there may be oth-er possible system-dependent workarounds.

0J27A


Appliesto Mask

DSP56306 Errata 306CE0J27A_2_0 pg. 2 /ng/7/17/00 1997–1999 Motorola




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ES47


If the DMA channel and the core access the same 1/4 K internal X data, Y data, or program memory page, and the DMA interrupt is enabled, a false interrupt may occur in addition to the correct one.

Workaround:

Ensure that the channel’s DTD status bit in the DSTR is set before jumping to the Interrupt Service Routine (i.e., the interrupt is correct only when DTD is set).

Example:

ORG P:I_DMA0JSSET #M_DTD0,X:M_DSTR,ISR_ ; ISR_ is the Interrupt

Service ; Routine label for DMA

channel 0

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ES48


Note: This is a subset of Errata #46 (i.e., in every case that errata #48 oc-curs, errata #46 occurs, but not vice versa).

When a DMA controller is in a mode that clears DE (i.e., TM = 0xx), and it transfers data to an external memory with two or more wait states, and the DSP core performs an external access with wait states or there is a transfer stall (see Appendix B, Section B.3.4.2 in the DSP56300 Family Manual) or a conditional transfer interlock (see Appendix B, Section B.3.5.1) during the last DMA channel transfer, the destination pointer for a subsequent DMA transfer may not be reprogrammed correctly. There are two defined workarounds to prevent the occurrence of this condition and one recovery code that should be used if the workarounds can not be used in a specific system:

Workaround 1:

a. Use a DMA mode that does not clear DE (i.e., TM = 1xx) and activate the DMA interrupt.

b. In the DMA ISR, clear DE, update the address registers, and set DE.

Workaround 2:

a. Use a DMA mode that does not clear DE (i.e., TM = 1xx).

b. Change the address mode from linear addressing to 2D or 2D to 3D and use an offset register to update the address automatically at the end of the block.

Recovery (to recover if the condition occurs):

a. Enable the DMA interrupt.

b. Use the following code in the DMA ISR:

movep #dummy_source, x:M_DSRimovep #dummy_dest, x:M_DDRimovep #0, x:M_DEOimovep #9E0240, x:M_DCRi ; initiate one dummy

transfer; if the bug

occurred, the; transfer will be to

the;

old_block_last_dest + 1

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Appliesto Mask


; and not to the dummy_dest

nop




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ES53


Using the JTAG instruction code 1111 ($F) or 1101 ($D) for the BYPASS instruction may cause the chip to enter Debug mode (which then correctly sets the Status bits (OS[1:0]) in the OnCE Status and Control Register (OSCR[7:6]) and asserts the DE output to acknowledge the Debug mode status).

Workaround:

Use one of the following alternatives:

a. If possible, do not use instruction code 1111 ($F) or 1101 ($D) for the BYPASS instruction. Use one of the other defined BYPASS instruction codes (i.e., any code from 1000–1100 ($8–$C) or 1110 ($E)).

b. If you must use instruction code 1111 ($F) or 1101 ($D), use the following procedure:

— While the $F or $D instruction code is in the Instruction Register, ensure that the JTAG Test Access Port (TAP) state machine does not pass through the JTAG Test-Logic-Reset state while accessing any JTAG registers (i.e., Instruction Register, Boundary Scan Register, or ID Register).— Before using any other JTAG instruction, load one of the other BYPASS instruction codes (i.e., any code from 1000–1100 ($8–$C) or 1110 ($E)) into the instruction register. Then, any other JTAG instruction may be used.

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ES54


When a DMA channel is configured using its DMA Control Register (DCR) in the following manner:

• Line Transfer mode is selected (DTM[2:0] = 010) • Non-Three-Dimensional Address mode is selected (D3D = 0) • Destination Address Offset Register DOR1 or DOR3 is selected

(DAM[5:3] = 001 or 011) • No Source Address Offset is selected (DAM[2:0] = 100 or 101)

The DMA transfer does not function as intended.

Workaround:

Select Destination Address Offset Register DOR0 or DOR2 by setting DAM[5:3] = 000 or 010.

0J27A

ES88

Description (added 6/4/98)

The OnCE port is functionally tested using a voltage supply range of 2.7 V to 3.4 V. within the temperature range of 25c to 100c and are guaranteed by test to be fully operational under these conditions. This is a change from the voltage levels specified in the 56306 Technical Data sheet. Above a voltage level of 3.4 V, the OnCE port is not guaranteed to function properly.

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ES89


If the SCI Receiver is programmed to work with a different serial clock than the SCI Transmitter so that either the Receiver or Transmitter is using the external serial clock and the other is using the internally-generated serial clock—RCM and TCM in the SCCR are programmed differently)—then the internal serial clock generator will not operate and the SCI portion (Receiver or Transmitter) clocked by the internal clock will be stuck.

Workaround:

Do not use SCI with the two SCI portions (Receiver and Transmitter) clocked by different serial clocks; use either both externally or both internally clocked.

Or:

When using both portions of the SCI (Receiver & Transmitter), do not program different values on RCM and TCM in the SCCR.

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ES90

Description (added 6/25/98)

A deadlock occurs during DMA transfers if all the following conditions exist:

1. DMA transfers data between internal memory and external memory through port A.

2. DMA and the core access the same internal 0.25K memory module.

3. The bus arbitration system is active, i.e. BG is changing, not tied to ground.

The symptom is a deadlock on DMA activity, i.e. a DMA transfer stops for no apparent reason. BR is not asserted when it should be asserted because of DMA.

Workaround:

One of the following:

1. Use intermediate internal memory on which there is no contention with the core.

2. Tie BG to ground, or have an external arbiter that asserts BG even if BR is not asserted by onyx.

3. Make core priority higher than the DMA in port A, and do a periodic external access by the core. The core access should solve the deadlock.

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ES91


If the Core reads data from the HRX while instructions are fetched from the memory Expansion Port (Port A) using 2 or more wait states, data may be lost.

Workaround :

There are three possible workarounds:

1) The host should guarantee that there is no more than one word in the TXH:TXM:TXL-HRX data path at any time. This can be achieved if the host writes a word to the HI08 only when the TRDY flag is set (i.e. the data path is empty).

2) Use a service routine running from fast (i.e. one wait state) external memory or internal memory to read the HRX read code; ensure that code that is fetched from slow (i.e. more than 1 wait state) external memory is located at least 4 instructions after the HRX register is read. For example:

READ_HRX_DATANOP NOP NOP NOP

Note:

a) Interrupt requests that fetch instructions from slow external memory should be masked during this service routine. Nonmaskable interrupt (NMI) request routines must not be in external memory.

b) If running from fast external memory and if a DMA channel accessing external memory is used, then the DMA may cause extra wait states to the core. Thus, the DMA should have a lower priority than the core so that the core can access the external memory with no more than 1 wait state.

3) Read the HRX using one of the channels of the on-chip DMA controller.

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ES95

If more than a single DMA channel is enabled while the DSP stays in the WAIT processing state, and triggering one of the DMA channels causes an exit from the WAIT state (See A-6.115, UM), triggering another DMA channel might cause improper DMA operation.

Workaround:

Assure that only a single DMA channel can be triggered during DSP WAIT state. If the application cannot guarantee this, other DMA channels should be disabled before the WAIT processing state is entered and then reenabled after WAIT state is exited.

0J27A

ES104


An improper operation may occur when a DMA channel uses the following transfer modes:

• DTM(2:0) = 100

• DTM(2:0) = 101

where the DE bit is not automatically cleared at the end of block and the DMA channel is disabled by software (DE bit is cleared) while it is triggered for a new transfer.

Workaround:

The DMA channel should be disabled only when it cannot be triggered by a new transfer. Use one of the following alternatives:

1. The system configuration must guarantee that no DMA trigger can occur while the DE bit is cleared.

2.The following sequence disables the DMA channel:

a/ Wait until the DTD bit is clearedb/ Clear the DE bitc/ Wait until the DTD bit is set

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ES114


A DMA channel may operate improperly when the address mode of this channel is defined as three-dimensional (D3D=1) and DAM[5:0] = 1xx 1 10 or DAM[5:0] = 01x1 10 (i.e., triple counter mode is E).

Workaround:

Use the triple counter modes C(DAM[1:0]=00) or D(DAM[1:0]=01) instead of the E(DAM[1:0]=10) mode.

0J27A

ES115


When a DMA channel (called channel A) is disabled by software clearing the channel’s DCR[DE] bit, the DTD bit may not get set, and the DMA end of the block interrupt may not happen if one of the following occurs:

1. There is another channel (channel B) executing EXTERNAL accesses, and the DE bit of channel A is being cleared by software at the end of the channel B word transfer - if channel B is in Word transfer mode, or at the end of the channel B line transfer - if channel B is in Line Transfer mode, or at the end of the channel B block transfer - if channel B is in Block transfer mode.

2. This channel (A) is executing EXTERNAL accesses, and the DE bit of this channel (A) is being cleared by software at the end of the channel B word transfer - if channel B is in Word transfer mode, or at the end of the channel B line transfer - if channel B is in Line transfer mode.

Workaround:

Avoid executing a DMA external access when any DMA channel should be disabled. This can be done as follows. Every time the DMA channel needs to be disabled by software, the following sequence must be used:

;; initialize an unused DMA channel "C"movep #DSR_swflag, x:M_DSRC ;; here DSR_swflag is an

;; unused X, Y or P memory;; location, should;; be initialized to;; $800000;; M_DSRC - address of the;; channel C DSR register.

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ES115 cont.

movep #DDR_swflag, x:M_DDRC ;; DDR_swflag is an unused;; X, Y or P memory;; location, should be;; initialized to $000000;; M_DDRC -;; address of the channel C;; DDR register .

movep #TR_LENGTH, x:M_DCOC ;; see below the definition;; of the TR_LENGTH value,;; M_DCOC - address;; of the channel C DCO

register .movep #1f0240, x:M_DCRC ;; M_DCRB - address of the;; channel C DCR register.;; Set transfer mode -;; block transfer,;; triggered by;; software highest ;; priority, continuous;; mode on no-update;; source and destination;; address mode X memory;; location for source;; and destination (can be;; chosen by;; user accordingly to;; DSR_swflag/DDR_swflag)

0J27A

ES115 cont.

;; disable DMA channel "A"

ori #3, mr ;; mask all interruptsbset #23, x:M_DCRC ;; enable DMA channel Cbclr #23,x:DDR_swflag,* ;; wait until DMA channel C

;; begin transfer

bclr #23, x:M_DCRA ;; disable DMA channel Anopnopjclr #M_DTDA, x:M_DSTR,* ;; polling DTD bit of the DMA

;; channel A,

The TR_LENGTH value can be defined as the maximum length of the external DMA transfer——from the length of the read DMA cycle and from the length of the write DMA cycle. The length of the external read/write DMA cycle can be defined as the length of the PORTA external access. The length of the internal read/write DMA cycle can be defined in the errata case as 2 DSP clock cycles. The TR_LENGTH can be found as sum of the lengths of the DMA read and DMA write cycles.

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Documentation Errata


Appliesto Mask

ED1

Description (revised 11/9/98):

XY memory data move does not work properly under one of the following two situations:

1. The X-memory move destination is internal I/O and the Y-memory move source is a register used as destination in the previous adjacent move from non Y-memory

2. The Y-memory move destination is a register used as source in the next adjacent move to non Y-memory.

Here are examples of the two cases (where x:(r1) is a peripheral):

Example 1:

move #$12,y0 move x0,x:(r7) y0,y:(r3) (while x:(r7) is a peripheral).

Example 2:

mac x1,y0,a x1,x:(r1)+ y:(r6)+,y0move y0,y1

Any of the following alternatives can be used:

a. Separate these two consecutive moves by any other instruction.

b. Split XY Data Move to two moves.

Pertains to: DSP56300 Family Manual, Section B-5 "Peripheral pipeline restrictions.

0J27A

ED3


A one-word conditional branch instruction at LA-1 is not allowed.

Pertains to: DSP56300 Family Manual, Appendix B, Section B.4.1.3

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ED4


The following instructions should not start at address LA:

MOVE to/from Program space MOVEM, MOVEP (only the P space options)

This is not a bug but a documentation update (Appendix B, DSP56300 Family Manual).

0J27A

ED7


When activity is passed from one DMA channel to another and the DMA interface accesses external memory (which requires one or more wait states), the DACT and DCH status bits in the DMA Status Register (DSTR) may indicate improper activity status for DMA Channel 0 (DACT = 1 and DCH[2:0] = 000).

Workaround:

None.

This is not a bug, but a specification update.

0J27A

ED9


When the SCI is configured in Synchronous mode, internal clock, and all the SCI pins are enabled simultaneously, an extra pulse of 1 DSP clock length is provided on the SCLK pin.

Workaround:

a. Enable an SCI pin other than SCLK.

b. In the next instruction, enable the remaining SCI pins, including the SCLK pin.

This is not a bug, but a specification update.

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ED14

The data sheets of the various DSP56300 host interfaces (HI32 excluded) must be modified to make the HI08/HDI08 compatible with PortA timing 114, which is included here as a reference.

Timing 321 "Write data strobe deassertion width" should be split (similar to timing 319 "Read data strobe deassertion width"), as described here:

Write data strobe deassertion width:

• after HCTR, HCVR and "Last Data Register" writes 2.5*Tc+10.0 @66MHz

2.5*Tc+8.3 @80MHz2.5*Tc+6.6 @100MHz

• after TXH:TXM writes (with HBE=0),TXM:TXL writes (with HBE=1) 25 @66MHz

20.6 @80MHz16.5 @100MHz

That is, a minimum of 4 WS for PortA is required for 100 MHz operation.

Reference: Timing 114 @ 100MHz

114WR_ deassertion time 0.5 x TC - 3.5 1.5ns

[WS = 1]

TC - 3.5 6.5ns[2 <= WS <= 3]

2.5 x TC - 3.5 21.5ns[4 <= WS <= 7]

3.5 x TC - 3.5 31.5ns[WS >= 8]

0J27A

ED17


In all DSP563xx technical datasheets, a note is to be added under "AC Electrical Characteristics" that although the minimum value for "Frequency of Extal" is 0MHz, the device AC test conditions are 15MHz and rated speed.

Workaround:

N/A

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ED20


In the Technical Datasheet Voh-TTL should be listed at 2.4 Volts, not as:

TTL = Vcc-0.4

Workaround:

This is a documentation update.

0J27A

ED24


The technical datasheet supplies a maximum value for internal supply current in Normal, Wait, and Stop modes. These values will be removed because we will specify only a "Typical" current.

Workaround:

This is a documentation update.

0J27A

ED26


The specification DMA Chapter is wrong.

“Due to the DSP56300 Core pipeline, after DE bit in DCRx is set, the corresponding DTDx bit in DSTR will be cleared only after two instruction cycles.”

Should be replaced with:

“Due to the DSP56300 Core pipeline, after DE bit in DCRx is set, the corresponding DTDx bit in DSTR will be cleared only after three instruction cycles.”

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ED28

Description (added 1/7/1997; identified as Documentation Errata 2/1/99):

When two consecutive LAs have a conditional branch instruction at LA-1 of the internal loop, the part does not operate properly. For example, the following sequence may generate incorrect results:

DO #5, LABEL1NOPDO #4, LABEL2NOP MOVE (R0) +BSCC _DEST ; conditional branch at LA-1 of

internal loopNOP ; internal LA

LABEL2NOP ; external LA

LABEL1NOP NOP

_DEST NOPNOP RTS

Workaround: Put an additional NOP between LABEL2 and LABEL1.

Pertains to: DSP56300 Family Manual, Appendix B, Section B-4.1.3, “At LA-1.”

0J27A

ED29

Description (added 9/12/1997; identified as a Documentation errata 2/1/99):

When the ESSI transmits data with the CRA Word Length Control bits (WL[2:0]) = 100, the ESSI is designed to duplicate the last bit of the 24-bit transmission eight times to fill the 32-bit shifter. Instead, after shifting the 24-bit word correctly, eight 0s are being shifted.

Workaround:

None at this time.

Pertains to: UM, Section 7.4.1.7, “CRA Word Length Control.” The table number is 7-2.

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ED30


When the ESSI transmits data in the On-Demand mode (i.e., MOD = 1 in CRB and DC[4:0] = $00000 in CRA) with WL[2:0] = 100, the transmission does not work properly.

Workaround:

To ensure correct operation, do not use the On-Demand mode with the WL[2:0] = 100 32-bit Word-Length mode.

Pertains to: UM, Section 7.5.4.1, “Normal/On-Demand Mode Selection.”

0J27A

ED31

Description (added 9/12/1997; modified 9/15/1997; identified as a Documentation errata 2/1/99):

Programming the ESSI to use an internal frame sync (i.e., SCD2 = 1 in CRB) causes the SC2 and SC1 signals to be programmed as outputs. If however, the corresponding multiplexed pins are programmed by the Port Control Register (PCR) to be GPIOs, then the GPIO Port Direction Register (PRR) chooses their direction, but this causes the ESSI to use an external frame sync if GPIO is selected.

Note: This errata and workaround apply to both ESSI0 and ESSI1.

Workaround:

To assure correct operation, either program the GPIO pins as outputs or configure the pins in the PCR as ESSI signals.

Note: The default selection for these signals after reset is GPIO.

Pertains to: UM, Section 7.4.2.4, “CRB Serial Control Direction 2 (SCD2) Bit 4”

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ED32

When returning from a long interrupt (by RTI instruction), and the first instruction after the RTI is a move to a DALU register (A, B, X, Y), the move may not be correct, if the 16-bit arithmetic mode bit (bit 17 of SR) is changed due to the restoring of SR after RTI.

Workaround:

Replace the RTI with the following sequence:

movec ssl,srnoprti

Pertains to: DSP56300 Family Manual. Add a new section to Appendix B that is entitled “Sixteen-Bit Compatibility Mode Restrictions.”

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ED33


When Stack Extension mode is enabled, a use of the instructions BRKcc or ENDDO inside do loops might cause an improper operation. If the loop is non nested and has no nested loop inside it, the erratais relevant only if LA or LC values are being used outside the loop.

Workaround:

If Stack Extension is used, emulate the BRKcc or ENDDO as in the following examples. We split between two cases, finite loops and do forever loops.

1) Finite DO loops (i.e. not DO FOREVER loops)

==============================================

BRKcc

Original code:

do #N,label1..........

do #M,label2..........BRKcc..........

label2..........

label1

Will be replaced by:

do #N, label1..........

do #M, label2..........Jcc fix_brk_routine..........

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ED33 cont.

nop_before_label2nop ; This instruction must be NOP.

label2..........

label1........

fix_brk_routinemove #1,lcjmp nop_before_label2

ENDDO------Original code:

do #M,label1..........

do #N,label2..........ENDDO..........

label2..........

label1


do #M, label1..........

do #N, label2..........JMP fix_enddo_routine

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ED33 cont.

nop_after_jmpNOP ; This instruction must be NOP...........

label2..........

label1........

fix_enddo_routinemove #1,lcmove #nop_after_jmp,lajmp nop_after_jmp

2) DO FOREVER loops===================

BRKcc-----Original code:

do #M,label1..........

do forever,label2..........BRKcc..........

label2..........

label1

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ED33 cont.


do #M,label1..........

do forever,label2..........JScc fix_brk_forever_routine ; <---

note: JScc and not Jcc..........

nop_before_label2nop ; This instruction must be NOP.

label2..........

label1........

fix_brk_forever_routinemove ssh,x:<..> ; <..> is some reserved not used

address (for temporary data)move #nop_before_label2,sshbclr #16,ssl ;move #1,lcrti ; <---- note: "rti" and not "rts" !

ENDDO------Original code:

do #M,label1..........

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ED33 cont.

do forever,label2..........ENDDO..........

label2..........

label1


do #M,label1..........

do forever,label2..........JSR fix_enddo_routine ; <--- note:

JSR and not JMPnop_after_jmp

NOP ; This instruction should be NOP..........

label2..........

label1........

fix_enddo_routinenopmove #1,lcbclr #16,sslmove #nop_after_jmp,larti ; <--- note: "rti" and not "rts"

Pertains to: DSP56300 Family Manual, Section B-4.2, “General Do Restrictions.”

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ED34


When stack extansion is enabled, the read result from stack may be improper if two previous executed instructions cause sequential read and write operations with SSH. Two cases are possible:

Case 1:

For the first executed instruction: move from SSH or bit manipulation on SSH (i.e. jclr, brclr, jset, brset, btst, bsset, jsset, bsclr, jsclr).

For the second executed instruction: move to SSH or bit manipulation on SSH (i.e. jsr, bsr, jscc, bscc).

For the third executed instruction: an SSL or SSH read from the stack result may be improper - move from SSH or SSL or bit manipulation on SSH or SSL (i.e., bset, bclr, bchg, jclr, brclr, jset, brset, btst, bsset, jsset, bsclr, jsclr).

Workaround:

Add two NOP instructions before the third executed instruction.

Case 2:

For the first executed instruction: bit manipulation on SSH (i.e. bset, bclr, bchg).

For the second executed instruction: an SSL or SSH read from the stack result may be improper - move from SSH or SSL or bit manipulation on SSH or SSL (i.e., bset, bclr, bchg, jclr, brclr, jset, brset, btst, bsset, jsset, bsclr, jsclr).

Workaround:

Add two NOP instructions before the second executed instruction.

Pertains to: DSP56300 Family Manual, Appendix B, add a new section called “Stack Extension Enable Restrictions.” Cover all cases. Also, in Section 6.3.11.15, add a cross reference to this new section.

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ED38


If Port A is used for external accesses, the BAT bits in the AAR3-0 registers must be initialized to the SRAM access type (i.e. BAT = 01) or to the DRAM access type (i.e. BAT = 10). To ensure proper operation of Port A, this initialization must occur even for an AAR register that is not used during any Port A access. Note that at reset, the BAT bits are initialized to 00.

Pertains to: DSP56300 Family Manual, Port A Chapter (Chapter 9 in Revision 2), description of the BAT[1 –0] bits in the AAR3 - AAR0 registers. Also pertains to the core chapter in device-specific user’s manuals that include a description of the AAR3 - AAR0 registers with bit definitions (usually Chapter 4).

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ED40

Description (added 11/11/99):When an instruction with all the following conditions follows a repeat instruction, then the last move will be corrupted.: 1. The repeated instruction is from external memory.2. The repeated instruction is a DALU instruction that includes 2 DAL registers, one as a source, and one as destination (e.g. tfr, add).3. The repeated instruction has a double move in parallel to the DALU instruction: one move’s source is the destination of the DALU instruction (causing a DALU interlock); the other move’s destination is the source of the DALU instruction. Example:

rep #number

tfr x0,a x(r0)+,x0 a,y0 ; This instruction is from external memory |__|_________|------|----------> This is condition 3 second part. |_____________|----------> This is condition 3, first part - DALU interlock

In this example, the second iteration before the last, the "x(r0)+,x0" doesn’t happen. On the first iteration before the last, the X0 register is fixed with the "x(r0)+,x0", but the "tfr x0,a" gets the wrong value from the previous iteration’s X0. Thus, at the last iteration the A register is fixed with "tfr x0,a", but the "a,y0" transfers the wrong value from the previous iteration’s A register to Y0.

Workaround: 1. Use the DO instruction instead; mask any necessary interrupts before the DO. 2. Run the REP instructions from internal memory. 3. Don’t make DALU interlocks in the repeated instruction. After the repeat make the move. In the example above, all the "move a,y0" are redundant so it can be done in the next instruction: rep #numbertfr x0,a x(r0)+,x0 move a,y0

If no interrupts before the move is a must, mask the interrupts before the REP. Pertains to: DSP56300 Family Manual, Rev. 2, Section A.3, “Instruction Sequence Restrictions.”

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NOTES

1. An over-bar (i.e. xxxx) indicates an active-low signal.

2. The letters seen to the right of the errata tell which DSP56306 mask numbers apply.

3. The Motorola DSP website has additional documentation updates that can be accessed at the following URL:

http://www.motorola-dsp.com/documentation/index.html

-end-

ED42

Description (added on 3/22/2000)

The DMA End-of-Block-Transfer interrupt cannot be used if DMA is operating in the mode in which DE is not cleared at the end of the block transfer (DTM = 100 or 101).

Pertains to:

DSP56300 Family Manual, Rev. 2, Section 10.4.1.2, “End-of-Block-Transfer Interrupt.” Also, Section 10.5.3.5, “DMA Control Registers (DCR[5–0],” discussion of bits 21 – 19 (DTM bits).

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Documents

Freescale Semiconductor, Inc. · Chip Errata DSP56306 Digital Signal Processor Mask: 0J27A Motorola SPS 306CE0J27A_2_0 pg. 1 /ng/7/17/00 6501 William Cannon Drive West, Austin, Texas