FS60X Manual

8/10/2019 FS60X Manual

http://slidepdf.com/reader/full/fs60x-manual 1/8

FS604FS609

Introduction

The FS604 and FS609 are compact, low cost development boards based on Xilinx Spartan 6LXFPGs!

Feat"res incl"de #$%& '(%, )*$+& FLS, a hi-h ."alit/ cloc so"rce, two expansion

connectors and a 1TG test access port 2or device con2i-"ration and deb"--in-!

Applications

St"dent lab demonstrator board

3)0%SPS oscilloscope capt"re b"er

#3)%SPS *6 bit ''S b"er

Triple *050i video 2rame b"ers

(obotic control

Physical

'imensions 36mm x 4*mm x *6mm

ei-ht

• $#- FS60x main board

• $9- with 7S&$8)500 re-"lator

• *$4- paca-ed shippin- wei-ht

Power cons"mption

• *60m t/pical 2rom $!468 rail and

• 5)m t/pical 2rom *!$#8 rail

(ev*!** www!sioi!com!a" *

Low cost Xilinx Spartan 6LX development boards

http://www.sioi.com.au/




FS604FS609

Key components

Xilinx Spartan 6LX FPG

• X6SLX4:#T;G*44 <FS604=

• X6SLX9:$T;G*44 <FS609=

S'(% $)6%b<*6%x*6= ''(400• Samsun- +4)6* 6#5

SP? Flash con2i-"ration memor/, 4%b <$!3%b FPG *!#%b "ser=

r/stal oscillator, 6$!) %@ low AiBer

Cxpansion ed-e connector, 64 wa/ *mm pitch #5 "ser ?D <$!)8 rail=

dditional expansion connector, *6 wa/ 0!*E pitch 5x$ receptacle 6 "ser ?D <$!)8 rail=

Xilinx standard *4 pin 1TG header

7ser controlled LC'

Customised versions

"stomised versions available "pon re."est

?nd"strial temperat"re ran-e FPG

Dther FPG speed options

• X6SLX4:$T;G*44

• X6SLX9:#T;G*44

'(% 64 %b *$5%b $)6%b )*$%b *Gb

'(% ''(400 ''()00 <64%b or *$5%b onl/=

Flash 4%b 5%b *6%b #$%b 64%b

64 wa/ expansion connector with da"-hter board parallel to the main board

$ www!sioi!com!a" (ev *!**





FS604FS609

Kit contents

FS60x main board

Power re-"lator 7S&$8)500 <pl"- into a 7S& port to power "nit=

7S& cable <power onl/= '(% controller ?P core ''(*66

(e2erence desi-n %icro&la@e H '(% H 7(T H GP?D

%an"al and Schematic

Here's what you get:

(ev*!** www!sioi!com!a" #





FS604FS609

Aaching the power regulator

Please attach the USB2V5A800 power adapter and USB cable like this:

The USB2V5A800 and the S!0" board are ke#ed at pin location $$ to pre%ent incorrect

insertion

The correct order &or connection is:

$' (onnect the USB2V5A800 to the S!0" motherboard2' (onnect the USB cable to the USB2V5A800

)' (onnect the USB cable to a power source

If you apply power to the USB2V5A800 before connecting to the FS60x boarthen you !ight a!age both boar"# $lea"e only apply power after the"e twoboar" are connecte#

To reset the P*A #ou need to disconnect the power and then reconnect it' The7S&$8)500 has b"ilt in circ"itr/ to correctl/ reset the FPG on power "p!

4 www!sioi!com!a" (ev *!**





FS604FS609

Aaching a JTAG programmer

To pro-ram the FPG please connect a 1TG pro-rammer lie this

7se a 1TG cable that matches the Xilinx standard *4 pin $mm pitch 1TG header

The Xilinx brand 7S& or Parallel cables wor well

(ev*!** www!sioi!com!a" )





FS604FS609

Primary Expansion connector

The 64 wa/ ed-e connector 2eat"res #5 "ser ?D pins which can be con2i-"red as #5 sin-le ended?Ds or as *9 dierential ?D pairs!

Support &or up to + di&&erential or 8 sin,le ended ,lobal clocks 50 ohm s in,le ended characteristic impedance

$00 ohm dierential characteristic impedance

-d,e connector maintains characteristic impedance across board to board boundar#

-d,e connector rated &or operation up to 5*bps per si,nal pair

P*A ./ pins powered &rom 2'+!V rail

(ompatible with ilin" 2'5V V((/ si,nalin, standards:

• 1V(/S25

• SST12• 1V3S425


FPGA pin IO bank Corner Pin name Expansion pin Notes

40 2 BL IO_L64N_D9_2 CN64-35

41 2 BL IO_L64P_D8_2 CN64-37

43 2 BL IO_L62N_D6_2 CN64-43

44 2 BL IO_L62P_D5_2 CN64-45

45 2 BL IO_L49N_D4_2 CN64-51

46 2 BL IO_L49P_D3_2 CN64-5347 2 BL IO_L48N_RDWR_B_VREF_2 CN64-61

48 2 BL IO_L48P_D7_2 CN64-59

50 2 BL IO_L31N_GCLK30_D15_2 CN64-62 GCLK capa!"

51 2 BL IO_L31P_GCLK31_D14_2 CN64-60 GCLK capa!"

55 2 BR IO_L30N_GCLK0_#$ERCCLK_2 CN64-58 GCLK capa!"

56 2 BR IO_L30P_GCLK1_D13_2 CN64-56 GCLK capa!"

57 2 BR IO_L14N_D12_2 CN64-54

58 2 BR IO_L14P_D11_2 CN64-52

61 2 BR IO_L12N_D2_%I$O3_2 CN64-50

62 2 BR IO_L12P_D1_%I$O2_2 CN64-48

66 2 BR IO_L2N_C%P%O$I_2 CN64-46

67 2 BR IO_L2P_C%PCLK_2 CN64-44

74 1 RB IO_L74N_DO#&_B#$'_1 CN64-42

75 1 RB IO_L74P_(W(KE_1 CN64-40

78 1 RB IO_L47N_1 CN64-38

79 1 RB IO_L47P_1 CN64-36

80 1 RB IO_L46N_1 CN64-34

81 1 RB IO_L46P_1 CN64-32

82 1 RB IO_L45N_1 CN64-30

83 1 RB IO_L45P_1 CN64-28

84 1 RB IO_L43N_GCLK4_1 CN64-26 GCLK capa!"

85 1 RB IO_L43P_GCLK5_1 CN64-24 GCLK capa!"

87 1 RB IO_L42N_GCLK6_&RD'1_1 CN64-20 GCLK capa!"

88 1 RB IO_L42P_GCLK7_1 CN64-18 GCLK capa!"

97 1 R& IO_L34N_1 CN64-1698 1 R& IO_L34P_1 CN64-14

99 1 R& IO_L33N_1 CN64-12

100 1 R& IO_L33P_1 CN64-10

101 1 R& IO_L32N_1 CN64-8

102 1 R& IO_L32P_1 CN64-6

104 1 R& IO_L1N_VREF_1 CN64-4

105 1 R& IO_L1P_1 CN64-2

)p*+),a! ".p+/" ), ."c),a .+"

)p*+),a! ".p+/" ), ."c),a .+"





FS604FS609

man# others see ilin" U*)8$

$8 o& the ./s come &rom Bank 2 and 20 come &rom Bank $' (onsult ilin" U*)8$re,ardin, the capabilities o& each ./ bank

/ne ./ pin can be con&i,ured as Bank $ V6- input

/ne ./ pin can be con&i,ured as Bank 2 V6- input

*round $'2)V and 2'+!V power rails connected at multiple pins

Unre,ulated 5V 7USB power also a%ailable at two pins

/pen drain *lobal 6eset allows reset in and reset out

The ed,e connector used is the same as that used &or P(.- "+' .t &eatures a $mm pitch and

has !+ connections con&i,ured as a ,roup o& 22 and a ,roup o& +2 with a ke#in, spacer

between the two ,roups

The ed,e connector used is (. part $00$898+$020$T1 or similar

n expansion board template 2or -C' P& ' paca-e available as a 2ree download2rom S?D? website

Connector orientationThe numberin, orientation o& the connectors is shown below:

(ev*!** www!sioi!com!a" 3





FS604FS609

econdary expansion connector

The *6 wa/ 5x$ *00 mil pitch connector is primaril/ a power inp"t b"t also incl"des connectionsto 6 FPG ?D pins, eno"-h 2or low bandwidth peripherals! connection to the open drainGlobal (eset si-nal is also provided!

The FLSIL+ si-nal is terminated on the 7S&$8)500 da"-hter board with a )0 ohmtermination to the *!$#8 rail!

o!ware Compati"ility ompatible with

• 2ree Xilinx ?SC ebP+ soJware

• Xilinx ?SC, C'+ and S'+ soJware

• Xilinx %icro&la@e soJ P7

#A$

Q: Can I power the board from the 64 way expansion connector ?

Kes, /o" can power the board 2rom the 64 wa/ expansion connector! Ko" need to s"ppl/ $!468

H: 0!0)8 and *!$#8! T/pical cons"mption is *60m and 5)m, so desi-n 2or at least twice that 2orsa2et/! The *!$#8 rail sho"ld be <)0*=M o2 the $!468 rail as it is "sed 2or ''( termination andre2erence volta-e! The T? TPS)* *00 is a s"itable re-"lator 2or the *!$#8 rail!

Ko" do not need to s"ppl/ )8, the )8 rail simpl/ r"ns 2rom the 64 wa/ connector to the *6 wa/connector in case /o" want to s"ppl/ )8 2rom one connector and cons"me it at the other!

The FS60x has several b"l deco"plin- capacitors close to the *6 wa/ connector! s /o" will bes"ppl/in- power 2rom the 64 wa/ connector please s"pplement them b/ placin- at least two*0"F ceramic deco"plin- caps 2or the $!468 rail and at least two *0"F ceramic deco"plin- caps2or the *!$#8 rail on /o"r da"-hter card, close to the ed-e connector!


FPGA pin IO bank Corner Pin name Expansion pin Notes

38 2 BL IO_L65N_C$O_B_2 FL($ C$ p+, DR16-16

70 2 BR IO_L1P_CCLK_2 FL($-CLK DR16-2

64 2 BR IO_L3N_%O$I_C$I_B_%I$O0_2 FL($-DIN DR16-14

65 2 BR IO_L3P_D0_DIN_%I$O_%I$O1_2 FL($-DO#& DR16-1

92 1 R& IO_L41N_GCLK8_1 DR16-3

93 1 R& IO_L41P_GCLK9_IRD'1_1 DR16-13

terminate on HDR16 daugterboar



Documents

FS60X Manual