FSM ASM Diagramas

8/16/2019 FSM ASM Diagramas

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George Mason UniversityECE 448 – FPGA and ASIC Design with VHDL

Finite State Machines

State Diagrams,

State Tables,

Algorithmic State Machine (ASM) Charts,

and VHDL code

ECE 44

Lect!re


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"ECE 448 – FPGA and ASIC Design with VHDL

#e$!ired reading

% S& 'ron and & Vranesic, Fundamentals of Digital Logi with VHDL Design

Chapter 8, Synchronous Sequential Circuits

Sections 8.1-8.5 Chapter 8.10, Algorithmic State Machine

(ASM) Charts

% *& Ch!, FPGA P!otot"#ing $" VHDL E%am#les

Chapter 5, SM


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+ECE 448 – FPGA and ASIC Design with VHDL

Datapath

vs.

Controller


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4ECE 448 – FPGA and ASIC Design with VHDL

Str!ct!re o a T-.ical Digital S-stem

Data.ath(E/ec!tion

0nit)

Controller (Control

0nit)

Data 1n.!ts

Data 2!t.!ts

Control 1n.!ts

Stat!s 2!t.!ts

Control

Signals

Stat!s

Signals


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Data.ath (E/ec!tion 0nit)

% Mani.!lates and .rocesses data

% *erorms arithmetic and logic o.erations, shiting,

and other data.rocessing tas5s

% 1s com.osed o registers, gates, m!lti.le/ers,

decoders, adders, com.arators, AL0s, etc&% *ro6ides all necessar- reso!rces and

interconnects among them to .erorm s.eciied

tas5

% 1nter.rets control signals rom the Controller and

generates stat!s signals or the Controller


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Controller (Control 0nit)

% Controls data mo6ements in the Data.ath b-sitching m!lti.le/ers and enabling or disablingreso!rces

E/am.le8 enable signals or registers

E/am.le8 control signals or m!/es

% *ro6ides signals to acti6ate 6ario!s .rocessingtas5s in the Data.ath

% Determines the se$!ence the o.erations.erormed b- Data.ath

% Follos Some 9*rogram: or Sched!le


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Controller

% Controller can be .rogrammable or non.rogrammable

% *rogrammable

% Has a .rogram co!nter hich .oints to ne/t instr!ction

% 1nstr!ctions are held in a #AM or #2M e/ternall-

% Micro.rocessor is an e/am.le o .rogrammablecontroller

% or=hardired instr!ctions>

% In the following several lectures we will be focusing

on non-programmable controllers.


8/56ECE 448 – FPGA and ASIC Design with VHDL

Finite State Machines% Digital S-stems and es.eciall- their Controllers can be

described as Finite State Machines (FSMs)% Finite State Machines can be re.resented !sing

% State Diagrams and State Tables s!itable or

sim.le digital s-stems ith a relati6el- e in.!ts

and o!t.!ts

% Algorithmic State Machine (ASM Charts

s!itable or com.le/ digital s-stems ith a large

n!mber o in.!ts and o!t.!ts

% All these descri.tions can be easil- translated to the

corres.onding s-nthesi?able VHDL code


9/56@ECE 448 – FPGA and ASIC Design with VHDL

!ardware Design with "T# $!D#

*se!docode

Data.ath Controller

'loc5

diagram

'loc5

diagram

State diagram

o! ASM chart

VHDL code VHDL code VHDL code

1nterace


10/56BECE 448 – FPGA and ASIC Design with VHDL

%inite State Machines"efresher



Finite State Machines (FSMs)

% An- Circ!it ith Memor- 1s a Finite StateMachine

% E6en com.!ters can be 6ieed as h!ge FSMs

% Design o FSMs 1n6ol6es% Deining states

% Deining transitions beteen states

% 2.timi?ation minimi?ation

% Man!al 2.timi?ationMinimi?ation 1s

*ractical or Small FSMs 2nl-


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Moore FSM

% 2!t.!t 1s a F!nction o a *resent State 2nl-

*resent State

register


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Meal- FSM

% 2!t.!t 1s a F!nction o a *resent State and 1n.!ts



State Diagrams



Moore Machine

state & '

output &

state 'output

transition

condition &

transition

condition


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Moore 6s& Meal- FSM ()

% Moore and Meal- FSMs Can 'eF!nctionall- E$!i6alent

% E$!i6alent Meal- FSM can be deri6ed rom

Moore FSM and 6ice 6ersa% Meal- FSM Has #icher Descri.tion and

0s!all- #e$!ires Smaller

States% Smaller circ!it area



Moore 6s& Meal- FSM (")

% Meal- FSM Com.!tes 2!t.!ts as soon as1n.!ts Change

% Meal- FSM res.onds one cloc5 c-cle sooner

than e$!i6alent Moore FSM% Moore FSM Has


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Moore FSM E/am.le

% Moore FSM that #ecogni?es Se$!ence =B>

SB B S B S"

BB

B

reset

Meaningo states8

SB8

obser6ed

S"8 =B>

obser6ed


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Meal- FSM E/am.le

% Meal- FSM that #ecogni?es Se$!ence=B>

SB S

B B B B

B reset

Meaning

o states8

SB8

obser6ed


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Moore Meal- FSMs E/am.le

cloc5

in.!t

Moore

Meal-

B B B B

SB S S" SB SB

SB S SB SB SB


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""ECE 448 – FPGA and ASIC Design with VHDL

%inite State Machinesin $!D#


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"+ECE 448 – FPGA and ASIC Design with VHDL

FSMs in VHDL

% Finite State Machines Can 'e Easil-

Described ith *rocesses

% S-nthesis Tools 0nderstand FSM Descri.tion

i Certain #!les Are Folloed

% State transitions sho!ld be described in a .rocess

sensiti6e to lo& and as"nh!onous !eset signals

onl-

%2!t.!t !nction described !sing r!les orcombinational logic, i&e& as conc!rrent statements

or a .rocess ith all in.!ts in the sensiti6it- list


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"3ECE 448 – FPGA and ASIC Design with VHDL

Meal- FSM


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"7ECE 448 – FPGA and ASIC Design with VHDL

Moore FSM E/am.le

% Moore FSM that #ecogni?es Se$!ence =B>

SB B S B S"

B

B

B

reset


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";ECE 448 – FPGA and ASIC Design with VHDL

Moore FSM in VHDL ()

T+, state IS (S* S&* S/

SI01A# Moore2state3 state/

42Moore3 ,"5CSS (cloc)* reset

60I1

I%(reset 7 8&9 T!1

Moore2state :7 S/

#SI% (cloc) 7 8&9 A1D cloc)9event T!1

CAS Moore2state IS

;!1 S 7<

I% input 7 8&9 T!1

Moore2state :7 S&/

#S

Moore2state :7 S/

1D I%/


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"ECE 448 – FPGA and ASIC Design with VHDL

Moore FSM in VHDL (")

;!1 S& 7


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"@ECE 448 – FPGA and ASIC Design with VHDL

Meal- FSM E/am.le

% Meal- FSM that #ecogni?es Se$!ence=B>

SB S

B B B B

B reset


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+BECE 448 – FPGA and ASIC Design with VHDL

Meal- FSM in VHDL ()

T+, state IS (S* S&/SI01A# Meal=2state3 state/

42Meal=3 ,"5CSS(cloc)* reset

60I1

I%(reset 7 8&9 T!1Meal=2state :7 S/

#SI% (cloc) 7 8&9 A1D cloc)9event T!1

CAS Meal=2state IS

;!1 S 7<

I% input 7 8&9 T!1

Meal=2state :7 S&/

#S

Meal=2state :7 S/

1D I%/


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Meal- FSM in VHDL (")

;!1 S& 7< I% input 7 89 T!1

Meal=2state :7 S/

#S

Meal=2state :7 S&/

1D I%/

1D CAS/

1D I%/

1D ,"5CSS/

5utput :7 8&9 ;!1 (Meal=2state 7 S& A1D input 7 89 #S 89/


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+"ECE 448 – FPGA and ASIC Design with VHDL

Algorithmic State Machine (ASMCharts


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++ECE 448 – FPGA and ASIC Design with VHDL

Algorithmic State Machine

Algorithmic State Machine

re.resentation o a Finite State Machine

s!itable or FSMs ith a larger n!mber oin.!ts and o!t.!ts com.ared to FSMs

e/.ressed !sing state diagrams and state

tables&


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+4ECE 448 – FPGA and ASIC Design with VHDL

Elements !sed in ASM charts ()

Output signals

or actions

(Moore type)

State name

Condition

expression

0 (False) 1 (True)

Conditional outputs

or actions (Mealy type)

(a) State ox () !ecision ox

(c) Conditional output ox


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State 'o/

% State bo> re.resents a state&

% E$!i6alent to a node in a state diagram or aro in a state table&

% Contains register transer actions or o!t.!tsignals

% Moore-t=pe outputs are listed inside of thebo>.

% 1t is c!stomar- to rite onl- the name o thesignal that has to be asserted in the gi6enstate, e&g&, ? instead o ?G&

% Also, it might be !se!l to rite an action to beta5en, e&g&, co!nt G co!nt I , and onl- latertranslate it to asserting a control signal thatca!ses a gi6en action to ta5e .lace (e&g&,enable signal o a co!nter)&

Output signals

or actions

(Moore type)

State name


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Decision 'o/

% Decision bo> indicates that a

gi6en condition is to

be tested and the

e/it .ath is to bechosen accordingl-

The condition

e/.ression ma-incl!de one or more

in.!ts to the FSM&

Condition

expression

0 (False) 1 (True)


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+;ECE 448 – FPGA and ASIC Design with VHDL

Conditional 2!t.!t 'o/

% Conditional

output bo>

% Denotes o!t.!t

signals that are o

the Meal- t-.e&

% The condition that

determines hether

s!ch o!t.!ts are

generated iss.eciied in the

decision bo/&

Conditional outputs

or actions (Mealy type)

ASMs re.resenting sim.le FSMs


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ASMs re.resenting sim.le FSMs

% Algorithmic state machines can model bothMeal- and Moore Finite State Machines

% The- can also model machines that are o

the mi/ed t-.e


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4BECE 448 – FPGA and ASIC Design with VHDL

Present Next state Outputstate

w " 0 w " 1 z

A A B 0B A C 0

C A C 1

Moore FSM E/am.le "8 State table


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4"ECE 448 – FPGA and ASIC Design with VHDL

4S ieee.std2logic2&&[email protected] /

1TIT+ simple IS

,5"T ( cloc) 3 I1 STD2#50IC /

resetn 3 I1 STD2#50IC /

w 3 I1 STD2#50IC /

3 54T STD2#50IC /

1D simple /

A"C!ITCT4" 6ehavior 5% simple IS

T+, State2t=pe IS (A* 6* C /

SI01A# = 3 State2t=pe /

60I1

,"5CSS ( resetn* cloc)

60I1

I% resetn 7 BB T!1

= :7 A /

#SI% (Cloc)B$1T A1D Cloc) 7 B&B T!1

E/am.le "8 VHDL code ()


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4+ECE 448 – FPGA and ASIC Design with VHDL

CAS = IS

;!1 A 7<

I% w 7 BB T!1= :7 A /

#S

= :7 6 /

1D I% /

;!1 6 7<

I% w 7 BB T!1

= :7 A /

#S

= :7 C /

1D I% /

;!1 C 7<

I% w 7 BB T!1

= :7 A /

#S

= :7 C /

1D I% /

1D CAS /

E/am.le "8 VHDL code (")

E am.le " VHDL code (+)


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E/am.le "8 VHDL code (+)

1D I% / 1D ,"5CSS /

:7 B&B ;!1 = 7 C #S BB /

1D 6ehavior /

S S


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A

w 0= z 0= ⁄

w 1= z 1= ⁄Bw 0= z 0= ⁄

Reset

w 1= z 0= ⁄

Meal- FSM E/am.le +8 State diagram


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ASM Chart or Meal- FSM E/am.le +

w

w0 1

0

1

A

B

Reset

z

E l + VHDL d ()


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4;ECE 448 – FPGA and ASIC Design with VHDL

#I6"A"+ ieee /

4S ieee.std2logic2&&[email protected] /

1TIT+ Meal= IS

,5"T ( cloc) 3 I1 STD2#50IC /

resetn 3 I1 STD2#50IC /

w 3 I1 STD2#50IC /

3 54T STD2#50IC /1D Meal= /

A"C!ITCT4" 6ehavior 5% Meal= IS

T+, State2t=pe IS (A* 6 /

SI01A# = 3 State2t=pe /

60I1,"5CSS ( resetn* cloc)

60I1

I% resetn 7 BB T!1

= :7 A /

#SI% (cloc)B$1T A1D cloc) 7 B&B T!1

E/am.le +8 VHDL code ()


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E/am.le +8 VHDL code (")

CAS = IS ;!1 A 7<

I% w 7 BB T!1

= :7 A /

#S

= :7 6 /1D I% /

;!1 6 7<

I% w 7 BB T!1

= :7 A /

#S

= :7 6 /

1D I% /

1D CAS /


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Control 0nit E/am.le8 Arbiter ()


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3BECE 448 – FPGA and ASIC Design with VHDL

Control 0nit E/am.le8 Arbiter ()

Arbiter

reset

r&

r

r

g&

g

g

cloc)

Control 0nit E/am.le8 Arbiter (")


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Idle

000

1xx

Reset

gnt1g1 ⁄ 1=

x1x

gnt2g2 ⁄ 1=

xx1

gnt3g3 ⁄ 1=

0xx 1xx

01xx0x

001xx0

Control 0nit E/am.le8 Arbiter (")


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E l 4 VHDL d ()


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E/am.le 48 VHDL code ()

L1'#A#J ieeeK0SE ieee&stdlogic74&allK

E


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E/am.le 48 VHDL code (")'E1<

*#2CESS ( #esetn, Cloc5 )

'E1<

1F #esetn NBN THE< - G 1dle K

ELS1F (Cloc5NEVE


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E/am.le 48 VHDL code (+)

HE< gnt+ O

1F r(+) NN THE< - G gnt+ K

ELSE - G 1dle K

E

Documents

FSM ASM Diagramas