FUJITSU APIX2 DEVICES · FUJITSU APIX2 DEVICES . APIX FIR ... filter is implemented in the Fujitsu APIX transmitters to compensate ISI. ... 1 C0,C1 in parallel. C2, C3 provide signal

Fujitsu Semiconductor Europe Application Note

an-apix-fir-setup-rev2.0

FUJITSU APIX2 DEVICES

APIX FIR SETUP REV 2.0

APPLICATION NOTE

GRAPHICS COMPETENCE CENTER

APIX FIR Setup Revision History

an-apix-fir-setup-rev2.0 - 2 - © Fujitsu Semiconductor Europe GmbH

Revision History

Date Issue

2013-06-06 Rev 1.0 - AP Initial

2013-06-21 Rev 1.1 - AP Names of FIR filter coefficients updated

2013-08-13 Rev 2.0 – JC Recommendations aligned to requirements from Inova Semiconductors application note AN_INAP_204.pdf revision 1.1

This document contains 16 pages.

APIX FIR Setup Warranty and Disclaimer

© Fujitsu Semiconductor Europe GmbH - 3 - an-apix-fir-setup-rev2.0

Warranty and Disclaimer The use of the deliverables (e.g. software, application examples, target boards, evaluation boards, starter kits, schematics, engineering samples of IC’s etc.) is subject to the conditions of Fujitsu Semiconductor Europe GmbH (“FSEU”) as set out in (i) the terms of the License Agreement and/or the Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying written materials.

Please note that the deliverables are intended for and must only be used for reference in an evaluation laboratory environment.

The software deliverables are provided on an as-is basis without charge and are subject to alterations. It is the user’s obligation to fully test the software in its environment and to ensure proper functionality, qualification and compliance with component specifications.

Regarding hardware deliverables, FSEU warrants that they will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of 1 year from the date of receipt by the customer.

Should a hardware deliverable turn out to be defect, FSEU’s entire liability and the customer’s exclusive remedy shall be, at FSEU´s sole discretion, either return of the purchase price and the license fee, or replacement of the hardware deliverable or parts thereof, if the deliverable is returned to FSEU in original packing and without further defects resulting from the customer’s use or the transport. However, this warranty is excluded if the defect has resulted from an accident not attributable to FSEU, or abuse or misapplication attributable to the customer or any other third party not relating to FSEU or to unauthorised decompiling and/or reverse engineering and/or disassembling.

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The contents of this document are subject to change without a prior notice, thus contact FSEU about the latest one. Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect

APIX FIR Setup Contents


Contents REVISION HISTORY ............................................................................................................ 2

WARRANTY AND DISCLAIMER ......................................................................................... 3

CONTENTS .......................................................................................................................... 4

1 INTRODUCTION .............................................................................................................. 5

2 FIR AND DFE DESCRIPTION ......................................................................................... 6

2.1 Transmitter FIR Filter .............................................................................................. 6

2.1.1 Transmitter FIR register interface .............................................................. 6

2.2 Limitations ............................................................................................................... 7

2.3 Receiver DFE .......................................................................................................... 7

2.3.1 Receiver DFE Register Interface ............................................................... 8

3 TRANSMITTER FIR FILTER SETUP ............................................................................... 9

3.1 Initial FIR Values ..................................................................................................... 9

3.1.1 Emerald-P, ApCo ....................................................................................... 9

3.1.2 Indigo2(-x) (Daisychain) ............................................................................. 9

3.2 Eye Diagrams .......................................................................................................... 9

3.2.1 ApCo ....................................................................................................... 10

3.2.2 Indigo2(-x) ............................................................................................... 11

4 MANUAL FIR SETUP .................................................................................................... 14

4.1 Concept ................................................................................................................. 14

4.2 Method .................................................................................................................. 15

4.2.1 Measurement at MP2 .............................................................................. 15

4.2.2 Measurement using DFE ......................................................................... 16

APIX FIR Setup Chapter 1 Introduction


1 Introduction For the APIX2 3Gbps mode, it is not sufficient to send the data without any pre-emphasis. Frequency dependent transmission line losses (caused mainly by dielectric losses and skin effect) and reflections (caused by impedance discontinuities) cause inter-symbol-interference (ISI), which reduces the eye opening at the receiver. A finite-impulse-response (FIR) filter is implemented in the Fujitsu APIX transmitters to compensate ISI.

This application note describes the setup of the APIX FIR filters in the APIX2 3Gbps mode. The setup procedure uses the Emerald-P as the APIX transmitter, and the Indigo2 as the APIX receiver. Nevertheless, this application note can be used for all devices with an APIX interface.

MB86R12 ‘Emerald-P’ and MB86R91 ‘ApCo’ family devices use low power transmitters. These devices support cable lengths up to 3m.

MB88F33x ‘Indigo2(-x)’ family devices support daisy chain cable lengths up to 7m.

APIX FIR Setup Chapter 2 FIR and DFE Description


2 FIR and DFE Description

2.1 Transmitter FIR Filter The Fujitsu APIX2 transmitter output buffers have implemented FIR filters with 4 taps for signal preconditioning. The FIR structure is defined by the ‘b’ and ‘d’ switches, so that taps may be switched in parallel or serially with a 1 unit interval (UI) delay. The contribution of each tap to the output signal is defined by the ‘c’ coefficients.

For 500Mbps no signal shaping is possible. For 1Gbps some pre-emphasis is possible, but not usually needed. For the 3Gbps the filter has to be configured to provide the signal shaping needed to obtain a compliant signal quality at the receiver.

Figure 2.1: FIR filter block diagram

b3,b2 d4,d3,d2 Description x, x 1, 1, 1 No signal shaping. All taps parallel. 0, 0 0, 1, 1 Set C3 negative to provide pre-emphasis for 1Gbps 1, x 0, 1, 1 Signal shaping for 3Gbps. C3 provides pre-emphasis.

(recommended for Emerald-P and ApCo) 0,1 0, 0, 1 C0,C1 in parallel. C2, C3 provide signal shaping using 2 previous bits.

Table 1: FIR structure examples

2.1.1 Transmitter FIR register interface

Device Module Register Description Emerald-P APIX TX LINK

CH* FIR_filter_0 FIR coefficients FIR_filter_1 FIR structure

ApCo APIX TX LINK CH*

FIR_filter_0 FIR coefficients FIR_filter_1 FIR structure

Indigo2(-x) Daisychain

APIX2_PHY PHY_LT_CFG_CTRL_1 FIR coefficients PHY_LT_CFG_CTRL_2 FIR structure

Table 2: Transmitter FIR registers



FIR coefficients (see Figure 2.1):

Bits Description Bits Description 30 Sign of coefficient C3 14 Sign of coefficient C1 29:24 Magnitude of coefficient C3 13:8 Magnitude of coefficient C1 22 Sign of coefficient C2 6 Sign of coefficient C0 21:16 Magnitude of coefficient C2 5:0 Magnitude of coefficient C0

Table 3: FIR coefficient register

FIR structure (see Figure 2.1):

Bits Description Bits Description 4:2 d4, d3, d2 1:0 b3, b2

Table 4: FIR structure register

2.2 Limitations The FIR structure used is dependent upon the cable length and the transmitter power. For Emerald-P and ApCo the transmitter power is limited to 1mA pro tap, so that multiple parallel taps are required to drive the appropriate current.

Furthermore, it is strongly recommended that the output drivers are calibrated to ensure the correct output level.

Indigo2(-x) supports a daisy-chain transmitter with 2mA per tap. This allows longer cables than the 4m defined in the APIX2 standard.

2.3 Receiver DFE The APIX receiver uses a decision feedback equalizer (DFE) to compensate for transmission line impairments, like frequency dependent phase and amplitude distortion.

The AGC and DFE coefficients are calculated using an LMS algorithm running in the receiver and are continuously updated.

Figure 2.2: RX DFE block diagram



The DFE algorithm is only activated for 3Gbps reception. For lower rates default settings are used (agc=32, dfe*=0).

2.3.1 Receiver DFE Register Interface

The currently calculated values for the DFE and AGC can be observed. The AGC sets the internal signal level. The DFE compensates inter-symbol interference typically caused by cable effects. In an ideal system with a perfect signal inside the receiver the DFE coefficients tend to zero. Transmitter and cable tolerances, environment, matching, and aging effects will cause non-zero values.

Device Module Address Register Description Indigo2

or

APIX2_PHY 0x000200EC OBS_RX_1 [10:4] agc_coeff 0x000200F0 OBS_RX_0 [14] obs_dfe_fir_c0 sign

OBS_RX_0 [13:8] obs_dfe_fir_c0 mag OBS_RX_1 [22] obs_dfe_fir_c1 sign OBS_RX_1 [21:16] obs_dfe_fir_c1 mag OBS_RX_2 [30] obs_dfe_fir_c2 sign OBS_RX_2 [30:24] obs_dfe_fir_c2 mag

APIX2_RX 0x0002113C DBG_STAT_4 [22:16] dbg_rx_agc_coeff DBG_STAT_4 [30] dbg_rx_fir_coeff_0 sign DBG_STAT_4 [29:24] dbg_rx_fir_coeff_0 mag

0x00021140 DBG_STAT_5 [6] dbg_rx_fir_coeff_1 sign DBG_STAT_5 [5:0] dbg_rx_fir_coeff_1 mag DBG_STAT_5 [14] dbg_rx_fir_coeff_2 sign DBG_STAT_5 [13:8] dbg_rx_fir_coeff_2 mag

Emerald-P

APIX RX LINK

0x3A000174 DBG_ STS_DATA _4 [22:16] dbg_rx_agc_coeff DBG_ STS_DATA _4 [30] dbg_rx_fir_coeff_0 sign DBG_ STS_DATA _4 [29:24] dbg_rx_fir_coeff_0 mag

0x3A000178 DBG_ STS_DATA _5 [6] dbg_rx_fir_coeff_1 sign DBG_ STS_DATA _5 [5:0] dbg_rx_fir_coeff_1 mag DBG_ STS_DATA _5 [14] dbg_rx_fir_coeff_2 sign DBG_ STS_DATA _5 [13:8] dbg_rx_fir_coeff_2 mag

ApCo

APIX RX LINK

0x00008174 DBG_ STS_DATA _4 [22:16] dbg_rx_agc_coeff DBG_ STS_DATA _4 [30] dbg_rx_fir_coeff_0 sign DBG_ STS_DATA _4 [29:24] dbg_rx_fir_coeff_0 mag

0x00008178 DBG_ STS_DATA _5 [6] dbg_rx_fir_coeff_1 sign DBG_ STS_DATA _5 [5:0] dbg_rx_fir_coeff_1 mag DBG_ STS_DATA _5 [14] dbg_rx_fir_coeff_2 sign DBG_ STS_DATA _5 [13:8] dbg_rx_fir_coeff_2 mag

Table 5: Observable receiver registers

APIX FIR Setup Chapter 3 Transmitter FIR Filter Setup


3 Transmitter FIR Filter Setup The APIX2 Physical Layer Compliance document (AN_INAP_204.pdf revision 1.1) defines a minimum eye opening at the receiver end of the cable (measurement point MP2). The transmitter FIR settings must be adjusted to meet this requirement. This requires eye measurement using a real time oscilloscope with jitter measurement capability.

Following this step, fine tuning of the FIR settings may be performed based upon the DFE values observed in the receiver. This step is optional.

3.1 Initial FIR Values These configurations have been tested using Fujitsu validation boards. They may be used as guidance for customer set ups. It remains the customer’s responsibility to ensure the eye compliance in his system.

3.1.1 Emerald-P, ApCo The following values have been tested using the ApCo validation board. Emerald-P uses the same transmitter.

Cable length (m) c0 c1 c2 c3 b d FIR_filter_0 FIR_filter_1 0.5 63 63 63 -36 3 3 0x643F3F3F 0x0000000F 1 63 63 63 -38 3 3 0x663F3F3F 0x0000000F 1.5 63 63 63 -40 3 3 0x683F3F3F 0x0000000F 2 63 63 63 -42 3 3 0x6A3F3F3F 0x0000000F 3 63 63 63 -60 3 3 0x7C3F3F3F 0x0000000F

Table 6: Recommended Tx FIR

3.1.2 Indigo2(-x) (Daisychain) Cable length (m) c0 c1 c2 c3 b d FIR_filter_0 FIR_filter_1

0.5 63 63 -22 -6 1 1 0x46563F3F 0x00000005 1 63 63 -30 -2 1 1 0x425E3F3F 0x00000005 2 63 63 -36 -4 1 1 0x44643F3F 0x00000005 3 63 63 -40 -2 1 1 0x42683F3F 0x00000005 5 63 63 35 -63 3 3 0x7F233F3F 0x0000000F 7 63 63 17 -63 3 3 0x7F113F3F 0x0000000F

Table 7: Recommended Tx FIR

3.2 Eye Diagrams The following eye diagrams were measured at MP2 using a PRBS12 signal at room temperature. Measurements over extreme operating conditions indicate that 50mV margin at room temperature is sufficient to ensure compliance under all conditions. The blue mask shows the 100mV 0.4UI eye opening for Apix2 compliance.



3.2.1 ApCo

Figure 3.1 : 0m5 cable, FIR0 = 0x643F3F3F

Figure 3.2 : 2m cable, FIR0 = 0x6A3F3F3F



Figure 3.3 : 3m cable, FIR0 = 7C3F3F3F

3.2.2 Indigo2(-x)

Figure 3.4 : 0m5 cable, FIR0 = 46563F3F



Figure 3.5 : 2m cable, FIR0 = 44643F3F

Figure 3.6 : 3m cable, FIR0 = 42683F3F



Figure 3.7 : 5m cable, FIR0 = 7F233F3F

Figure 3.8 : 7m cable, FIR0 = 7F233F3F

APIX FIR Setup Chapter 4 Manual FIR Setup


4 Manual FIR Setup

4.1 Concept

Low power: Three taps provide drive current. The remaining tap can be used for signal preconditioning.

C0+C1+C2

C3

Signal at receiver without preconditioning

Signal at transmitter with preconditioning

Ideal signal at receiver

Figure 4.1: Signal preconditioning

Tap 0+1+2: Nominal current Tap 3: Post cursor

Short cables, high power: The drive strength of one tap is sufficient for high power transmitters driving signals over short cables. The other taps can be used for signal preconditioning. The FIR is configured as a shift register with 4 taps.

C0 C1 C2 C3





Tap 0: Pre cursor Tap 1: Nominal current Tap 2: Post cursor Tap 3: Corrections



Long cables, high power: The drive strength of one tap is not sufficient to achieve a good signal with high cable attenuations. Two taps are required for driving the appropriate drive current. The two remaining taps can be used for signal preconditioning.

C0 C1+C2 C3





Tap 0: Pre cursor Tap 1+2: Nominal current Tap 3: Corrections

4.2 Method

4.2.1 Measurement at MP2 • Set: c3 = c2 = c1= 0. Set c0 = 63. Set b=3, d=7 • Measure the eye at MP2. • If the eye is not sufficiently open (100mV) set c1 =63 and, if needed c2=63. • Set ‘b’ and ‘d’ according to table below:

c0 c1 c2

Comment b d 63 0 0 Short cable, high power 0 0 Case 1

63 63 0 Longer cable, high power 1 1 Case 2

63 63 63 Low power 3 3 Case 3

• Case 1: o Set b=0, d=0. Set c3=0, c1=63, c0=0. o Adjust c2 (negative) to optimise eye. o Adjust c0 (negative) and c3 (small) to improve eye further. o Optimize eye by balancing c0, c2 and c3 o After adjustment the eye opening must be min. 100mV for 0.4UI.

If this is not possible, case 2 is required.

• Case 2: o Set b=0, d=1. Set c1=c0=63, c3=c2=0. o Adjust c2 (negative) to optimize eye. o Adjust c3 (small) to improve eye further. o Optimize eye by balancing c2 and c3 o After adjustment, the eye opening must be min. 100mV for 0.4UI.

If this is not possible, case 3 is required.



• Case 3: o Set b=3, d=3. Set c2=c1=c0=63. o Adjust c3 (negative) to optimize eye. o If needed, set c3=-63 and reduce c2

If the eye opening exceeds the 100mV 0.4UI requirement, the total power can be reduced by reducing the magnitude of all ‘c’ coefficients proportionally.

4.2.2 Measurement using DFE Optionally, the transmitter FIR can be fine-tuned to minimize the DFE coefficients in the receiver. Fine-tune DFE coefficient 0 first, then 1, then 2.

Documents

FUJITSU APIX2 DEVICES · FUJITSU APIX2 DEVICES . APIX FIR ... filter is implemented in the Fujitsu APIX transmitters to compensate ISI. ... 1 C0,C1 in parallel. C2, C3 provide signal