Full Chip Impact Study of Power Delivery Network Designsin Monolithic 3D ICs

Sandeep Kumar Samal†, Kambiz Samadi§, Pratyush Kamal§, Yang Du§, and Sung Kyu Lim†

†School of ECE, Georgia Institute of Technology, Atlanta, GA§Qualcomm Research, San Diego, CA

sandeep.samal@gatech.edu, limsk@ece.gatech.edu

Abstract—In this paper, we present a comprehensive study on the im-pact of power delivery network (PDN) on full-chip wirelength, routability,power, and thermal effects in monolithic 3D ICs. Our studies first showthat the full PDN worsens routing congestion more severely in monolithic3D ICs than in 2D designs due to the significant reduction in resourcesfor 3D connections. The increase in signal wirelength translates intoadditional net switching power dissipation, which significantly contributesto total power. This in turn aggravates thermal issues in 3D ICs. Inaddition, we observe that PDN tradeoffs among wirelength, power, andthermal are more pronounced in monolithic 3D ICs than TSV-based 3Dand 2D designs. This is because of the higher integration density andthe severe competition between signal and power connections. Lastly,we develop various PDN design optimization techniques for monolithic3D ICs and obtain up to 8% signal wirelength and 5% maximumtemperature reduction under the given IR drop budget.

I. INTRODUCTION

Monolithic 3D IC is an emerging technology which is enabled bysequential vertical integration of extremely thin device layers withvery high alignment precision [1]. Unlike TSVs, monolithic inter-tier vias (MIVs) are miniscule (<100nm diameter) and can be usedin large numbers within the design. This helps in high integrationdensity allowing numerous 3D connections which results in reducedwirelength, improved power and better performance [2] [3]. TSV-based 3D ICs allow only limited number 3D connections due to largeTSV area and parasitics. This does not bring out the best in 3D ICs.MIVs on the other hand are similar to inter metal layer vias andhave negligible capacitance (≪1fF) compared to TSVs and thereforeimprove the potential benefits in 3D ICs. The side-view of a typicaltwo-tier monolithic stackup structure with seven metal layers in eachtier is shown in Figure 1. The device layer thickness is around 30nmand the inter tier dielectric (ILD) which separates different tiers isabout 100nm thick.

Every new emerging technology comes with new design challengesand issues which need to be first identified and then resolved to getmaximum benefits from that technology. Monolithic 3D ICs provideultra high integration density but the stacking of dies increases thepower density of the chip and also the current demand per unitarea. This in turn complicates the cooling issues and the powerdelivery network design. Most of the works on monolithic 3D ICsdo not address any thermal or power delivery issue. We know thatinterconnects do not scale with the same rate as devices. Therefore,interconnect power starts to dominate heavily as devices becomesmaller. Monolithic 3D ICs helps in reducing the interconnect lengthsignificantly by allowing tens of thousands of 3D MIVs. However, thepresence of power delivery network reduces the routing resources andadversely affects the total signal wirelength. Power delivery network(PDN) is always important in any design but due to 3D stacking oftiers with very high integration density in monolithic 3D ICs, optimalPDN design becomes much more important.

This work is supported by Qualcomm Research.

handle bulk (75 µm)

m1

m7

m7 MIV

top

tier

bot

tier

active

30nm

m1ILD

100nm

Fig. 1. Side-view of 2-tier Monolithic 3D IC structure (with seven metallayers in each tier)

There have been very few studies on 3D PDN design specificto monolithic 3D ICs. Wei et al. have shown that PDN helps inreducing the temperature in monolithic 3D ICs with an example ofOpenSPARC T2 processor core [4]. Though the presence of PDNhelps in improving the thermal conductivity and reduces maximumtemperature, they assume the same power dissipation of the blockswith or without PDN, ignoring its impact on increased congestionduring signal routing. This congestion results in increased signalwirelength and hence increased net power especially in moderntechnology nodes. Also, their power simulation has been carriedout at the architectural level. Another work on power supply inmonolithic 3D IC focuses only on cross power domain interfacedesign for multiple power domains and does not cover any powerdelivery network designs [5].

Other 3D PDN works focus only on TSV-based 3D ICs or 3D PDNsimulation and analysis techniques. A 3D IC floorplan and power-ground co-synthesis tool is developed in [6]. However, only blocklevel floorplanning and power/ground design is considered for TSV-based 3D designs. There is no discussion on the PDN inside theblocks. The total intra-block wirelength heavily dominates the totalwirelength in any design.Therefore, we need to consider the routingresource usage inside the blocks to have a correct estimation andobtain the best PDN design. In other recent works, Luo et al. havedeveloped 3D IC power delivery networks benchmark for researchpurposes [7]. They have covered various sizes of 3D designs but allof them are TSV-based and at the block level. System level powerdelivery design comparison for 2D and TSV-based 3D ICs has beendone in [8]. None of the above works consider the full chip impactof PDN design on monolithic 3D ICs. Gate-level monolithic 3D ICspresent great power and performance benefits and therefore, it isimportant to study any factors influencing these benefits.

In this paper, we study the impact of PDN on monolithic 3DICdesign QoR and develop various PDN design techniques to reduce the

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Fig. 2. OpenSPARC T2 layouts in monolithic 3D. The top row is theplacement/floorplan in each tier and the bottom row shows the overall signalnet routing. PDN is not shown in routing for clarity.

adverse effects. The major contributions of this work are as follows:• This is the first work to identify and study the impact of power

delivery network in monolithic 3D ICs for gate level designs. Inparticular we show that PDN affects monolithic 3D ICs moreseverely than 2D ICs in terms of wirelength increase and henceinterconnect power increase.

• We study the thermal impact due to the presence of PDNin monolithic 3D ICs and show that though PDN helps inimproving lateral conductivity, the increase in power due toincreased signal interconnect dampens this effect.

• We study simple yet effective PDN design techniques to reduceits impact on wirelength and power increase without exceedingthe IR drop budget.

• We propose efficient power delivery network design guidelinesspecific to monolithic 3D ICs to reduce this impact withoutexceeding the IR drop budget of a given circuit.

II. DESIGN AND ANALYSIS SETUP

For our study, we implement two benchmark circuits and analyzethe PDN impact on physical design for 2D and monolithic 3D.The first one is a single core gate-level design implementation ofOpenSPARC T2 [9] and the second one is Advanced EncryptionStandard (AES) circuit obtained from OpenCores [10]. We use 28nmtechnology library for all the designs. The 2D physical design iscarried out using standard layout techniques in Cadence Encounter.For the 3D designs, the same netlist is used but the 2D footprint areais first reduced by half and memory is partitioned and planned. Inorder to place similar number of cells as 2D in half the footprint, theplacement capacity is doubled and the placement engine is run [11].This is followed by placement driven partitioning which gives ustwo separate tiers with normal placement capacity. Since, the focusof our study is the impact of PDN on the full design, any goodpartitioning methodology will suffice. After that, we perform tier by

metal top

metal Int

metal 1

(a) section of PDN mesh

(b) power MIV array (at periphery of module)

metal 1

(top tier)

metal top

(bottom tier)

power MIV

Fig. 3. (a) Section of Power/Ground mesh structure (top), (b) a Power MIVarray at periphery (bottom).

tier routing to get the final designs. Two types of 2D and 3D designsare obtained with similar placement of cells. One is routed withoutany power or ground wires in the metal layers, while the other onehas power/ground wires in the relevant metal layers. The circuits aredesigned to meet similar timing constraints in both 2D and 3D and aretherefore iso-performance designs. Power analysis is carried out onthese iso-performance designs using Synopsys PrimeTime. Figure 2shows the placement and routing of both the tiers of T2 benchmark.Power/ground wires are not shown for clear view of signal routing.3D designs consume less power than 2D due to reduction in signalwirelength (Table I).

We use standard power delivery design techniques for our studywhich uses topmost metal layer for global wires and then intermediatemetal layers to connect to the metal1 VDD and VSS rails [12]. Thedensity of power/ground wires is decided such that the maximum IRdrop in 2D designs is limited to 5% of the supply voltage whichis 1.05V for our library. We use the same pitch of PDN wires in3D designs as well and then perform comparisons. It is to be notedthat our benchmarks are parts of larger SoC designs and thereforeform modules or cores of a bigger design. The power supply to suchdesigns is delivered mostly through ring connections at the peripheryof the chip and not directly through the C4 bumps. These supplies arethen distributed using the intra-module PDN. The C4 bumps in flip-chip designs supply power to the full SoC which in turn distributes itto these different modules. Also different designs use up to differentmetal layers depending on the design density and routing resourcerequirement. Cost is directly proportional to number of metal layersused. Therefore, it is important to optimize the number of metallayers in each module or core. We use a maximum of seven metallayers for the T2 design and five metal layers for AES design. Thesenumbers are determined after performing experiments to verify thetotal routing requirement.

For the OpenSPARC T2 single core benchmark, metal7 is used forhorizontal wires and metal4 for the intermediate vertical wires in the

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(a) without any PDN (b) with VDD and VSS stripes

(c) signal MIV landing pad locations constrained

metal 1(top tier)

metal top(bottom tier)

Poly

Active

ILD

signal MIV

VDDVDD

VSSVSS

VDD

VDD

Fig. 4. Impact of PDN on MIV landing pads a) MIVs freely distributedwithout any PDN blockages in top metal b) PDN blockages affect MIVs intop metal c) Isometric view showing the constraints on signal MIV landingpad locations in top metal and metal1 of the next tier.

power/ground mesh. The preferred orientations are used as specifiedin the technology. 40% of the top metal and 20% of the intermediatemetal is used for PDN. The top metal power/ground wires are madewider while the intermediate metal4 wires are relatively less wide.The frequency of occurrence of the wires are determined by thepercentage usage as mentioned earlier and all the wires are placedequidistant from each other. The VDD and VSS rails run on metal1cell rows as usual. The bottom-most intermediate layer which hasPDN wires should always run orthogonal to metal1 power/groundrails to ensure full connectivity. This is because a similarly orientedwire can completely overlap with some metal1 rails and they willnot get connected if polarities are different. For the AES designwhere five metal layers are used, metal5 is used for the horizontalpower/ground wires. All the designs are circumscribed with VSS andVDD rings where the external supply is input to the design.

For 3D designs, 3D power ground connections are in the form ofMIV arrays distributed along the periphery (Fig 3). Since a singleMIV is extremely thin, it presents very high resistance to the supplypaths. Therefore, a cluster of such MIVs is used for a single supplyconnection. We use 15 x 15 arrays which consume an area of almost3µm x 3µm. Such arrays are not placed inside the area of thedesign because it consumes extra silicon area, and as we observelater, reduced footprint in 3D designs helps to keep the maximum IRdrop at the central locations well within limits.

We carry out full IR drop analysis using Cadence VoltageStorm. 3Dtechnology files are generated to allow the tool to carry out 3D Ir dropanalysis. The 3D technology file has the basic stack-up informationalong with vertical stretch of the ILD and MIVs connecting the twotiers of monolithic 3D IC. Current sources are placed in the respectivemetal1 rails of each tier and the full two-tier IR drop analysis iscarried out. The values of the current sources are determined usingthe detailed cell-level power analysis results from PrimeTime. For3D designs, it is always the tier away from the C4 bumps or externalsupplies which are affected most. In our case, the bottom tier of

Fig. 5. Impact of PDN on (a) Wirelength and (b) Total Switching Power for2D and Monolithic 3D designs

Figure 1 shows maximum IR drop since it is away from the externalpower supply input which is on the top metal of top tier.

III. NEW POWER DELIVERY ISSUES IN MONOLITHIC 3D ICS

A good power delivery network with tolerable IR drop is essentialin the design of any integrated circuit. In general, the top metallayer(s) is completely dedicated for power delivery depending on thenumber of supply voltages required for the design. Instead of havinga long via stack to metal1 VDD and VSS rails which connect directlyto the standard cells, one or more intermediate metal layers are alsoused in between to redistribute the supply and reduce the resistivedrop [12]. Because of the usage of these metals for PDN, there areless routing resources for signal nets. This results in many detours forsignal nets and hence increased wirelength. This increased wirelengthand coupling results in more net power dissipation.

A. Impact of PDN

Top metals are usually thick and wide and are not used forsignal routing in traditional 2D designs. Therefore, using a significantportion of these metal layers for power delivery does not affect theoverall signal interconnect length. The other intermediate metal layersare not heavily used up by PDN (˜20%) and therefore the overallimpact is not very severe. However, for 3D designs, the top metal ofthe bottom tier is very important during signal routing because all the3D connections (TSVs or MIVs) run from this metal layer and move

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TABLE IDETAILED COMPARISON OF IMPACT OF POWER DELIVERY NETWORK ON 2D AND 3D DESIGNS. ALL % NUMBERS ARE EVALUATED RELATIVE TO THE

RESPECTIVE W/O PDN DESIGN.

Design Style Footprint Wirelength No. of MIVs Switching Power Internal Power Total Power IR Drop (mV)(µm x µm) (m) (mW ) (mW ) (mW ) Maximum Average

OpenSPARC T2 - Single Core

2D w/o PDN 1600 x 1600 17.89 - 458.4 169.2 754.3 - -w/ PDN 19.12 (+6.9%) 478.9 (+4.5%) 173.9 779.4 (+3.3%) 48 30

3D w/o PDN 1140 x 1140 15.33 140546 370.5 159 642.9 - -w/ PDN 17.09 (+11.5%) 116727 (-16.9%) 400.1 (+8.0%) 162.7 676.1 (+5.2%) 29 15

AES

2D w/o PDN 750 x 750 3.64 - 169.7 63.6 247.0 - -w/ PDN 3.90 (+7.1%) 175.4 (+3.4%) 63.9 253.0 (+2.4%) 46 26

3D w/o PDN 540 x 540 3.02 57442 143.1 65.7 222.5 - -w/ PDN 3.64 (+20.5%) 47850 (-16.7%) 165.1 (+15.4%) 66.8 245.6 (+10.4%) 28 16

up to the metal1 landing pads of the next tier above. For very few 3Dconnections like in TSV-based 3D designs, the presence of blockagesin top metal is not very critical. On the other hand, monolithic 3DICs allow tens of thousands of 3D MIVs and therefore face seriousrouting blockages when top metal is used up for power delivery.For example, all signal MIVs in Figure 1 require metal7 of bottomtier. Unavailability of continuous free routing area in these top metallayers results in heavy reduction in MIV count which diminishes thehuge benefits of monolithic 3D over 2D.

Figure 4 shows the magnified view of top metal layer of a circuitdesigned with and without power delivery network. The same regionsof the layout are shown in both (a) and (b). The MIV planning andinsertion is carried out by combining the individual tiers togetherand using commercial routing tools to get the via locations [11].Since normal routing tools allow multiple via insertion for eachnet, we get multiple MIVs per 3D net. The presence of power andground rails prohibits the MIVs from getting freely distributed asexplained in Figure 4(c). In the following subsection, we present 2Dand monolithic 3D design results to validate this fact.

B. PDN Analysis Results

Table I shows the detailed results and comparison of the impact ofpower delivery networks on 2D and monolithic 3D designs. Figure 5highlights the major metrics affected and the degree to which theyaffect the designs. The OpenSPARC T2 single core has many memorymodules and hence leakage power is a significant portion of the totalpower. Also there are many memory to logic connections which arenot affected much in 3D over 2D. Therefore, the overall increase inpower due to extra interconnects is not very bad, but it is still worsethan the corresponding 2D design degradation. Figure 6 shows themetal usage for signal routing of all the metal layers except metal1in the bottom tier of monolithic 3D T2 design. The bottom tier iscritical because its top metal is used heavily for signal MIV insertion(Fig 1). It can be clearly observed from Figure 6 that due to thepresence of PDN, the density of overall routing reduces significantlyfrom metal4 to metal7. While metal4 and metal7 have the actualpower/ground mesh, the presence of large via arrays in metal5 andmetal6 to connect these wide wires prohibit continuous signal routingin these layers as well. This can be better visualized by observingthe uniform routing in the bottom row of Figure 6 compared to thedense routing in the top row which has routing completed without anyPDN blockages. Though, the usage of metal2 and metal3 becomesmuch more in the designs with PDN blockages, it is not able tocompensate for the loss in routing resources in the top metals and alsoresult in increased coupling parasitics. Figure 7 gives a closer lookat the metal7 and metal4 layers with and without PDN blockages.

The density of routing and the placement of MIVs can be clearlydifferentiated in the two cases. The IR drop is more for 2D thanin 3D designs because we use peripheral supply connections andfootprint of 3D is 50% less that that of 2D. This results in reductionof overall drop as we move towards the center of the layout.

The AES benchmark is a pure logic circuit and interconnect powercontributes significantly to the total power consumption. Therefore,we see more severe impact on the AES case where the overallwirelength rise in 3D due to presence of PDN is 20.5% comparedto 7.1% in 2D. This increase results in an extra 8% overall powerincrease when compared to the relative increase in 2D. Also, weuse only up to five metal layers in AES and therefore, the routingresources are more constrained. The major difference in impact ofPDN compared to 2D comes from the top metal layer blockages,which reduces the 3D connections and hence diminish the potential3D benefits.

IV. THERMAL IMPACT OF POWER DELIVERY NETWORK

A. New Issues

Thermal issues have remained one of the major challenges of 3DIC design. All the potential benefits which 3D IC gives over 2Ddesigns in terms of power savings, wirelength reduction, footprintarea reduction and increase in bandwidth are of no use if the chiptemperatures are above tolerable limits. Due to stacking of multipledevice layers, the power dissipation per unit area increases by thesame factor as number of tiers. It is therefore essential to carry outdetailed thermal analysis of the various 3D designs and try to reducethe maximum temperature as much as possible.

The device layers are extremely thin in monolithic 3D ICs and thereis negligible lateral conductivity at the source of power dissipation.As discussed earlier, Wei et al. [4] demonstrated that the presenceof thick PDN metal helps in improving the lateral conductivity andreducing the maximum temperature. However, the power simulationswere done at architectural level and do not take into account thefact that PDN present in the individual modules increases the netswitching power as demonstrated in the earlier section. This powerrise offsets the conductivity enhancement brought about by the thickand wide power/ground wires. In this section, we re-establish thefact that PDN indeed helps in improving the temperature profileand reducing the maximum temperature, but the overall improvementcompared to a no PDN design case is affected by the switching powerincrease due to increased signal wirelength and coupling.

B. Temperature Results and Discussions

We carry out detailed full chip thermal analysis with the helpof ANSYS Fluent and supporting scripts to generate the required

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metal 2 metal 3 metal 4 metal 5 metal 6 metal 7

Fig. 6. Complete signal routing from metal 2 - metal 7 in the bottom tier (tier with MIVs on top metal) of the two-tier monolithic T2 design. The top rowshows the routing done without PDN blockages and the bottom row shows routing after PDN blockages

metal 7 metal 4

Fig. 7. Closer look at the signal routing in the metal layers with the PDNmesh. The top row shows the routing done without PDN blockages and thebottom row is routing with PDN (solid line) blockages

input files for Fluent. Our thermal analysis tool considers all thelayers in the technology and assigns conductivity to each individualtile of the 3D mesh. A full GDS analysis is carried out to knowthe exact position of the active, poly and signal and PDN metallayers in each tier. For each tile, weighted conductivity is assigneddepending on the materials which fall in that tile. For example, a tilemay have some portion as Si02 and some portion as metal and theaverage conductivity is assigned based on the volume occupied byeach material. Conventional heat sink and heat spreader are used onthe side of the handle bulk (Fig 1 in flip-chip). The power dissipationoccurs only at the device layers of each tier. These power numbersare obtained for each individual cell using PrimeTime analysis. The2D tile size used for each layer in the stackup is 20µm x 20µm.

TABLE IITHERMAL ANALYSIS RESULTS OF THE 3D DESIGNS. MAXIMUM

TEMPERATURE VALUES ARE REPORTED (IN oC). ROOM TEMPERATURE IS27oC . % NUMBERS ARE CALCULATED W.R.T. RISE ABOVE ROOM IN W/O

PDN CASE.

w/o PDN w/ PDNw/o PDN conductivity w/ PDN conductivity

T2 52.81 55.72 (+11.3%) 53.99 (+4.6%)AES 58.7 63.89 (+16.4%) 62.04 (+10.5%)

We evaluate three different cases for our benchmarks. The firstcase is the 3D design which has no power delivery network. In thesecond case, we use the 3D design with power delivery networkand the corresponding power dissipation numbers, but we ignore theconductivity of the metal wires used for PDN. For the third case, weuse the same design and power as the second case but now the PDNwires are included while assigning the conductivity values to eachtile. We handle this by modifications to the post-routing GDS files.We use the second case to isolate the impact of PDN in conductivity.

Table II shows the maximum temperature values for each of theevaluated cases. The maximum temperature occurs at the device layeraway from the heat sink. The full tier temperature maps for theselayers are shown in Figure 8. The cooler rectangular regions for theT2 temperature maps are the memory modules in the design whichhave lower power density compared to the rest of the design. Oncomparing the second and third columns in the figure, we observethat PDN indeed helps in improving the temperature profile by around7% by enhancing the lateral conductivity close to the device layers.This is in agreement with [4]. However, the situation is still worsethan designs with no PDN in it. This can be explained easily bythe fact that there is a power increase from 3D w/o PDN to 3D w/PDN which is 5.2% for T2 design and 10.4% for AES (Table I).While PDN metal does play an important role in enhancement ofconductivity, it is very important to include the negative impact ofpower increase because of PDN.

V. POWER DELIVERY NETWORK OPTIMIZATION

In this section, we explore different power delivery network designsin monolithic 3D ICs to reduce its impact on 3D signal routing. The

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52 oC

64 oC

44 oC

56 oC

w/o PDN w/ PDN

conductivity ignored

w/ PDN

conductivity considered

(a)

(b)

Fig. 8. Top Tier (away from heat sink) temperature maps for (a) T2 design and (b) AES design. The actual dimensions are normalized. Note that the middlecolumn is having the same power dissipation as the right column but does not consider the enhancement of conductivity because of PDN.

TABLE IIISUMMARY OF METAL USAGE IN THE VARIOUS ALTERNATIVE PDN

DESIGNS (T2 BENCHMARK). ALL THESE CHANGES ARE DONE TO THEBOTTOM TIER ONLY I.E. THE TIER WITH MIV LANDING PADS ON TOP

METAL.

PDN Design Metal 7 Metal 6 Metal 5 Metal 4baseline 40% - - 20%modified 40% - - 20%less topmetal 20% - - 20%multiple metals 10% 10% 10% 20%intermediate metals Rings Only - 40% 20%no topmetal Rings Only - - 20%

maximum IR drop of the design has to remain within the specifiedbudget while using any other power/ground layout. We use verysimple yet effective changes to the existing PDN, which helps inproviding more free areas for MIVs in the top metal, while keepingthe IR drop under control. We utilize the fact that IR drop for 3Ddesigns is less than that of 2D designs to our advantage (Table I). Wespecify the maximum allowed IR drop as 5% of the supply voltagewhich is around 50mV for our design library.

A. Design Styles

Table III summarizes the various PDN design styles used for fullchip impact analysis along with the percentage of metal layers used.The first modification we make is bringing the power and groundrails together instead of having all of them equally spaced. Figure 9explains this modification. The purpose is to provide more unblockedspace for MIV routing and to avoid long detours. By using this type oftechnique alone, we save up to 2.6% in switching power (Table IV).All other design styles discussed later use this modification. Thistechnique can also be used in 2D ICs, but it will not be as effective asvery less top metal is used for signal routing. The other design stylesinclude reduction of top metal layer usage for PDN and compensationwith PDN wires in other metals below. As pointed out earlier, wetake advantage of the fact that 3D designs have lesser footprint than

VDD

VDD

VDD

VSS

VSS

VSS

VDD

VDD

VDD

VSS

VSS

VSS

baseline modified

Fig. 9. Baseline PDN vs Modified PDN. Note the extra continuous spacebetween the red top metal wires which enhances MIV insertion and routing.The yellow wires are on intermediate metal.

2D and therefore, we can relax the density of PDN wires and stillsatisfy the specified the IR drop budget. The design less topmetalreduces top metal usage to half that of the baseline. Multiple metalsuses the metal layers between the top and intermediate metals usedfor the PDN in baseline. Only the intermediate metal layers areused in intermediate metals. They are connected to the input on topmetal through rings only. The final case no topmetal uses only oneintermediate metal layer for PDN and is connected to supply throughrings in the top metal. Even though this is impractical PDN designfrom an IR drop perspective, nevertheless we implement it and studythe full chip impact. Similar to earlier sections, we use PDN in metal4as the common intermediate metal used across all design styles. T2designs use metal7 as top metal while AES uses metal5 as top metal.Therefore, the design styles multiple metals and intermediate metalsdo not apply to the AES benchmark.

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TABLE IVWIRELENGTH AND POWER COMPARISON OF VARIOUS OPTIMIZED 3D PDN DESIGNS. THE FOOTPRINT AREA IS SAME FOR THE SAME BENCHMARK. THE

% NUMBERS ARE EVALUATED W.R.T. THE BASELINE PDN.

PDN Design Style Wirelength No. of MIVs Switching Power Internal Power Total Power IR Drop (mV)(m) (mW ) (mW ) (mW ) Maximum Average

OpenSPARC T2 - Single Corebaseline 17.09 116727 400.1 162.7 676.1 29 15modified 16.86 (-1.31%) 118121 (+1.19%) 398.0 (-0.53%) 162.7 673.3 (-0.41%) 29 15less topmetal 16.89 (-1.14%) 128715 (+10.27%) 395.2 (-1.23%) 162.0 670.3 (-0.86%) 55 23multiplemetals 16.75 (-1.96%) 132205 (+13.26%) 394.7 (-1.35%) 161.8 669.9 (-0.92%) 39 18intermediate metals 16.46 (-3.70%) 136156 (+16.65%) 395.6 (-1.13%) 161.8 671.0 (-0.75%) 32 14no topmetal 16.08 (-5.90%) 137173 (+17.52%) 383.8 (-4.07%) 160.7 657.8 (-2.71%) 214 46

AESbaseline 3.64 47850 165.1 66.8 245.6 28 16modified 3.56 (-2.19%) 47970 (+0.25%) 160.8 (-2.61%) 66.6 241.2 (-1.79%) 28 16less topmetal 3.35 (-8.05%) 55311 (+15.59%) 153.1 (-7.27%) 66.3 233.1 (-5.09%) 45 17no topmetal 3.35 (-8.05%) 56954 (+19.03%) 152.7 (-7.51%) 66.3 232.7 (-5.25%) 69 22

baseline less topmetal

Fig. 10. Signal routing for top metal of bottom tier (T2 design) after reducingPDN wires along with clustering of VDD and VSS wires (less topmetaldesign)

B. Full PDN Analysis Results

With the various PDN design styles, we carry out detailed signalrouting and power analysis to analyze the improvement. The full chipimpact of the different power delivery design styles are summarizedin Table IV. The baseline PDN is treated as reference and allpercentage numbers are reported w.r.t this baseline. The IR dropvalues are also reported in the last two columns. The wirelength andpower improvements are more pronounced in the AES benchmarkthan the T2 benchmark because of the contribution of switchingpower to the total power. A significant portion of power in T2 isleakage and therefore, the observed improvement in total power isnot very significant. But for designs like the AES benchmark, anyimprovement on wirelength translates to high power reduction.

We observe that simple modifications to the existing PDN can bringabout significant reduction in wirelength and power. In addition, 3Dimplementation helps us to reduce the density of PDN which furtherfacilitates the use of top metal layers for 3D signal routing. Figure 10shows the massive improvement in signal routing density in top metalof bottom tier when we allow more space. Not only does it helpin adding more vias, it also provides sufficient space for routingwithout unnecessary detours. The less topmetal design shows verygood improvement especially in the AES benchmark which has highcontribution from switching power. We save up to 8% wirelength and5% power by just reducing the density of PDN usage in top metal.The maximum IR drop is still better than the worst IR drop in 2Ddesign case (Table I). The design case intermediate metals shows very

baseline modified

less topmetal no topmetal

Fig. 11. Comparison of IR drop across various PDN styles of bottom tier inAES design. Red regions are above 50mV. Rest of the colors are within theIR drop budget of 5% of VDD

good improvement in the MIV count and wirelength but switchingpower increases slightly compared to less topmetal due to morecoupling. The multiple metals case also gives good improvement.The no topmetal design is similarly affected by PDN as in normal2D designs and though is attractive from power perspective, it is notpractically feasible due to huge IR drops.

The detailed IR drop maps for all four AES designs are presentedin Figure 11. The scales are set such that all areas above the 5%VDD limit are red in color. IR drop increases as we move towardsthe center because the supply connections are present in the peripheryonly. As mentioned earlier, no topmetal design violates this limit. Thepattern of IR drop in this case follows vertically elongated profilesunlike concentric profiles in other maps because the intermediatepower/ground wires run vertically. All other design styles satisfy the

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baseline less topmetal

Fig. 12. AES top tier (away from heat sink) thermal maps for baseline PDNvs PDN design with less top metal used. The temperature scale is kept sameas Figure 8

IR drop requirement well within the limits. The supply connectionsare along the periphery and the PDN of the two tiers in 3D IC areconnected using P/G MIV arrays used at the periphery only. Thebaseline and modified designs have the same IR drop values becausethe density of the PDN remains the same. Only the VDD and VSSwires come closer to each other.

We also evaluate the temperature improvement brought about bythese design changes in power delivery networks. Since there isreduction in power, the maximum temperature reduces even thoughthere is slight decrease in PDN wires. Figure 12 shows the AESdesign temperature maps for the tier away from the heat sink. The leftmap is the baseline and is same as the one shown earlier in Figure 8).The right map is the temperature map for the less topmetal designcase. The maximum temperature rise above room drops from 35oCto 33.2oC amounting to a 5% temperature reduction.

VI. PDN DESIGN GUIDELINES FOR MONOLITHIC 3D ICS

In this section, we summarize all the key findings from our studyand propose some general guidelines which are very simple yet highlyeffective to control the impact of power delivery networks on theoverall power and temperature in monolithic 3D technology. Withthe advancement in the sequential integration technique, mass scalemonolithic 3D IC production is expected in the near future. Theseguidelines will help monolithic 3D IC designers to maximize the 3Dbenefits without any significant impact of the power delivery network.

While designing power delivery network for monolithic 3D ICs,the fundamental thing to be always kept in mind is that the top metalof the lower tiers are heavily used for signal MIV landing pads (Fig 1)and therefore cannot be fully utilized for PDN as done in 2D designs.The proposed design guidelines are as follows:

1) It is necessary to first identify whether the given design isinterconnect dominated or memory dominated. If the design isdominated by interconnects, monolithic 3D IC presents hugebenefits by reduced wirelength. Power Delivery Network needsto be designed much more carefully for these cases. On theother hand, for memory dominated designs, leakage contributessignificantly to the total power and PDN will not have a verysevere impact on the total power increase and their design canbe more flexible. However, we need to pay special attention tomemory PDN connections.

2) The top metal needs to be given more free area for optimalMIV placement and therefore power/ground wires’ density intop metal layers has to decrease. The PDN wires removed from

top metal can be compensated by using some wires in the metallayers below.

3) It is always better to have different power/ground supply wiresclustered together and then these clusters equally spaced on therespective metal layers rather than all of them being individualspaced equally from each other. This allows more continuousroom for signal routing and MIV planning even though thepercentage of routing blockages remains the same. Also the IRdrop is not affected at all in this case as the amount of supplyconnections remain the same.

4) Depending on the area and the overall current demand, thefrequency of PDN wires as well as the number of total metallayers used for a given module can be optimized to reduce theimpact of PDN blockages on signal routing within the IR dropbudget. Larger designs will need more power/ground wires tosatisfy the IR drop budget if we have connections only at theperiphery.

VII. CONCLUSION

We studied the full chip impact of power delivery network inmonolithic 3D ICs in detail and demonstrated that the impact is moresevere compared to simple 2D designs. The impact is more severefor logic-only and interconnect dominated designs where interconnectswitching power is a major contributor to total power. We also analyzethe role of PDN in the full chip thermal behavior. As pointed out inearlier works, our study re-establishes the fact that PDN does helpin enhancing lateral thermal conductivity in monolithic 3D IC andhence results in temperature reduction. But we also find that there isincrease in power dissipation due to increased signal wirelength andthis must be taken into account for accurate temperature analysis.Simple yet efficient PDN design styles are evaluated to show goodimprovements in wirelength and power and some general guidelinesfor PDN design in monolithic 3D ICs are proposed.

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