Full-Custom Design Migration with MunEDA …...2014/05/07 · STMicroelectronics - Optimization of High-Speed I/O circuits in 28nm 20 28nm DDRx High-Speed I/O Task: Reduce jitter

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Full-Custom Design Migration

with MunEDA WiCkeDTM

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MunEDA WiCkeDTM SPT Schematic Porting Tool - Agenda

Challenges of IP Re-use & Circuit Migration

State-of-the-art: Manual Schematic Porting

MunEDA Circuit Migration Flow

Schematic Migration

Re-Sizing and Verification

Summary

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Full-custom design porting - Introduction

Porting designs between process technologies efficiently and correctly is a key challenge of IC design.

Horizontal porting = Migrating designs from one technology node

to the same node of a different foundry Second sourcing Fab consolidation Foundry migration Foundry interoperability

Vertical porting = Migrating designs from one technology node to a smaller one (usually of the same foundry) New product generation

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Design Migration Challenges

State of the art Digital IP reuse on ESL, RTL level Layout migration for memory, std cell lib Manual design migration for analog/mixed-signal/RF

Migrating full-custom AMS/RF is a major challenge

Many blocks (whole SoC) to be migrated in a short time No simple shrinking rule.

Blocks need simulation, adjust geometries, modify biasing, … to meet specs The circuit topology may need modification due to new process, Vdd, new

specs Some devices (mimcaps, inductors, …) may or may not be available in the

target PDK, or only of a quite different type

AMS/RF: Specification-driven Design Migration 1. migrate the schematic to the new PDK 2. adjust topology and geometries to meet specs 3. recreate the layout

Improve Design Performance & Yield

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MunEDA WiCkeD & SPT supports a Full-Custom IP Porting and Re-Sizing Workflow

The generalized design flow follows 3 major steps 1. Schematic Porting or IP Re-use 2. Design Assessment (Analysis & Verification) 3. Sizing & Sign-off (Circuit Optimization: Sizing and Design Centering)

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State-of-the-art: Manual Schematic Porting

To migrate a schematic between PDKs, you have to 1. track property values of every single device in the full schematic

hierarchy, 2. Close Design Framework, replace source PDK with target PDK,

restart Design Framework 3. Delete and recreate every device instance with adapted property

values in the new PDK. Rewire is symbol shape is different.

That‘s infeasible to do by hand designers write scripts, try dangerous shortcuts.

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Manual Schematic Porting

Popular mistakes with manual schematic porting

keep two PDKs open simultaneously high risk of wrong callback execution, wrong values in OA database, difficult to detect and debug

replace lib/cell name in property editor will leave traces of old property values in the database with high risk of side-effects

untested Skill scripts hacked ad-hoc by designers lots of bugs, few features, limited to one PDK, no professional support

High risk of hard-to-find design bugs and wasted time

Needs a systematic approach MunEDA SPT

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Fast Schematic Porting with MunEDA SPT Schematic Porting Tool

MunEDA SPT performs automatic & fast schematic migration replaces devices in the schematic with their counterparts Recalculate property values by rules (configurable)

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MunEDA SPT Implementation & Interfaces

MunEDA WiCkeD SPT performs schematic migration replaces devices in the schematic with their counterparts

(source PDK target PDK) recalculates the properties of target cells according simple rules performs mapping of terminals, if they have different positions rotates/mirrors devices to match terminals Simplifies wiring after removing terminals, adds wires to connect

new terminals stretch the schematic by factor of 2, if the symbols of target PDK

is larger than ones of source PDK

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Conversion of devices with Pins differences

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40nm (Source PDK) → 28nm (Target PDK)

crtmom (3-pins) cfmom_2t (2-pins) nch_mac (bulk pin centered) nch_mac (bulk pin shifted)

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Conversion of the devices with additional Pin

40nm (Source PDK) → 28nm (Target PDK) rppolywo (2-pins)

rupolym_m (3-pins)

created additional wire

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Schematic stretching by factor 2

40nm (Source PDK) → 28nm (Target PDK) after stretching by factor 2

* Check option “Stretch Schematic”

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MunEDA SPT Implementation & Interfaces

Advantages of using MunEDA WiCkeD SPT tool Correct and repeatable replacement of instances guarantees

database consistency. Fast: Migrates 1000s of devices in seconds, hierarchically. Flexible property mapping, configurable, automated shrinking,

can map net expressions to properties, can handle MOS, R, C, inductors, varactors, …

Flexible symbol and terminal mapping, removing/adding terminals

Generates conversion report Shows every mapped instance, selected properties and values

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MunEDA WiCkeD & SPT supports a Full-Custom IP Porting and Re-Sizing Workflow

The generalized design flow follows 3 major steps 1. Schematic Porting or IP Re-use 2. Design Assessment (Analysis & Verification) 3. Sizing & Sign-off (Circuit Optimization: Sizing and Design

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Numerical Sizing in Advanced Circuit Design

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Parasitic Extraction Layout Simulation

(sweeps, MC, corners, …)

Sizing by formula

Topology design

Numerical Sizing

=adjusting device parameters

(W,L,R, …) based on simulation

results

Done

Traditional analog design method: Simulation is used as a verification tool only, but not as a design tool.

Numerical sizing: Modify device geometries iteratively based on simulation results (after traditional initial design).

Circuit Sizing &

Optimization



Numerical sizing in the full-custom design flow

Numerical sizing has become a must-have for advanced circuit design

– High-speed I/O: transients, balancing over corners – RF: noise, jitter, power trade-offs – Complex OTAs: speed, stability, feedback loops – PMU: temperature, stability – Low power analog: specs vs. power trade-off – Memory interfaces: full-custom I/O, paths, sensing, …

Numerical sizing is critical for some products‘ KPI – Ultra low power design, mobile communication, medical,

near field communication, memories, FPGA

Manual sizing consumes a lot of designer‘s time – Experienced designers spending weeks of

manual tweak-simulate-tweak

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Circuit Sizing &

Optimization



Analog circuit migration: 50nm to 40nm

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Results published by HLMC at MTF Shanghai 2014



Semi-automated full-custom circuit sizing software

MunEDA tools address the challenges of circuit sizing – Scalable with sufficient capacity for relevant designs (>500 devices, >100

design variables, >10 specs, >200 constraints, …) – Efficient enough for circuits with long simulation time (>30min.) – User-defined sizing strategy – Multi-objective optimization, power & noise minimization – Multi-corner sizing – Support process variation & mismatch (design for yield) – Support aging simulation (constraints on device parameter degradation and

spec degradation) – Support FinFET – Multi-simulator support, batch mode sizing

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Customer Example – Sizing & Design Centering with MunEDA WiCkeD Optimization Tools TOP Microprocessor Company - Using MunEDA tools to optimize AMS/RF IP in 65nm

TOP Microprocessor Company - RF receiver path in advanced node – Task: reduce power consumption while keeping noise low – To see the noise vs power trade-off, the complete path has to be considered – Circuit size: ~2000 MOS, ~8000 parasitics.

Simulation time: 40min. for a single run (dc+pss+pnoise) – Optimization complexity: 80 specs, 50 design parameters

Three process corners + temperature + Vdd

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Block 1 Block 2 Block 3 Block 4

Noise matching between blocks

power

Results: • Power consumption significantly

reduced. • Sizing task performed completely

automatically. • Designer attention time is reduced

from 4 weeks to a few hours.



Customer Example – Sizing & Design Centering with MunEDA WiCkeD Optimization Tools STMicroelectronics - Optimization of High-Speed I/O circuits in 28nm

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28nm DDRx High-Speed I/O

Task: Reduce jitter and duty cycle Challenge: Manual tuning

takes 2 weeks

Solution: Use MunEDA Sensitivity Analysis and Corner Optimization

Results published by STMicroelectronics at MUGM 2011

Design Time reduced from 2 weeks to only 3 hours Corner spread reduced by 50%

Easy analysis of circuit sensitivities



Customer Example – Batch mode sizing of FinFET Memory Interfaces (SAMSUNG)

Circuits: General Purpose I/O (GPIO) and Memory Interface macros

Goals: Improve Accuracy Reduce Design Time

Solution: Batch mode I/O optimization with MunEDA WiCkeD DNO

Results published by Samsung at MUGM 2013

Result: Up to 60% design time reduction, 6% better performance, 15% less area

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Customer Example – Sizing & Design Centering with MunEDA WiCkeD Optimization Tools Altera - Post-layout optimization of FPGA lookup tables

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Circuit Description: FPGA LUT 40nm > 2,400 MOS

> 40,000 RC > 30,000 nodes

187 degrees of freedom 5 simultaneous runsets Transient simulation with

HSim

Task: Reduce area by 20%, but don‘t increase delays

Solution: Run WiCkeD FEA and DNO

Results published by Altera at MUGM 2010

Result: Area reduced by 22%, delays as good as initially.



Customer Example – Sizing & Design Centering with MunEDA WiCkeD Optimization Tools SKHynix - Digital Full-Custom Design – Path Delay Optimization in 28nm Memory (DRAM)

Circuit Description: – Receiver for DRAM Cells – 28nm Technology – 1300 Transistors

Issue: Timing Difference (Delay) of Pin-to-Pin-Skew caused by local variation is too high (simulation: 100ps; pre-silicon)

Goal: Optimize path delay to <15ps in silicon

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Solution Approach: 4 main analysis & optimization steps with MunEDA WiCkeD tools:

Path Delay (P2P Skew) reduced with WiCkeD from >100ps to 31,4 ps in simulation – corresponding to 14,7 ps in silicon (measured result)

Results published by Hynix Semiconductor at MUGM2009, MTF Korea 2011



Solution: MunEDA Nominal Optimization in Batch Mode

Customer Example – Sizing & Design Centering with MunEDA WiCkeD Optimization Tools Faraday – Batch-mode optimization of standard cells

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Standard cell: Clock buffers

Task: Balance slopes Challenge: many cell & process variants,

multiple slews and output loads, frequent model update

Complete automation reduces design time significantly.

Equal or better results than manual design.

Results published by Faraday at MTF Anaheim 2008



MunEDA Foundry Cooperations

TSMC OIP Member – SPT and optimization shown on OIP Forum Book 2012, with RF VCO

migration 65nm to 40nm – Performance Tuning and yield optimization shown in RF RDK 2.0

XFAB

– EDA Partner since 2007 – MunEDA tool configurations delivered inside foundry PDK

austriamicrosystems

Lfoundry

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MunEDA WiCkeDTM SPT Schematic Porting Tool

Industry’s first commercially-available automated porting solution

Automated schematic porting 10-100X faster than manual porting

Improves designers’ productivity and simplifies designers’ jobs

Consistently achieves repeatable and verified results Re-size porting results with MunEDA WiCkeD tools for

analysis, modeling and automatic sizing

SPT Schematic Porting Tool - User Benefits

Faster and more convenient porting with SPT Schematic Porting Tool

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Summary – Schematic Porting & IP Re-Sizing

Improved and automated flow for IP Porting & Circuit Migration using

MunEDA WiCkeD tools Fast Schematic Porting with new MunEDA SPT Schematic Porting Tool Efficient Re-Sizing with MunEDA WiCkeD Analysis and Sizing Tools Save Time and Efforts Make designer’s life more convenient and results reliable

MunEDA – Industry and Silicon proven solutions for IP Porting, Circuit Analysis, Modeling and Optimization

For more information please contact MunEDA with www.muneda.com

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Documents

Full-Custom Design Migration with MunEDA …...2014/05/07 · STMicroelectronics - Optimization of High-Speed I/O circuits in 28nm 20 28nm DDRx High-Speed I/O Task: Reduce jitter