Fundamental of FPGA Design Flow

by

Ass. Prof. Dr. Majid S.Naghmash Dijlah University College, Computer Engineering Techniques Department

2016

FPGA design flow

EDIF UCF

HDL of Activation System

FPGA / ADC / DAC

Synthesis : Convert HDL Code into FPGA based optimized netlist EDIF File (Electronic Design Interchange Format) and UCF File ( User Constraint File)

Translate : Merges the Netlist EDIF file with user constraint file UCF into Xilinx FPGA design file NGD ( Native Generic Database file )

Map : Map the logic defined by an NGD file into FPGA elements in NCD file NCD File ( Native Circuit Description file)

Place & Rout : Place and rout the design NCD file to the time constraint and produce PAR report ( place and rout report)

Programming File Generation : produce bit stream for FPGA Configuration BGN

EDIF UCF

NGD

NCD

PAR optimized NCD

BGN

FPGA

Implementation results

project status and device utilization summary generated by ISE Software

Mapping: NCD to Logic

Placing: Logic file to FPGA hardware architecture

Routing: convert the design to FPGA hardware and ruoting

No

Yes

No

No Yes

Yes

No

Yes

DSP modeling

Simulation of data flow at each stage of

DSP model

Generate HDL netlist of DSP model

Simulation of data flow at each stage of

HDL netlist of DSP model

START

HDL integration of DSP model netlist

and setup configuration

Simulation of data flow at each stage of

HDL integrated design

HDL design of setup configuration for

ADC, DAC, and clock synthesizer

Simulation of data flow at each stage of

HDL module of setup configuration

Result correct?

Result correct?

Result correct?

Result correct?

No Yes ModelSim

Environment

Xilinx

System Generator

+

Simulink (MATLAB)

Environment

Synthesis of HDL integrated design

Estimated timing simulation of

synthesized integrated design

Timing error? Increase latency at the

worst delayed path

Pin assignment of I/O ports on FPGA

2

2

2

Synplify Pro

Environment

1

Thank you for your attention!

Questions?