1
USN Time: 3 hrs. la. b. c. 2a. b. Fourth Semester B.E. Degree Examination, Dec.2013 lJan.2ol4 Fundamentals of HDL Max. Marks:100 06EC45 (06 Marks) (06 Marks) (08 Marks) (02 Marks) Marks) ) arks) Marks) o o o L a (.) o 3e N9 7r) oDr traa .= o.l rB+ Ho FO E= o> 3* a: oO =\ ad E(g ,(.) or= o; oj o: atE !o 6 .:i ooo Eil) o= *O tr> o ->r lr< :^ (J o z L E Note: Answer FIVE full questions, selecting at least TWO questions from each poit. PART _ A Cornpare VHDL and Verilog. What are values that std-logic (VHDL) and nets (verilog) can take? With proper example explain the logical operators of verilog. What are the facts of data flow description? 3a. b. Starting from the basics draw the logic symbol of D'latch exoitation table, K map circuit for D latch and write VI{DL and verilog program for the sr}me. (10 Marks) c. Write a data flow description (in both VHDL and verilog) of a full adder with enable. If the enable is low (0). the sum and carry are zero; otherwise the sum and carry are usual outputs of the adder. Use a 5 ns delay for any gate inoluding xor. Draw the truth table of this adder (08 Marks) (10 Marks) Write a program in VHDL and verilog for JK flip flop using if & else if statements. b. Write VHDL behavioral description of a tristate buffer. Use this as nent for and derive the Boolean function after minimization. With syntax explain different types of loops in VHDL and verilog. (10 Marks) 4 a. What is binding? Explain the binding between entity and components in VHDL and between two modules in verilog. (t0 Marks) 5a. b. structural of 2 to 4 decoder with tristate output. PART _ B Write VHDL procedure and verilog task for N-bit ripple caffy With suita-ble example write VHDL code for writing integers to a 6 a. Give an example of a VHDL package. b. write the block diagram and function table of a SRAM of 16x8 and writd the same. using two half adders. b. Discuss the facts and limitations of mixed language description. 8 a. Draw the flow chart and explain the steps involved in synthesis. b. Write a program in VHDL and obtain the gate level synthesis input and ADH is the output. BP varies from 0 to 7 and ADH that if BP is more than 5 the ADH is 0. For BP > 2 and less ADH:_5*BP+25 verilog code for , (12 Mark$ 7 a. How to invoke a verilog module from a VHDL module? Giving an example of a full adder ' --'--^D (10 Marks) (10 Marks) (10 Marks) for BP and ADH. BP is the varies from 0 to 16. Assume than 5 the ADH is given by (10 Marks) (10 Marks) (# f/. {<***{< For More Question Papers Visit - www.pediawikiblog.com For More Question Papers Visit - www.pediawikiblog.com www.pediawikiblog.com

Fundamentals of HDL Jan 2014

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Page 1: Fundamentals of HDL Jan 2014

USN

Time: 3 hrs.

la.b.

c.

2a.b.

Fourth Semester B.E. Degree Examination, Dec.2013 lJan.2ol4Fundamentals of HDL

Max. Marks:100

06EC45

(06 Marks)(06 Marks)(08 Marks)

(02 Marks)

Marks)

)arks)

Marks)

oooLa

(.)

o

3e

N97r)oDrtraa.= o.lrB+

HoFOE=

o>3*a:

oO

=\

ad

E(g,(.)or=

o;

oj

o:atE

!o6 .:ioooEil)

o=*Otr>o->rlr<:^(J

oz

L

E

Note: Answer FIVE full questions, selectingat least TWO questions from each poit.

PART _ ACornpare VHDL and Verilog.What are values that std-logic (VHDL) and nets (verilog) can take?With proper example explain the logical operators of verilog.

What are the facts of data flow description?

3a.b.

Starting from the basics draw the logic symbol of D'latch exoitation table, K map circuit forD latch and write VI{DL and verilog program for the sr}me. (10 Marks)

c. Write a data flow description (in both VHDL and verilog) of a full adder with enable. If theenable is low (0). the sum and carry are zero; otherwise the sum and carry are usual outputsof the adder. Use a 5 ns delay for any gate inoluding xor. Draw the truth table of this adder

(08 Marks)

(10 Marks)Write a program in VHDL and verilog for JK flip flop using if & else if statements.

b. Write VHDL behavioral description of a tristate buffer. Use this as nent for

and derive the Boolean function after minimization.

With syntax explain different types of loops in VHDL and verilog.

(10 Marks)

4 a. What is binding? Explain the binding between entity and components in VHDL and betweentwo modules in verilog. (t0 Marks)

5a.b.

structural of 2 to 4 decoder with tristate output.

PART _ BWrite VHDL procedure and verilog task for N-bit ripple caffyWith suita-ble example write VHDL code for writing integers to a

6 a. Give an example of a VHDL package.b. write the block diagram and function table of a SRAM of 16x8 and writd

the same.

using two half adders.b. Discuss the facts and limitations of mixed language description.

8 a. Draw the flow chart and explain the steps involved in synthesis.b. Write a program in VHDL and obtain the gate level synthesis

input and ADH is the output. BP varies from 0 to 7 and ADHthat if BP is more than 5 the ADH is 0. For BP > 2 and lessADH:_5*BP+25

verilog code for

, (12 Mark$

7 a. How to invoke a verilog module from a VHDL module? Giving an example of a full adder' --'--^D(10 Marks)(10 Marks)

(10 Marks)for BP and ADH. BP is thevaries from 0 to 16. Assumethan 5 the ADH is given by

(10 Marks)

(10 Marks)

(#f/.

{<***{<For More Question Papers Visit - www.pediawikiblog.com

For More Question Papers Visit - www.pediawikiblog.com

www.pediawikiblog.com