EC404USN 1 ILI S 0

M.S. RAMAIAH INSTITUTE OF TECHNOLOGY(AUTONOMOUS INSTITUTE, AFFILIATED TO VTU)

BANGALORE - 560 054SEMESTER END EXAMINATIONS - JUNE 2010

Course & Branch BE (Electronics and Communication ) Semester : IV

Subject Fundamentals of Verilog HDL Max. Marks : 100

Subject Code : EC404 D urat ion : 3 hr

Instructions to the Candidates:Answer one full question from each unit.

UNIT-I1. a) Explain the importance of HDL compared to the traditional methods of (10)

design. Describe a typical design flow for designing VLSI chips.b) What is a test bench? Write the structure of a test bench. Explain the (10)

difference between the following system tasksi) $monitor and $display ii) $stop and $finish

2. a) Distinguish between the following with examples. (12)i) Modules and instances.ii) Top down and bottom up approach.iii)' Design block and stimulus block.

b) Discuss the four different levels of abstraction in Verilog with examples. (08)

UNIT-113. a) Discuss different logical operators used in HDL. Illustrate each of them with (04)

an example.b) Write Verilog description using primitive gates for a 2 X 4 decoder with (08)

tristate output.c) Write Verilog code for a 4 bit ripple carry full adder in gate level modeling. (08)

The full adder is made up of two half adders. Write a test bench for verifyingyour code. Exercise at least five input combinations.

4. a) Explain the difference between : (06)i) Nets and registersii) Vectors and scalarsiii) Concatenation operation and Conditional operator

b) Design a full subtractor and write Verilog code for the same in Dataflow (10)style. Write a stimulus block to-verify this design using all eight possiblecombinations.

c) Which are the different types of delays associated with gates? Explain with (04)

examples.

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EC404

5. a)

UNIT-IIIDescribe a 4-bit shift register using 'if statements. The register should have (10)

)

a right/left control signal to control the direction of shift, a parallel loadfacility, and a serial and parallel output. Shift register has got an active highreset.What is the difference between a sequential block and a parallel block? 06)

c)

Explain using example. Can a sequential block apper inside within a parallelblock?Design a clock with time period 40 time units and a duty cycle of 25% by (04)

6. a)

using the `always' and 'initial' statements. The value of clock at time TO = 0.

Explain the use of non-blocking statement with the help of an example. (07)

b)Differentiate between a blocking and a non-blocking procedural assignment.Explain the syntax of `Generate' statement and the use of it with an (07)

c)example.Describe a priority 4-bit encoder using casex statements in Verilog. (06)

7. a)

Bit(O) or the LSB of the input has the highest priority.

UNIT-IVExplain the use of 'automatic function' in Verilog with the help of a Verilog (07)

b)code to compute factorial of a 4-bit number. Output is a 32 bit value.What are the differences between tasks and functions? (05)

c) Write a Verilog code which uses a function that calculates the parity of a (08)

8. a)

32- bit address and returns a one bit value.

What are Tasks in Verilog. Explain Task declaration and invocation. (07)

b) Define a `task' to compute area of a sphere, given the radius. (05)

c) Write a Verilog code for converting a fraction binary to real using tasks. (08)

9. a)UNIT-V

What is meant by RTL description? Design a 3:8 decoder using a Verilog (10)

b)RTL description.Discuss the synthesis design flow starting from an RTL description to an (10)

10 a)

optimized gate level description.

Explain with examples how the logic synthesis tool interpret the following (06)

b)

constructs and translate them into logic gates.i) Assignment statement ii) If-else statement iii) case statementWhat is logic synthesis? Explain the impact of computer aided logic synthesis (10)

c)tools.Which are the typical synthesizable constructs in Verilog? (04)

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