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futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5

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Page 1: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5
Page 2: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5

For details on futexes, avoid the Linux man pages, but look athttp://people.redhat.com/drepper/futex.pdf, from which this material was obtained.Note that there’s actually just one futex system call; whether it’s a wait or a wakeup isspecified by an argument.

Page 3: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5

These functions are available on most architectures, particularly on the x86. Note thattheir effect must be atomic: everything happens at once.

Page 4: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5
Page 5: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5
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Page 7: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5

This slide illustrates a simplistic view of the architecture of a multi-core processor: anumber of processors are all directly connected to the same memory (which they share).If one core (or processor) stores into a storage location and immediately thereafteranother core loads from the same storage location, the second core loads exactly whatthe first core stored.

Page 8: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5

Real multi-core processors employ a hierarchy of caches between the cores andmemory, will the caches sharing the bus with the memory controller. (The Intel I-5architecture, used on SunLab machines, has three levels of caches: two L1 caches (oneeach for data and instructions) per core, one L2 cache per core, and an L3 cache sharedby all four cores. For the purposes of this discussion, it suffices to think of just onecache for each core.) An elaborate cache-coherency protocol is used so that the cachesare consistent: no two caches have different versions of the same data item and if some aparticular cache contains a data item that different (and newer) than what’s in memory,other caches when they attempt to load that item will get the newest version.

Page 9: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5

This slide shows an even more realistic model, pretty much the same as what we sawis actually used in recent Intel processors. Between each core and its caches is a storebuffer. Stores by a core go into the buffer. Sometime later the effect of the store reachesthe cache. In the meantime, the core is issuing further instructions. Loads by the coreare handled from the buffer if the data is still there; otherwise they are taken from thecaches, or perhaps from memory.In all instances of this model the effect of a store, as seen by other cores, is delayed. In

some instances of this model the order of stores made by one core might be perceiveddifferently by other cores. Architectures with the former property are said to havedelayed stores; architectures with the latter are said to have reordered stores (anarchitecture could well have both properties).

Page 10: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5

In this example, one thread running on one processor is loading from an integer instorage; another thread running on another processor is loading from and then storinginto an integer in storage. Can this be done safely without explicit synchronization?On most architectures, the answer is yes. If the integer in question is aligned on a

natural (e.g., eight-byte) boundary, then the hardware (perhaps the cache) insures thatloads and stores of the integer are atomic.However, one cannot assume that this is the case on all architectures. Thus a portable

program must use explicit synchronization (e.g., a mutex) in this situation.

Page 11: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5

Shown on the slide is Peterson’s algorithm for handling mutual exclusion for twothreads without explicit synchronization. (The me argument for one thread is 0 and forthe other is 1.) This program works given the first two shared-memory models. Does itwork with delayed-store architectures?

The algorithm is from “Myths About the Mutual Exclusion Problem,” by G. L. Peterson,Information Processing Letters 12(3) 1981: 115–116.

Page 12: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5

This example is a solution, employing “busy waiting,” to the producer-consumerproblem for one consumer and one producer. It works for the first two shared-memorymodels, and even for delayed-store architectures. But does it work on reordered-storearchitectures?

This solution to the producer-consumer problem is from “Proving the Correctness ofMultiprocess Programs,” by L. Lamport, IEEE Transactions on Software Engineering, SE-3(2) 1977: 125-143.

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The point of the previous several slides is that one cannot rely on expected propertiesof shared memory to eliminate explicit synchronization. Shared memory can behave insome very unexpected ways. However, it is the responsibility of the implementers of thevarious synchronization primitives to make certain not only that they behave correctly,but also that they synchronize memory with respect to other threads.

Page 14: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5

In most systems there are actually two components of the execution context: the usercontext and the kernel context. The former is for use when an activity is executing usercode; the latter is for use when the activity is executing kernel code (on behalf of thechore). How these contexts are manipulated is one of the more crucial aspects of athreads implementation.The conceptually simplest approach is what is known as the one-level model: each

thread consists of both contexts. Thus a thread is scheduled to an activity and theactivity can switch back and forth between the two types of contexts. A single schedulerin the kernel can handle all the multiplexing duties. The threading implementation inWindows is (mostly) done this way.

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Unlike most other Unix systems, which make a distinction between processes andthreads, allowing multithreaded processes, Linux maintains the one-thread-per-processapproach. However, so that we can have multiple threads sharing an address space,Linux supports the clone system call, a variant of fork, via which a new process can becreated that shares resources (in particular, its address space) with the parent. Theresult is a variant of the one-level model.This approach is not unique to Linux. It was used in SGI’s IRIX and was first

discussed in early ’89, when it was known as variable-weight processes. (See “Variable-Weight Processes with Flexible Shared Resources,” by Z. Aral, J. Bloom, T. Doeppner, I.Gertner, A. Langerman, G. Schaffer, Proceedings of Winter 1989 USENIX AssociationMeeting.)

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As implemented in Linux, a process may be created with the clone system call (inaddition to using the fork system call). One can specify, for each of the resources shownin the slide, whether a copy is made for the child or the child shares the resource withthe parent. Only two cases are generally used: everything is copied (equivalent to fork) oreverything is shared (creating what we ordinarily call a thread, though the “thread” has aseparate process ID).

Page 17: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5

Building a POSIX-threads implementation on top of Linux’s variable-weight processesrequires some work. What’s discussed here is the approach used prior to Linux 2.6.Each thread is, of course, a process; all threads of the same computation share the

same address space, open files, and signal handlers. One might expect that theimplementation of pthread_create would be a simple call to clone. This, unfortunately,wouldn’t allow an easy implementation of operations such as pthread_join: a Unixprocess may wait only for its children to terminate; a POSIX thread can join with anyother joinable thread. Furthermore, if a Unix process terminates, its children areinherited by the init process (process number 1). So that pthread_join can beimplemented without undue complexity, a special manager thread (actually a process) isthe parent/creator of all threads other than the initial thread. This manager threadhandles thread (process) termination via the wait4 system call and thus provides ameans for implementing pthread_join. So, when any thread invokes pthread_create orpthread_join, it sends a request to the manager via a pipe and waits for a response. Themanager handles the request and wakes up the caller when appropriate.The state of a mutex is represented by a bit. If there are no competitors for locking a

mutex, a thread simply sets the bit with a compare-and-swap instruction (allowingatomic testing and setting of the mutex’s state bit). If a thread must wait for a mutex tobe unlocked, it blocks using a sigsuspend system call, after queuing itself to a queueheaded by the mutex. A thread unlocking a mutex wakes up the first waiting thread bysending it a Unix signal (via the kill system call). The wait queue for condition variablesis implemented in a similar fashion.On multiprocessors, for mutexes that are neither recursive nor error-checking, waiting

is implemented with an adaptive strategy: under the assumption that mutexes aretypically not held for a long period of time, a thread attempting to lock a locked mutex“spins” on it for up to a short period of time, i.e., it repeatedly tests the state of the

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mutex in hopes that it will be unlocked. If the mutex does not become available afterthe maximum number of tests, then the thread finally blocks by queuing itself andcalling sigsuspend.

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NPTL, the “Native POSIX Threads Library” that comes with most Linux 2.6 systems,provides a big improvement over the previous version of threads on Linux, which isreferred to as “Linux Threads.” There’s no need for a manager thread anymore, signal-handling semantics are now as they should be in POSIX, and synchronization constructsare implemented much more efficiently than on Linux Threads.

Page 20: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5

Another approach, the two-level model, is to represent the two contexts as separatetypes of threads: user threads and kernel threads. Kernel threads become “virtualactivities” upon which user threads are scheduled. Thus two schedulers are used: kernelthreads are multiplexed on activities by a kernel scheduler; user threads are multiplexedon kernel threads by a user-level scheduler. An extreme case of this model is to use onlya single kernel thread per process (perhaps because this is all the operating systemsupports). The Unix implementation of the Netscape web browser was based on thismodel (recent Solaris versions use the native Solaris implementation of threads), as wereearly Unix threads implementations. There are two obvious disadvantages of thisapproach, both resulting from the restriction of a single kernel thread per process: onlyone activity can be used at a time (thus a single process cannot take advantage of amultiprocessor) and if the kernel thread is blocked (e.g., as part of an I/O operation), nouser thread can run.

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A more elaborate use of the two-level model is to allow multiple kernel threads perprocess. This deals with both the disadvantages described above and is the basis of theSolaris implementation of threading. It has some performance issues; in addition thenotion of multiplexing user threads onto kernel threads is very different from the notionof multiplexing threads onto activities—there is no direct control over when a chore isactually run by an activity. From an application’s perspective, it is sometimes desired tohave direct control over which chores are currently being run.

Page 23: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5
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One negative aspect of the two-level model is that its use might induce deadlock. Forexample, suppose we have two user threads and one kernel thread. One thread iswriting into a pipe (using the write system call). However, at the moment the pipe is full.The the call to write blocks. The other user thread is ready to do a read system call onthe pipe, thus making it not full and unblocking the first thread, but since there’s onlyone kernel thread and it’s blocked (since it’s running the first user thread), the seconduser thread can’t read from the pipe and thus we’re stuck: deadlocked.The solution would be to introduce an additional kernel thread if such a situation

happens. This was done in the Solaris implementation of the two-level thread model: ifall kernel threads in a process are blocked, a new one was automatically created.

Page 25: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5
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Thread-local storage (TLS) is implemented as part of POSIX threads. We use it inmthreads for references to the current utthread and the current LWP. Unfortunately,referencing TLS is not async-signal safe. Since you will be using TLS within the signalhandler for SIGVTALRM, make sure that you mask SIGVTALRM when using TLS.

Page 28: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5

Yet another approach, known historically as the scheduler activations model, is thatthreads represent user contexts, with kernel contexts supplied when needed (i.e., not asa kernel thread, as in the two-level model). User threads are multiplexed on activities bya user-level scheduler, which communicates to the kernel the number of activitiesneeded (i.e., the number of ready user threads). The kernel multiplexes entire processeson activities—it determines how many activities to give each process. This model, whichis the basis for the Digital-Unix (now True64 Unix) threading package, certainly givesdirect control to the user application over which chores are being run.To make some sense of this, let’s work through an example. A process starts up,

containing a single user execution context (and user thread) and a kernel executioncontext (and kernel thread). Following the dictates of its scheduling policy, the kernelscheduler assigns a processor to the process. If the kernel thread blocks, the processimplicitly relinquishes the processor to the kernel scheduler, and gets it back once itunblocks.Suppose that the user program creates a new thread (and its associated user execution

context). If actual parallelism is desired, code in the user-level library notifies the kernelthat two processors are desired. When a processor becomes available, the kernel createsa new kernel execution context; using the newly available processor running in the newkernel execution context, it places an upcall (going from system code to user code,unlike a system call, which goes from user code to system code) to the user-level library,effectively giving it the processor. The library code then assigns this processor to the newthread and user execution context.

Page 29: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5
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This slide shows, roughly, the I/O architecture of multicore x86 systems. For detailssee “Intel 64 and IA-32 Architectures Software Developer’s Manual,” Volume 3A, Chapter10, obtainable fromhttp://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html. “APIC” stands for “advanced programmable interruptcontroller.” External devices issue interrupts through an I/O APIC. These, based oncriteria such as the current interrupt-priority level of the various processor cores, directan interrupt to one of them. The local APIC determines when to interrupt the local core.It also contains an interval timer that’s available to software.

Page 32: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5

The choice between the current stack and the separate stack is an architecturaldecision, i.e., made by the designers of the hardware, not by the designers of theoperating system.

Page 33: futex ora is - Brown Universitycs.brown.edu/courses/cs167/lectures/04ThreadsImp3.pdf · Realmulti-coreprocessorsemployahierarchyofcachesbetweenthecoresand memory,willthecachessharingthebuswiththememorycontroller.(TheIntelI-5
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This approach was used both by Unix and VMS on the Digital VAX-11 architecture.

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Interrupt threads are used in the Solaris operating system.

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We assume the threads are running on a single-processor system.

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This code doesn’t work!

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More is needed. (See next slide.)

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