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Hiroshi Iwai
Frontier Research Center
Tokyo Institute of Technology
Future of Nano CMOS Technology
May 26, 2014,
IEEE EDS MQ at KTH, Kista, Stockholm, Sweden
1
Back ground for nano-electronics
2
3
(1970) 10 μm 8 μm 6 μm 4 μm 3 μm 2 μm 1.2 μm
0.8 μm 0.5 μm 0.35 μm 0.25 μm 180 nm 130 nm
90 nm 65 nm 45 nm 32 nm (28 nm ) 22 nm(2012)
Feature Size / Technology Node
From 1970 to 2013 (Last year)
18 generations
Line width: 1/450
Area: 1/200,000
43 years 1 generation
2.5 years
Line width: 1/1.43 = 0.70
Area: 1/2 = 0.5
14 nm (2014)
LDiffusive transport
LBallistic transport
~L
Quasi-Ballistic transport
L :Mean free pathsource drain
Mobility
Theory
Real nanoscale
MOSFETs
Back scattering
from drain
Ballistic transport will never
happen for MOSFET because
of back scattering at drain
With decreasing channel length,
Drain current increase continue.
一次元バリスティック伝導
Also, 1D quantum conduction, or ballistic conduction will not happen.
Ballistic conduction will not happen
even decreasing channel lengh.
(1D quantum conduction: 77.8mS regardless of the length and material).4
5
Then, now!.
Noticed that the technology is difficult.
Development of EUV (Extreme Ultra Violet)
lithography delayed significantly.
https://www.google.co.jp/search?q=euv&tbm=isch&tbo=u&source=univ&sa=X&ei=ikY8U5asC8HXyAGok4DwCA&ved=0CDgQsAQ&biw=1745&bih=828#facrc=_&imgrc=KmzxirNdZ0cBM
%253A%3B6JNTCrv867Tq0M%3Bhttp%253A%252F%252Ftechon.nikkeibp.co.jp%252Farticle%252FNEWS%252F20061017%252F122347%252FEUV.jpg%3Bhttp%253A%252F%252
Ftechon.nikkeibp.co.jp%252Farticle%252FNEWS%252F20061017%252F122347%252F%253FSS%253Dimgview_scr%2526FD%253D-672378983%3B750%3B562
6
Noticed that the technology is difficult.
- Reduction of the thickness of High-k gate oxide
becomes very difficult.
In addition with the significant delay in EUV
(Extreme Ultra Violet) lithography delayed
significantly,
- Decreasing supply voltage becomes difficult
because of subtreshold leakage and
variability of thereshold voltage.
Now
7
Technology development delayed.
Number of the semiconductor companies which can develop
state of the art technology decreasing.
In the past, technologies come with the purchase of
equipment's
But now, every companies are facing threat of dropping off,
unless they concentrated on the development of
technologies.
Shrink rate of gate length will become from 07 to 0.8 or 0.85.
Thus, technology development is becoming much
important.
8
Near future smart-society has to treat huge
data.
Demand to high-performance and low power
CMOS become much more stronger.
9
Semiconductor Device Market will
grow 5 times in 12 years, even
though, it is very matured market!!
Gartner: By K. Kim, CSTIC 2012
300B USD
2011
1,500B USD
2025
What is the problem for downsizing?
Question
10
The problem for downsizing
Ioff increase: Transistor cannot be turned-off.
Ioff (Off-leakage current) between S and D
11
1. Punch-through between S and D
2. Direct-tunneling between S and D
3. Subthreshold current between S and D
S and D distance small
Ion & Ioff increase
12
1. Punch-through between S and D
Gate oxide
Gate metal
Source Drain
1V0V0V
Substrate 0V Depletion
Region (DL)
by Drain Bias
1V
0V 0V
tox and Vdd have to be decreased for better channel
potential control IOFF Suppression
0V < Vdep<1V
0V
0V < Vdep<1V
Channel
0V
0V
0V0V
0.5V
Large IOFF
Region governed
By drain biasRegion governed
by gate bias
DL touch with S
Region (DL)
Large IOFF
No tox. Vdd
thinning
Vdd
Vdd
13
Problem for downsizing
(Electron current)
14
1. Punch-through between S and D
There are 3 solutions to suppress the depletion layer
A. Decrease supply voltage Very difficult
B. Decrease tox to enhance the channel potential controllability by gate bias
as explained later
C. Gate/channel configuration change to enhance the channel potential controllability by gate bias
Fin-FET, ET-SOI, etc.
A. Toriumi (Tokyo Univ), IEDM 2006, Short Course
t ox(
(
15
B.Decrease tox
16
C. Configuration change for channel and gate structures for better control of channel potential.
Fin-FET, ET-SOI, etc.
1V0V
0V
S
0V
0V <V<1V
1V0V
0V
0V
0VS D
G
G
G
Extremely Thin (or Fully-Depleted) SOI
Planar ET (or FD) SOI17
Si
SiO2
Extremely
thin Si
Drain bias
induced
depletion
- Make Si layer thin
- Control channel potential also from the bottom
1V0V
0V
S
0V
0V <V<1V
1V0V
0V
0V
0VS D
G
G
G
Surrounding gate structure (Multiple gates)
PlanarMulti gate
18
Si fin or
nanowire
Drain bias
induced
depletion
- Make Si layer thin
- Control channel potential also by multiple gates
not only from top & bottom but maybe also
from side
Fin Tri-gate
(Variation)
W-gate All-around
G G G
G
G
Multi-gate structures
19
G
Tri-gate
New structures!
Our work at TIT: W-gate Si NanowireS. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)
19 nm
12 nm
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.5 -1.0 -0.5 0.0 0.5 1.0
10-12
Gate Voltage (V)
pFET nFET
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
Dra
in C
urr
en
t (A
)
Vd=-50mV
Vd=-1V
Vd=50mV
Vd=1V
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.5 -1.0 -0.5 0.0 0.5 1.0
10-12
Gate Voltage (V)
pFET nFET
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
Dra
in C
urr
en
t (A
)
Vd=-50mV
Vd=-1V
Vd=50mV
Vd=1V
0 0.5 1 1.5 2ION (mA/mm)
Lg=65nm
0 0.5 1 1.5 2ION (mA/mm)
Lg=65nm
Lg=65nm
Poly-Si
SiO2
SiNSiN
SiO2
NW
・Conventional CMOS process
・High drive current
(1.32 mA/mm @ IOFF=117 nA/mm)
・DIBL of 62mV/V and SS of 70mV/dec
for nFET20
21
2. Direct-tunneling between S and D
Wave function of electron penetrates the channel potential barriers by quantum mechanical physics, when the channel length is around 3 nm.
Tunnelingdistance
3 nm
Source DrainChannel
22
Ene
rgy o
r P
ote
ntia
l
for
Ele
ctr
on
Direct-tunnelcurrent
There is no solutions!
Downsizing limit is @ Lg = 3 nm.
Built-in potential
between Source
and Channel pn
junction < 0.7 V
When transistor is at off state
23
3. Subthreshold current between S and D
24
Vg
Id
Vth
(Threshold Voltage)
Vg=0V
Subthreshould
Leakage Current
Subtheshold leakage current of MOSFET
ONOFF
Ion
Subthreshold
region
25
Vg (V)1
0.3 V
0.5 V 1.0 V
Ion
Ioff
Id (A/mm)
10-7
10-5
10-11
10-9
Vd
Vth
0.15 V
0 0.5
Subthreshold leakage current
Electron Energy
Boltzmann statics
Exp (qV/kT)
Lg 1/2
Vd, Vg 1/2
Vth 1/2
Ioff 103 in this example
However
Because of
log-linear dependence
26
Vg
Id
Vth
(Threshold Voltage)
Vg=0V
Subthreshould
Leakage Current
Subtheshold leakage current of MOSFET
Subthreshold Current
Is OK at Single Tr. level
But not OK
For Billions of Trs.
ONOFF
Ion
Subthreshold
region
27
3. Subthreshold current between S and D
Solution: however very difficult
Keep Vth as high as possible
- Do not decrease supply voltage, Vd
- Suppress variability in Vth
However, punchthough enhanced
Thus, subthreshold current will limit the downsizing, especially for mobile devices
28Subthreshold Leakage (A/mm)
Op
era
tio
n F
req
ue
nc
y (
a.u
.)
e)
100
10
1
Source: 2007 ITRS Winter Public Conf.
The limit is deferent depending on application
How far can we go for production?
10mm 8mm 6mm 4mm 3mm 2mm 1.2mm 0.8mm 0.5mm
0.35mm 0.25mm 180nm 130nm 90nm 65nm 45nm 32nm
(28nm) 22nm 14nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm?
Past 0.7 times per 2.5 years
Now Future
・At least 4,5 generations to 8 ~ 5 nm
29
Intermediate
node
Direct-tunnelSubthreshold
punchthrough
Limit depending
on applications
Fundamental
limit
However, careful about the name of technology!
22 nm Technology by Intel
Lg (Gate length) = 30 nm (HP), 34 nm (MP), 34 nm or larger (SP)
IEDM 2012, VLSI 2013
10 nm Technology by Leti (FD-SOI)
Lg (Gate length) = 25 nm Euro SOI 2014
Recently,
Gate length (Lg) is much larger than the Technology name
14 nm Technology by Global
Lg (Gate length) = 15 nm
2015 2017 2019 20252021 2023 20272013
10 7 5 1.83.5 2.5 1.314
32 25.3 20 1015.9 12.6 840
19 16 13.3 7.711.1 9.3 6.423
16.8 14.0 11.7 6.79.7 8.1 5.620.2(10) (8) (6) (5)(13)
0.73 0.67 0.61 0.470.56 0.51 0.430.80(0.60) (0.55) (0.50) (0.50)(0.60)
0.83 0.80 0.77 0.680.74 0.71 0.650.86(0.80) (0.70) (0.70) (0.65)(0.90)
6.1 5.1 4.3 2.53.6 3.0 2.07.4(6.0) (4.5) (3.8) (3.2)(6.0)
Year
Lg (nm)
Metal half pitch (nm)
(Lg for ITRS 2007)
Commercial name (nm)
Lg for low stand by power (nm)
Vdd (V) (Vdd (V) for ITRS 2007)
EOT (nm) (EOT (nm) for ITRS 2007)
TSi (nm) (TSi (nm) for ITRS 2007)
(4.5 in 2022)
(3.0 in 2022)
(0.50 in 2022)
(0.65 in 2022)
ITRS 2013 (Just published in April 2014)
The rate for the shrinkage for the gate length and
line pitch will be larger than 0.7 in near future,
because of the subthreshold leakage, and also
because of the delay in EUV lithography.
As a result, we will have more technology
generations until reaching the downsizing limit,
and the time to reach the limit will be delayed.
How far can we go for production?
33
Thus, we may go down to “1.5 nm”
technology node by choosing
whatever gate length we want for the
application.
More Moore to More More Moore
65nm 45nm 32nm
Technology node
M. Bohr, pp.1, IEDM2011 (Intel)
P. Packan, pp.659, IEDM2009 (Intel)
C. Auth et al., pp.131, VLSI2012 (Intel)
T. B. Hook, pp.115, IEDM2011 (IBM)
S. Bangsaruntip et al., pp.297, IEDM2009 (IBM)
Lg 35nm Lg 30nm
(Fin,Tri, Nanowire)
22nm15nm, 11nm, 8nm, 5nm, 3nm
Alternative (III-V/Ge)
Channel FinFET
Emerging
Devices
Tri-Gate
Now Future
Si channel
Si
Others
(ETSOI)Planar
Si is still main stream for future !! ET: Extremely Thin28nm
High-k gate dielectrics
Continued research
and development
SiO2 IL (Interfacial Layer)
is used at Si interface to
realize good mobility
Technology for direct contact of
high-k and Si is necessary
Remote SiO2-IL
scavenging
HfO2 (IBM)
EOT=0.52 nm
Si
La-silicate
MG
Direct contact with La-silicate (Tokyo.Tech)
T. Ando, et al., p.423, IEDM2009, (IBM)
T. Kawanago, et al., T-ED, vol. 59, no.
2, p. 269, 2012 (Tokyo Tech.)
K. Mistry, et al., p.247, IEDM 2007, (Intel)
TiN
HfO2
Si
SiO2
EOT=0.9nm
HfO2/SiO2
(IBM)
T.C. Chen, et al., p.8, VLSI 2009, (IBM)
Hf-based oxides
45nm
EOT:1nm
32nm
EOT:0.95nm
22nm
EOT:0.9nm15nm, 11nm, 8nm, 5nm, 3nm,
K. Kakushima, et al., p.8, IWDTF 2008,
(Tokyo Tech.)
EOT=0.37nm EOT=0.40nm EOT=0.48nm
0.48 → 0.37nm Increase of Id at 30%
35
High-k is very important, however
very difficult.
36
Thickness (EOT) decreased only
0.05 nm (or 0.5 Å, or 1 atom
layer) for every generation.
How far can we go for production?
37
Now, Ion/Ioff ratio is typically 106.
However, it degrades significantly
with decrease in Vsupply.
Rather than Ioff value, Ion/Ioff ratio
is important.
[a] C. Auth et al., pp.131, VLSI2012 (Intel).[b] K. Mistry et al., pp.247, IEDM2007 (Intel).[c] H.-J. Cho et al., pp.350, IEDM2011 (Samsung).[d] S. Saitoh et al., pp.11, VLSI2012 (Toshiba).[e] S. Bangsaruntip et al., pp.297, IEDM2009 (IBM).
[f] T. Yamashita et al., pp.14, VLSI2011 (IBM).[g] A. Khakifirooz et al., pp.117, VLSI2012 (IBM).
ION and IOFF benchmark
[h] G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics).[i] S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)[j] K. Cheng et al., pp.419, IEDM2012 (IBM)
1
10
100
1000
10000
0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2
ION [mA/mm]
I OF
F[n
A/m
m]
NMOS
Intel [a]
Bulk 32nm
VDD=0.8V
Intel [a]
Tri-Gate 22nm
VDD=0.8V
Intel [b]
Bulk 45nm
VDD=1V
Toshiba [d]
Tri-Gate NW
VDD=1V
Samsung [c]
Bulk 20nm
VDD=0.9V
IBM [5]
GAA NW
VDD=1V
IBM [g]
FinFET 25nm
VDD=1V
IBM [g]
ETSOI
VDD=0.9V
IBM [g]
ETSOI
VDD=1V
STMicro. [h]
GAA NW
VDD=0.9V
STMicro. [h]
GAA NW
VDD=1.1V
Tokyo Tech. [i]
W-gate NW
VDD=1VIBM [j]
ETSOI
VDD=0.9V
Ieff
1
10
100
1000
10000
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
ION [mA/mm]
I OF
F[n
A/m
m]
PMOS
Intel [a]
Bulk 32nm
VDD=0.8V
Intel [a]
Tri-Gate 22nm
VDD=0.8V
Intel [b]
Bulk 45nm
VDD=1V
IBM [g]
ETSOI
VDD=1VSamsung [c]
Bulk 20nm
VDD=0.9V
IBM [e]
GAA NW
VDD=1V
IBM [f]
FinFET 25nm
VDD=1V
IBM [g]
ETSOI
VDD=0.9V
STMicro. [h]
GAA NW
VDD=1.1V
IBM [j]
ETSOI
VDD=0.9V
Ieff
Nanowire/Tri gate MOSFETs have
advantage not only suppressing Ioff,
but also for increasing Ion over planer
MOSFETs
39
1. Because of higher mobility due to
lower vertical electric field
2. Because of higher carrier density at
the round corner
40
0.E+00
1.E+19
2.E+19
3.E+19
4.E+19
5.E+19
6.E+19
0 2 4 6 8Distance from SiNW Surface (nm)
6
5
4
3
2
1
0
角の部分
平らな部分
電子濃度(x1019cm-3)Electron Density
Edge portion
Flat portion
41
3. Now Problems for downsizing!
42
We have to decrease Si layer
thickness to better control of
channel potential by gate bias
when we decrease the gate length.
Significant decrease in conduction
or Ion.
2015 2017 2019 20252021 2023 20272013
10 7 5 1.83.5 2.5 1.314
Year
Commercial name (nm)
6.1 5.1 4.3 2.53.6 3.0 2.07.4(6.0) (4.5) (3.8) (3.2)(6.0)
TSi (nm) (TSi (nm) for ITRS 2007) (3.0 in 2022)
0.73 0.67 0.61 0.470.56 0.51 0.430.80(0.60) (0.55) (0.50) (0.50)(0.60)
EOT (nm) (EOT (nm) for ITRS 2007) (0.50 in 2022)
ITRS 2013
Short-channel effectT. Skotnicki, IEDM 2009 Short Course (STMicroelectronics)
44
45
Mobility degradation for small
diameter nanowire FETs, because
channel carriers become too
close to all surrounding nanowire
surface, and scattered strongly.
S. Bangsaruntip et al., pp.297, IEDM2009 (IBM),
K. Tachi et al., pp.313, IEDM2009 (CEA-LETI)
Decreasing the diameter of NW
Problems in Multi-gate
Improved
short-channel control
Severe mobility
degradation
Significant m degradation
at diameter < 10 nm Need to decrease
diameter for SCH
46
K. Uchida et al., pp.47, IEDM2002 (Toshiba)
Problems in SOI
Mobility is also decreased with
decreasing the Si thickness of SOI
transistor similar to the NW transistor.47
When wire diameter becomes less than 10 nm, sudden drop of Id
Problem for nanowire
Id
Diameter
10 nm
2. Electron density decrease
If diameter cannot be scaled, SCE cannot be suppressed.
Then, again aggressive EOT scaling of high-k is necessary. 48
< 10 nm
1. Mobility degradation
Extremely small distance between the
electron and all around Si surface.
Strong scattering of electrons by interaction
with all around Si surface.
Decrease of DOS in extremely narrow wire.
49
Carrier density degradation for
small diameter nanowire FET,
because of the decrease in
density of states.
Number of quantum channels
Energy band of Bulk Si
Eg
By Prof. Shiraishi of Tsukuba univ.
Energy band of 3 x 3 Si wire
4 channels can be used
Eg
50
51By Profs. Oshiyama and Iwata, U. of Tokyo
Diameter dependence1 nm 2 nm 3 nm 4 nm 6 nm
K. Kim, pp.1, IEDM2010 (Samsung)
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
EO
T [
nm
]
202020152010
Year
12
10
8
6
4
2
0
Bo
dy T
hic
kn
ess [n
m]
Multi-
GatePlanar
ITRS2011
Fin width
EOT Scaling Trends
Smaller wire/fin width is necessary for SCE suppression
But mobility and ION severely degrade with wire/fin width reduction
Therefore even in multi-gate structures, EOT scaling should be
accelerated to provide SCE immunity 52
High-k
beyond 0.5 nm
53
New Materials!
To use high-k dielectrics
Thin SiO2
Thick high-k
dielectrics
Almost the same
electric characteristics
However, very difficult and big challenge!
K: Dielectric Constant
5 times thicker
Small
leakage
Current
K=4K=20
Solution
SiO2 High-k
54
R. Hauser, IEDM Short Course, 1999Hubbard and Schlom, J Mater Res 11 2757 (1996)
●
● Gas or liquid
at 1000 K
●H
○Radio activeHe
● ● ● ● ● ●Li BeB C N O F Ne
① ● ● ● ●Na
Mg Al Si P S Cl Ar
② ① ① ① ① ① ① ① ① ① ① ● ● ● ●K Ca Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr
● ① ① ① ① ① ● ① ① ① ① ① ● ●Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe● ③ ① ① ① ① ① ● ● ● ● ① ① ○ ○ ○Cs Ba
★ HfTa W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn
○ ○ ○ ○ ○ ○ ○ ○Fr Ra ☆ Rf Ha Sg Ns Hs Mt
○La Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb Lu○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
★
☆
Candidates
● ●Na Al Si P S Cl Ar
② ① ① ① ① ① ① ① ① ① ● ● ● ●K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr
● ① ① ① ① ① ● ① ①
○ ○ ○ ○ ○ ○Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
★
☆
②
③
Unstable at Si interfaceSi + MOX M + SiO2①
Si + MOX MSiX + SiO2
Si + MOX M + MSiXOY
Choice of High-k elements for oxide
HfO2 based dielectrics
are selected as the
first generation
materials, because of
their merit in
1) band-offset,
2) dielectric constant
3) thermal stability
La2O3 based
dielectrics are
thought to be the next
generation materials,
which may not need a
thicker interfacial
layer
55
0 10 20 30 40 50
Dielectric Constant
4
2
0
-2
-4
-6
SiO2
Ba
nd
Dis
co
nti
nu
ity [
eV
]Si
XPS measurement by Prof. T. Hattori, INFOS 2003
Conduction band offset vs. Dielectric Constant
Band offset
Oxide
Leakage Current by Tunneling
56
SiO2-ILHfSix (k~4)
VO
IO
IO
VO
VO
IO
IOVO
HfO2
Si substrateSiO2-IL
(k~4)
LaSix
VO
IOVO
IO
VO
IOLa2O3
silicateLa-rich Si-rich
Si substrate
High PO2Low PO2 High PO2Low PO2
HfO2 case La2O3 case
Direct contact can be achieved with La2O3 by forming silicate at interface
Control of oxygen partial pressure is the key for processing.
Our approach
K. Kakushima, et al., VLSI2010, p.69
Direct high-k/Si by silicate reaction
PO2: Partial pressure of O2 during
high temperature annealing
1837184018431846
Binding energy (eV)
Inte
ns
ity
(a
.u)
Si sub.
Hf SilicateSiO2
500 oC
1837184018431846
Binding energy (eV)
Inte
ns
ity
(a
.u)
Si sub.
Hf SilicateSiO2
500 oC
SiOx-IL
HfO2
W
1 nm
k=4
k=16
SiOx-IL growth at HfO2/Si Interface
HfO2 + Si + O2 → HfO2 + Si + 2O*→HfO2+SiO2
Phase separator
SiOx-IL is formed after annealing
Oxygen control is required for optimizing the reaction
Oxygen supplied from W gate electrode
XPS Si1s spectrum
D.J.Lichtenwalner, Tans. ECS 11, 319
TEM image500 oC 30min
H. Shimizu, JJAP, 44, pp. 6131
La-Silicate Reaction at La2O3/Si
La2O3
La-silicate
W
500 oC, 30 min
1 nm
k=8~14
k=23
1837184018431846
Binding energy (eV)
Inte
nsit
y (
a.u
)
as depo.
300 oC
La-silicate
Si sub.
500 oC
1837184018431846
Binding energy (eV)
Inte
nsit
y (
a.u
)
as depo.
300 oC
La-silicate
Si sub.
500 oC
La2O3 + Si + nO2
→ La2SiO5, La2Si2O7,
La9.33Si6O26, La10(SiO4)6O3, etc.
La2O3 can achieve direct contact of high-k/Si
XPS Si1s spectraTEM image
Direct contact high-k/Si is possible
60
① silicate-reaction-formed
fresh interface
metal
Si sub.
metal
Si sub.
La2O3 La-silicateSi Si
Fresh interface with
silicate reaction
J. S. Jur, et al., Appl. Phys. Lett.,
Vol. 87, No. 10, (2007) p. 102908
② stress relaxation at interface
by glass type structure of La
silicate.
La atom
La-O-Si bonding
Si sub.
SiO4tetrahedron network
FGA800oC is necessary to
reduce the interfacial stress
S. D. Kosowsky, et al., Appl. Phys. Lett.,
Vol. 70, No. 23, (1997) pp. 3119
Physical mechanisms for small Dit
61
2
1.5
1
0.5
0
Capacitance [m
F/c
m2]
-1 -0.5 0 0.5 1
Gate Voltage [V]
10kHz 100kHz 1MHz
20 x 20mm2
1.5
1
0.5
0
Ca
pa
cita
nce
[m
F/c
m2]
-1.5 -1 -0.5 0 0.5
Gate Voltage [V]
20 x 20mm2
10kHz 100kHz 1MHz
2
1.5
1
0.5
0
Ca
pa
cita
nce
[m
F/c
m2]
-1.5 -1 -0.5 0 0.5
Gate Voltage [V]
20 x 20mm2
10kHz 100kHz 1MHz
FGA500oC 30min FGA700oC 30min FGA800oC 30min
A fairly nice La-silicate/Si interface can be obtained
with high temperature annealing. (800oC)
However, high-temperature anneal is necessary
for the good interfacial property
5m
Robot
Flash Lamp
ALD
RTAEntrance
Sputter
for MG
EB Deposition for HK5m
Cluster tool for HKMG Stack
62
Cluster Chambers for HKMG Gate Stack
Flash Lamp
Anneal
EB Deposition: HK
Sputter: MG
ALD: HK
Robot
RTA
Entrance
63
substrate
①La gas
feed
②Ar purge ③H2O
feed④Ar purge
La
ligand HO
substrate substrate substrate
1 cycle
L a
C 3H 7
3
L a
C 3H 7
3
L a
C 3H 7
3
CLaN
NH
C3H7
C3H7
La(iPrCp)3 La(FAMD)3
Precursor
(ligand)
ALD is indispensable from the manufacturing viewpoint
- precise control of film thickness and good uniformity
K. Ozawa, et al., (Tokyo Tech. and AIST) Ext. Abstr.
the 16th Workshop on Gate Stack Technology and Physics., 2011, p.107.
64
ALD of La2O3
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
600 700 800 900 1000As depo
~ ~
Annealing temperature (oC)
EO
T (
nm
)
Annealed for 2 s
La2O3(3.5 nm)
W(60 nm)
TiN/W(12 nm)
TiN/W(6 nm)
TiN(45nm)/W(6nm)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
-1 -0.5 0 0.5
Vg (V)
Cg
(u
F/c
m2)
Experiment
Cvc fittingTheory
EOT=0.55nm
TaN/(45nm)/W(3nm)
900oC, 30min
EOT=0.55nm
65
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.5 0.55 0.6 0.65 0.7
Fla
t-ba
nd
vo
lta
ge
(V)
EOT(nm)
TaN(45nm)/W(3nm)
900oC, 30min
Qfix=1×1011 cm-2
Fixed Charge density: 1×1011 cm-2
66
0 0.2 0.4 0.6 0.8 1.0
Drain Voltage (V)
0.2
0.4
0.6
0.8
1.0
Dra
in C
urr
en
t (m
A)
Vg= 0.4V
Vg= 0.6V
Vg= 0.8V
Vg= 1.0V
Vg= 0.2V
Vg= 0 V
L/W = 5/20mm
T = 300K
Nsub = 3×1016cm-3
0
20
40
60
80
100
120
140
0 0.5 1 1.5 2 2.5
EOT = 0.40nm
L/W = 5/20mm
T = 300K
Nsub = 3×1016cm-3
Eeff [MV/cm]
Ele
ctr
on
Mo
bilit
y [
cm
2/V
sec]
EOT=0.40nm
Our Work at TIT: High-k
67
Our result at TIT
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
0.3 0.4 0.5 0.6 0.7 0.8
ITRS requirement
Jg
at 1
V (
A/c
m2)
EOT (nm)
Benchmark of La-silicate dielectrics
T. Ando, et al., (IBM) IEDM 2009, p.423
0
50
100
150
200
250
300
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
EOT (nm)M
ob
ility
(cm
2/V
se
c)
at 1 MV/cm
Open square : Hf-based oxides
Solid circle: Our data
Our data: La-silicate gate oxide
La-silicate gate oxide
L.-Å. Ragnarsson, et al., (IMEC) Microelectron. Eng, vol. 88, no. 7, pp. 1317–1322, 2011.
68
Gate Leakage current Effective Mobility
Si-sub.
Metal
SiO2-IL
High-k
Small interfacial state
density at high-k/Si
Oxygen diffusion control for
prevention of EOT increase
and oxygen vacancy
formation in high-k
Thinning or removal of
SiO2-IL for small EOT
Flat metal/high-k
interface for better
mobility
O
Workfunction engineering for
Vth control
Interface dipole control
for Vth tuning
Suppression of
oxygen vacancy
formation
Control of interface reaction
and Si diffusion to high-k
Oxygen concentration control
for prevention of EOT increase
and oxygen vacancy
formation in high-k
Suppression of
metal diffusion
Endurance for high
temperature process
Remove contamination
introduced by CVD
Reliability: PBTI,
NBTI, TDDB
Suppression of gate
leakage current
Suppression of FLP
69
Issues in high-k/metal gate stack
70
Thank you very much
for your attention.
71
Appendix
72
What is Next Revolution for Device Technology?
1900: Electronics
73
What is Next Revolution for Device Technology?
1900: Electronics
1970: Micro Electronics
74
What is Next Revolution for Device Technology?
1900: Electronics
1970: Micro Electronics
When?: What?
75
What is Next Revolution for Device Technology?
1900: Electronics
1970: Micro Electronics
?: Nano Electronics
76
What is Next Revolution for Device Technology?
1900: Electronics
1970: Micro Electronics
?: Nano Electronics
Maybe Not a Revolution
But Great Innovention
77
What is Next Revolution for Device Technology?
1900: Electronics
1970: Micro Electronics
When?: What?
78
What is Next Revolution for Device Technology?
1900: Electronics
1970: Micro Electronics
When?: What?
? years
79
What is Next Revolution for Device Technology?
1900: Electronics
1970: Micro Electronics
When?: What?
70 years
? years
80
What is Next Revolution for Device Technology?
1900: Electronics
1970: Micro Electronics
When?: What?
70 years
70 years
81
What is Next Revolution for Device Technology?
1900: Electronics
1970: Micro Electronics
2040: Braintronics
70 years
70 years
82We do know system and algorithms are important!But do not know how it can be by us for use of bio?
Braintronics
83
Source: H. Iwai, IPFA 2006
Size
Saturation of Downsizing
Some time in 2020 -2030
New Materials, New Process, New Structure
Hybrid integration of different functional Chip Increase of SOC functionality
3D integration of memory cell3D integration of logic devices
Low cost for LSI processRevolution for CR, Equipment
Miniaturization of Interconnects on PCB(Printed Circuit Board)
Introduction of algorithmof biosystemBrain of insects, human
After 2040?
We do not know how?
Long term roadmap for development
Braintronics
84
Braintronics for 2040’s
It’s a task for you,
For young generations!