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1
1
10 11
20I/CLK
I
I
I
I
I
I
I
I
GND
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
5
15
FUNCTIONAL BLOCK DIAGRAMFEATURES
PIN CONFIGURATION
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY— 3.5 ns Maximum Propagation Delay— Fmax = 250 MHz— 3.0 ns Maximum from Clock Input to Data Output— UltraMOS ® Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR— 75mA Typ Icc on Low Power Device— 45mA Typ Icc on Quarter Power Device
• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY— Reconfigurable Logic— Reprogrammable Cells— 100% Tested/Guaranteed 100% Yields— High Speed Electrical Erasure (
Specifications GAL16V8
1996 Data Book2
GAL16V8 ORDERING INFORMATION
Commercial Grade Specifications
PART NUMBER DESCRIPTION
Blank = CommercialI = Industrial
Grade
PackagePowerL = Low PowerQ = Quarter Power
Speed (ns)
XXXXXXXX XX X X X
Device Name
_
P = Plastic DIPJ = PLCC
GAL16V8DGAL16V8CGAL16V8B
)sn(dpT )sn(usT )sn(ocT )Am(ccI #gniredrO egakcaP
5.3 5.2 0.3 511 JL3-D8V61LAG CCLPdaeL-02
5 3 4 511 PL5-C8V61LAG PIDcitsalPniP-02
511 8V61LAG 5-C JL CCLPdaeL-02
5.7 7 5 1 51 8V61LAG C PL7- PIDcitsalPniP-02
1 51 8V61LAG C JL7- CCLPdaeL-02
511 PL7-B8V61LAG PIDcitsalPniP-02
511 JL7-B8V61LAG CCLPdaeL-02
01 01 7 511 PL01-B8V61LAG PIDcitsalPniP-02
511 JL01-B8V61LAG CCLPdaeL-02
01 01 5.7 55 PQ01-D8V61LAG PIDcitsalPniP-02
55 JQ01-D8V61LAG CCLPdaeL-02
51 21 01 55 PQ51-D8V61LAG PQ51-B8V61LAGro PIDcitsalPniP-02
55 JQ51-D8V61LAG ro JQ51-B8V61LAG CCLPdaeL-02
09 PL51-D8V61LAG ro PL51-B8V61LAG PIDcitsalPniP-02
09 JL51-D8V61LAG ro JL51-B8V61LAG CCLPdaeL-02
52 51 21 55 PQ52-D8V61LAG ro PQ52-B8V61LAG PIDcitsalPniP-02
55 JQ52-D8V61LAG ro JQ52-B8V61LAG CCLPdaeL-02
09 PL52-D8V61LAG ro PL52-B8V61LAG PIDcitsalPniP-02
09 JL52-D8V61LAG ro JL52-B8V61LAG CCLPdaeL-02
)sn(dpT )sn(usT )sn(ocT )Am(ccI #gniredrO egakcaP
5.7 7 5 031 IPL7-C8V61LAG PIDcitsalPniP-02
031 IJL7-C8V61LAG CCLPdaeL-02
01 01 7 031 IPL01-B8V61LAG PIDcitsalPniP-02
031 IJL01-B8V61LAG CCLPdaeL-02
51 21 01 031 IPL51-D8V61LAG ro IPL51-B8V61LAG PIDcitsalPniP-02
031 IJL51-D8V61LAG ro IJL51-B8V61LAG CCLPdaeL-02
02 31 11 56 IPQ02-D8V61LAG ro IPQ02-B8V61LAG PIDcitsalPniP-02
56 IJQ02-D8V61LAG ro IJQ02-B8V61LAG CCLPdaeL-02
52 51 21 56 IPQ52-D8V61LAG ro IPQ52-B8V61LAG PIDcitsalPniP-02
56 IJQ52-D8V61LAG ro IJQ52-B8V61LAG CCLPdaeL-02
031 IPL52-D8V61LAG ro IPL52-B8V61LAG PIDcitsalPniP-02
031 IJL52-D8V61LAG ro IJL52-B8V61LAG CCLPdaeL-02
Industrial Grade Specifications
Specifications GAL16V8
1996 Data Book3
OUTPUT LOGIC MACROCELL (OLMC)
The following discussion pertains to configuring the output logicmacrocell. It should be noted that actual implementation is ac-complished by development software/hardware and is completelytransparent to the user.
There are three global OLMC configuration modes possible:simple , complex , and registered . Details of each of thesemodes are illustrated in the following pages. Two global bits, SYNand AC0, control the mode configuration for all macrocells. TheXOR bit of each macrocell controls the polarity of the output in anyof the three modes, while the AC1 bit of each of the macrocellscontrols the input/output configuration. These two global and 16individual architecture bits define all possible configurations in aGAL16V8 . The information given on these architecture bits isonly to give a better understanding of the device. Compiler soft-ware will transparently set these architecture bits from the pindefinitions, so the user should not need to directly manipulatethese architecture bits.
The following is a list of the PAL architectures that the GAL16V8can emulate. It also shows the OLMC mode under which theGAL16V8 emulates the PAL architecture.
PAL Architectures GAL16V8Emulated by GAL16V8 Global OLMC Mode
16R8 Registered16R6 Registered16R4 Registered
16RP8 Registered16RP6 Registered16RP4 Registered
16L8 Complex16H8 Complex16P8 Complex
10L8 Simple12L6 Simple14L4 Simple16L2 Simple10H8 Simple12H6 Simple14H4 Simple16H2 Simple10P8 Simple12P6 Simple14P4 Simple16P2 Simple
COMPILER SUPPORT FOR OLMC
Software compilers support the three different global OLMCmodes as different device types. These device types are listedin the table below. Most compilers have the ability to automati-cally select the device type, generally based on the register usageand output enable (OE) usage. Register usage on the deviceforces the software to choose the registered mode. All combina-torial outputs with OE controlled by the product term will force thesoftware to choose the complex mode. The software will choosethe simple mode only when all outputs are dedicated combinatorialwithout OE control. The different device types listed in the tablecan be used to override the automatic device selection by thesoftware. For further details, refer to the compiler softwaremanuals.
When using compiler software to configure the device, the usermust pay special attention to the following restrictions in eachmode.
In registered mode pin 1 and pin 11 are permanently configuredas clock and output enable, respectively. These pins cannot beconfigured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 11 become dedicated inputs anduse the feedback paths of pin 19 and pin 12 respectively. Becauseof this feedback path usage, pin 19 and pin 12 do not have thefeedback option in this mode.
In simple mode all feedback paths of the output pins are routedvia the adjacent pins. In doing so, the two inner most pins ( pins15 and 16) will not have the feedback option as these pins arealways configured as dedicated combinatorial output.
Registered Complex Simple Auto Mode Select
ABEL P16V8R P16V8C P16V8AS P16V8CUPL G16V8MS G16V8MA G16V8AS G16V8LOG/iC GAL16V8_R GAL16V8_C7 GAL16V8_C8 GAL16V8OrCAD-PLD "Registered"1 "Complex"1 "Simple"1 GAL16V8APLDesigner P16V8R2 P16V8C2 P16V8C2 P16V8ATANGO-PLD G16V8R G16V8C G16V8AS3 G16V8
1) Used with Configuration keyword.2) Prior to Version 2.0 support.3) Supported on Version 1.20 or later.
Specifications GAL16V8
1996 Data Book4
REGISTERED MODE
In the Registered mode, macrocells are configured as dedicatedregistered outputs or as I/O functions.
Architecture configurations available in this mode are similar tothe common 16R8 and 16RP4 devices with various permutationsof polarity, I/O and register placement.
All registered macrocells share common clock and output enablecontrol pins. Any macrocell can be configured as registered orI/O. Up to eight registers or up to eight I/O's are possible in this
mode. Dedicated input or output functions can be implementedas subsets of the I/O function.
Registered outputs have eight product terms per output. I/O'shave seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature(UES) fuses and the Product Term Disable (PTD) fuses, areshown on the logic diagram on the following page.
Registered Configuration for Registered Mode
- SYN=0.- AC0=1.- XOR=0 defines Active Low Output.- XOR=1 defines Active High Output.- AC1=0 defines this output configuration.- Pin 1 controls common CLK for the registered outputs.- Pin 11 controls common OE for the registered outputs.- Pin 1 & Pin 11 are permanently configured as CLK & OE.
Combinatorial Configuration for Registered Mode
- SYN=0.- AC0=1.- XOR=0 defines Active Low Output.- XOR=1 defines Active High Output.- AC1=1 defines this output configuration.- Pin 1 & Pin 11 are permanently configured as CLK & OE.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
D Q
Q
CLK
OE
XOR
XOR
Specifications GAL16V8
1996 Data Book5
REGISTERED MODE LOGIC DIAGRAM
DIP & PLCC Package Pinouts
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
0000
0224
0256
0480
0512
0736
0768
0992
1024
1248
1280
1504
1536
1760
1792
2016
19
XOR-2048AC1-2120
XOR-2049AC1-2121
XOR-2050AC1-2122
XOR-2051AC1-2123
XOR-2052AC1-2124
XOR-2053AC1-2125
XOR-2054AC1-2126
XOR-2055AC1-2127
2824201612840 PTD2128
2191OE
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
SYN-2192AC0-2193
Specifications GAL16V8
1996 Data Book6
COMPLEX MODEIn the Complex mode, macrocells are configured as output onlyor I/O functions.
Architecture configurations available in this mode are similar tothe common 16L8 and 16P8 devices with programmable polarityin each macrocell.
Up to six I/O's are possible in this mode. Dedicated inputs oroutputs can be implemented as subsets of the I/O function. Thetwo outer most macrocells (pins 12 & 19) do not have input ca-
pability. Designs requiring eight I/O's can be implemented in theRegistered mode.
All macrocells have seven product terms per output. One productterm is used for programmable output enable control. Pins 1 and11 are always available as data inputs into the AND array.
The JEDEC fuse numbers including the UES fuses and PTD fusesare shown on the logic diagram on the following page.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Combinatorial I/O Configuration for Complex Mode
- SYN=1.- AC0=1.- XOR=0 defines Active Low Output.- XOR=1 defines Active High Output.- AC1=1.- Pin 13 through Pin 18 are configured to this function.
Combinatorial Output Configuration for Complex Mode
- SYN=1.- AC0=1.- XOR=0 defines Active Low Output.- XOR=1 defines Active High Output.- AC1=1.- Pin 12 and Pin 19 are configured to this function.
XOR
XOR
Specifications GAL16V8
1996 Data Book7
COMPLEX MODE LOGIC DIAGRAM
DIP & PLCC Package Pinouts
0000
0224
0256
0480
0512
0736
0768
0992
1024
1248
1280
1504
1536
1760
1792
2016
PTD
2128
2191
11
12
13
14
15
16
17
18
19
1
2
3
4
5
6
7
8
9
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
SYN-2192AC0-2193
XOR-2055AC1-2127
XOR-2054AC1-2126
XOR-2053AC1-2125
XOR-2052AC1-2124
XOR-2051AC1-2123
XOR-2050AC1-2122
XOR-2049AC1-2121
XOR-2048AC1-2120
OLMC
OLMC
2824201612840
Specifications GAL16V8
1996 Data Book8
SIMPLE MODEIn the Simple mode, macrocells are configured as dedicated inputsor as dedicated, always active, combinatorial outputs.
Architecture configurations available in this mode are similar tothe common 10L8 and 12P6 devices with many permutations ofgeneric output polarity or input choices.
All outputs in the simple mode have a maximum of eight productterms that can control the logic. In addition, each output has pro-grammable polarity.
Pins 1 and 11 are always available as data inputs into the ANDarray. The center two macrocells (pins 15 & 16) cannot be usedas input or I/O pins, and are only available as dedicated outputs.
The JEDEC fuse numbers including the UES fuses and PTD fusesare shown on the logic diagram.
Combinatorial Output with Feedback Configurationfor Simple Mode
- SYN=1.- AC0=0.- XOR=0 defines Active Low Output.- XOR=1 defines Active High Output.- AC1=0 defines this configuration.- All OLMC except pins 15 & 16 can be configured to this function.
Combinatorial Output Configuration for Simple Mode
- SYN=1.- AC0=0.- XOR=0 defines Active Low Output.- XOR=1 defines Active High Output.- AC1=0 defines this configuration.- Pins 15 & 16 are permanently configured to this function.
Dedicated Input Configuration for Simple Mode
- SYN=1.- AC0=0.- XOR=0 defines Active Low Output.- XOR=1 defines Active High Output.- AC1=1 defines this configuration.- All OLMC except pins 15 & 16 can be configured to this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Vcc
XOR
Vcc
XOR
Specifications GAL16V8
1996 Data Book9
SIMPLE MODE LOGIC DIAGRAM
DIP & PLCC Package Pinouts
1
11
12
13
14
15
16
17
18
19
2
3
4
5
6
7
9
0000
0224
0256
0480
0512
0736
0768
0992
1024
1248
1280
1504
1536
1760
1792
2016
PTD
2128
2191
8
XOR-2048AC1-2120
OLMC
XOR-2049AC1-2121
XOR-2050AC1-2122
XOR-2051AC1-2123
XOR-2052AC1-2124
XOR-2053AC1-2125
XOR-2054AC1-2126
XOR-2055AC1-2127
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
SYN-2192AC0-2193
2824201612840
Specifications GAL16V8
1996 Data Book10
Specifications GAL16V8D
ABSOLUTE MAXIMUM RATINGS (1) RECOMMENDED OPERATING COND.
Commercial Devices:Ambient Temperature (T
A) ............................... 0 to 75°C
Supply voltage (VCC
) with Respect to Ground ..................... +4.75 to +5.25V
Industrial Devices:Ambient Temperature (T
A) ........................... –40 to 85°C
Supply voltage (VCC
) with Respect to Ground ..................... +4.50 to +5.50V
Supply voltage VCC
...................................... –0.5 to +7VInput voltage applied .......................... –2.5 to V
CC +1.0V
Off-state output voltage applied.......... –2.5 to VCC
+1.0VStorage Temperature................................. –65 to 150°CAmbient Temperature with
Power Applied ........................................ –55 to 125°C1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. Theseare stress only ratings and functional operation of the deviceat these or at any other conditions above those indicated in theoperational sections of this specification is not implied (whileprogramming, follow the programming specifications).
VIL Input Low Voltage Vss – 0.5 — 0.8 V
VIH Input High Voltage 2.0 — Vcc+1 V
IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 µA
IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC — — 10 µA
VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V
VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V
L-3 — — 16 mA
IOL Low Level Output Current L-15/-25 — — 24 mAQ-10/-15/-20/-25
IOH High Level Output Current — — –3.2 mA
IOS2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA= 25°C –30 — –150 mA
DC ELECTRICAL CHARACTERISTICSOver Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL PARAMETER CONDITION MIN. TYP. 3 MAX. UNITS
COMMERCIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -3 — 75 115 mASupply Current ftoggle = 15MHz Outputs Open L-15/-25 — 75 90 mA
Q-10/-15/-25 — 45 55 mA
INDUSTRIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -15/-25 — 75 130 mASupply Current ftoggle = 15MHz Outputs Open Q -20/-25 — 45 65 mA
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by testerground degradation. Guaranteed but not 100% tested.3) Typical values are at Vcc = 5V and TA = 25 °C
Specifications GAL16V8
1996 Data Book11
tpd A Input or I/O to Comb. Output 1 3.5 3 10 3 15 3 20 3 25 ns
tco A Clock to Output Delay 1 3 2 7.5 2 10 2 11 2 12 ns
tcf2 — Clock to Feedback Delay — 2.5 — 6 — 8 — 9 — 10 ns
tsu — Setup Time, Input or Fdbk before Clk↑ 2.5 — 10 — 12 — 13 — 15 — ns
th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — 0 — nsA Maximum Clock Frequency with 182 — 57.1 — 45.5 — 41.6 — 37 — MHz
External Feedback, 1/(tsu + tco)
fmax3 A Maximum Clock Frequency with 200 — 62.5 — 50 — 45.4 — 40 — MHzInternal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with 250 — 62.5 — 62.5 — 50 — 41.6 — MHzNo Feedback
twh — Clock Pulse Duration, High 2 — 8 — 8 — 10 — 12 — ns
twl — Clock Pulse Duration, Low 2 — 8 — 8 — 10 — 12 — ns
ten B Input or I/O to Output Enabled — 4.5 3 10 — 15 — 18 — 20 ns
t B OE to Output Enabled — 4.5 2 10 — 15 — 18 — 20 ns
tdis C Input or I/O to Output Disabled — 4.5 2 10 — 15 — 18 — 20 ns
t C OE to Output Disabled — 4.5 1 10 — 15 — 18 — 20 ns
Specifications GAL16V8D
AC SWITCHING CHARACTERISTICSOver Recommended Operating Conditions
UNITS-25
MIN. MAX.
-20
MIN. MAX.
-15
MIN. MAX.
-10
MIN. MAX.PARAM. DESCRIPTION
TESTCOND1.
-3
MIN. MAX.
COM COM COM / IND IND COM / IND
CAPACITANCE (T A = 25°C, f = 1.0 MHz)
SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS
CI Input Capacitance 8 pF VCC = 5.0V, VI = 2.0V
CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V
*Guaranteed but not 100% tested.
Specifications GAL16V8
1996 Data Book12
Specifications GAL16V8C
VIL Input Low Voltage Vss – 0.5 — 0.8 V
VIH Input High Voltage 2.0 — Vcc+1 V
IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 µA
IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC — — 10 µA
VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V
VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V
IOL Low Level Output Current — — 16 mA
IOH High Level Output Current — — –3.2 mA
IOS2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA= 25°C –30 — –150 mA
ABSOLUTE MAXIMUM RATINGS (1) RECOMMENDED OPERATING COND.
Commercial Devices:Ambient Temperature (T
A) ............................... 0 to 75°C
Supply voltage (VCC
) with Respect to Ground ..................... +4.75 to +5.25V
Supply voltage VCC
...................................... –0.5 to +7VInput voltage applied .......................... –2.5 to V
CC +1.0V
Off-state output voltage applied.......... –2.5 to VCC
+1.0VStorage Temperature................................. –65 to 150°CAmbient Temperature with
Power Applied ........................................ –55 to 125°C1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. Theseare stress only ratings and functional operation of the deviceat these or at any other conditions above those indicated in theoperational sections of this specification is not implied (whileprogramming, follow the programming specifications).
DC ELECTRICAL CHARACTERISTICSOver Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL PARAMETER CONDITION MIN. TYP. 3 MAX. UNITS
COMMERCIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -5/-7 — 75 115 mASupply Current ftoggle = 15MHz Outputs Open
INDUSTRIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -7 — 75 130 mASupply Current ftoggle = 15MHz Outputs Open
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by testerground degradation. Guaranteed but not 100% tested.3) Typical values are at Vcc = 5V and TA = 25 °C
Industrial Devices:Ambient Temperature (TA) ........................... –40 to 85°CSupply voltage (VCC) with Respect to Ground ..................... +4.50 to +5.50V
Specifications GAL16V8
1996 Data Book13
Specifications GAL16V8C
AC SWITCHING CHARACTERISTICSOver Recommended Operating Conditions
-7
MIN. MAX.
-7
MIN. MAX.
tpd A Input or I/O to 8 outputs switching 1 5 3 7.5 1 7.5 nsComb. Output 1 output switching — — — 7 — — ns
tco A Clock to Output Delay 1 4 2 5 1 5 ns
tcf2 — Clock to Feedback Delay — 3 — 3 — 3 ns
tsu — Setup Time, Input or Feedback before Clock↑ 3 — 7 — 7 — ns
th — Hold Time, Input or Feedback after Clock↑ 0 — 0 — 0 — nsA Maximum Clock Frequency with 142.8 — 83.3 — 83.3 — MHz
External Feedback, 1/(tsu + tco)
A Maximum Clock Frequency with 166 — 100 — 100 — MHzInternal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with 166 — 100 — 100 — MHzNo Feedback
twh — Clock Pulse Duration, High 3 — 5 — 5 — ns
twl — Clock Pulse Duration, Low 3 — 5 — 5 — ns
ten B Input or I/O to Output Enabled 1 6 3 9 1 9 nsB OE to Output Enabled 1 6 2 6 1 6 ns
tdis C Input or I/O to Output Disabled 1 5 2 9 1 9 nsC OE to Output Disabled 1 5 1.5 6 1 6 ns
UNITSPARAMETERTEST
COND1.DESCRIPTION
INDCOMCOM
-5
MIN. MAX.
1) Refer to Switching Test Conditions section.2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.3) Refer to fmax Descriptions section. Characterized initially and after any design or process changes that may affect these
parameters.
CAPACITANCE (T A = 25°C, f = 1.0 MHz)
SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS
CI Input Capacitance 8 pF VCC = 5.0V, VI = 2.0V
CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V
*Guaranteed but not 100% tested.
fmax3
Specifications GAL16V8
1996 Data Book14
Specifications GAL16V8B
INDUSTRIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -10/-15/-25 — 75 130 mASupply Current ftoggle = 15MHz Outputs Open Q -20/-25 — 45 65 mA
COMMERCIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -7/-10 — 75 115 mASupply Current ftoggle = 15MHz Outputs Open L -15/-25 — 75 90 mA
Q -15/-25 — 45 55 mA
ABSOLUTE MAXIMUM RATINGS (1) RECOMMENDED OPERATING COND.
Commercial Devices:Ambient Temperature (T
A) ............................... 0 to 75°C
Supply voltage (VCC
) with Respect to Ground ..................... +4.75 to +5.25V
Supply voltage VCC
...................................... –0.5 to +7VInput voltage applied .......................... –2.5 to V
CC +1.0V
Off-state output voltage applied.......... –2.5 to VCC
+1.0VStorage Temperature................................. –65 to 150°CAmbient Temperature with
Power Applied ........................................ –55 to 125°C1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. Theseare stress only ratings and functional operation of the deviceat these or at any other conditions above those indicated in theoperational sections of this specification is not implied (whileprogramming, follow the programming specifications).
Industrial Devices:Ambient Temperature (T
A) ........................... –40 to 85°C
Supply voltage (VCC
) with Respect to Ground ..................... +4.50 to +5.50V
DC ELECTRICAL CHARACTERISTICSOver Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL PARAMETER CONDITION MIN. TYP. 3 MAX. UNITS
VIL Input Low Voltage Vss – 0.5 — 0.8 V
VIH Input High Voltage 2.0 — Vcc+1 V
IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 µA
IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC — — 10 µA
VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V
VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V
IOL Low Level Output Current — — 24 mA
IOH High Level Output Current — — –3.2 mA
IOS2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA= 25°C –30 — –150 mA
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by testerground degradation. Guaranteed but not 100% tested.3) Typical values are at Vcc = 5V and TA = 25 °C
Specifications GAL16V8
1996 Data Book15
Specifications GAL16V8B
AC SWITCHING CHARACTERISTICSOver Recommended Operating Conditions
tpd A Input or I/O to 8 outputs switching 3 7.5 3 10 3 15 3 20 3 25 nsComb. Output 1 output switching — 7 — — — — — — — — ns
tco A Clock to Output Delay 2 5 2 7 2 10 2 11 2 12 ns
tcf2 — Clock to Feedback Delay — 3 — 6 — 8 — 9 — 10 ns
tsu — Setup Time, Input or Fdbk before Clk↑ 7 — 10 — 12 — 13 — 15 — ns
th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — 0 — nsA Maximum Clock Frequency with 83.3 — 58.8 — 45.5 — 41.6 — 37 — MHz
External Feedback, 1/(tsu + tco)
fmax3 A Maximum Clock Frequency with 100 — 62.5 — 50 — 45.4 — 40 — MHzInternal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with 100 — 62.5 — 62.5 — 50 — 41.6 — MHzNo Feedback
twh — Clock Pulse Duration, High 5 — 8 — 8 — 10 — 12 — ns
twl — Clock Pulse Duration, Low 5 — 8 — 8 — 10 — 12 — ns
ten B Input or I/O to Output Enabled 3 9 3 10 — 15 — 20 — 25 nsB OE to Output Enabled 2 6 2 10 — 15 — 18 — 20 ns
tdis C Input or I/O to Output Disabled 2 9 2 10 — 15 — 20 — 25 nsC OE to Output Disabled 1.5 6 1.5 10 — 15 — 18 — 20 ns
UNITS
1) Refer to Switching Test Conditions section.2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.3) Refer to fmax Descriptions section.
-25
MIN. MAX.
-20
MIN. MAX.
-15
MIN. MAX.
-10
MIN. MAX.PARAM. DESCRIPTIONTESTCOND1.
-7
MIN. MAX.
CAPACITANCE (T A = 25°C, f = 1.0 MHz)
SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS
CI Input Capacitance 8 pF VCC = 5.0V, VI = 2.0V
CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V
*Guaranteed but not 100% tested.
COM COM / IND COM / IND IND COM / IND
Specifications GAL16V8
1996 Data Book16
SWITCHING WAVEFORMS
Registered OutputCombinatorial Output
OEOEOEOEOE to Output Enable/DisableInput or I/O to Output Enable/Disable
fmax with Feedback
Clock Width
COMBINATIONALOUTPUT
VALID INPUTINPUT orI/O FEEDBACK
tpd
COMBINATIONALOUTPUT
INPUT orI/O FEEDBACK
tentdis
CLK
(w/o fb)1/fmax
twltwh
INPUT orI/O FEEDBACK
REGISTEREDOUTPUT
CLK
VALID INPUT
(external fdbk)
tsu
tco
th
1/fmax
OE
REGISTEREDOUTPUT
tentdis
CLK
REGISTEREDFEEDBACK
tcf tsu1/fmax (internal fdbk)
Specifications GAL16V8
1996 Data Book17
fmax DESCRIPTIONS
fmax with Internal Feedback 1/( tsu+tcf)
Note: tcf is a calculated value, derived by subtracting tsu fromthe period of fmax w/internal feedback (tcf = 1/fmax - tsu). Thevalue of tcf is used primarily when calculating the delay fromclocking a register to a combinatorial output (through registeredfeedback), as shown above. For example, the timing from clockto a combinatorial output is equal to tcf + tpd.
fmax with External Feedback 1/( tsu+ tco)
Note: fmax with external feedback is calculated from measuredtsu and tco.
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). Thisis to allow for a clock duty cycle of other than 50%.
SWITCHING TEST CONDITIONS
REGISTERLOGICARRAY
CLK
tsu + th
REGISTERLOGICARRAY
tcotsu
CLK
Test Condition R 1 R2 CL
A 200Ω 390Ω 50pFB Active High ∞ 390Ω 50pF
Active Low 200Ω 390Ω 50pFC Active High ∞ 390Ω 5pF
Active Low 200Ω 390Ω 5pF
CLK
REGISTER
LOGICARRAY
tcftpd
TEST POINT
C *L
FROM OUTPUT (O/Q) UNDER TEST
+5V
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R 2
R 1
Input Pulse Levels
Table 2-0003/16V8
Input Rise and Fall Times
Input Timing Reference Levels
Ouput Timing Reference Levels
Output Load
GND to 3.0V
1.5V
1.5V
See figure at right3-state levels are measured 0.5V from steady-state active level.
2 – 3ns 10% – 90%
1.5ns 10% – 90%
GAL16V8B andGAL16V8D-10 (andslower)
GAL16V8C andGAL16V8D-3
GAL16V8B and GAL16V8D-10/-15/-20/-25 Output LoadConditions (see figure above) GAL16V8C Output Load Conditions (see figure above)
Test Condition R 1 R2 CL
A 200Ω 200Ω 50pFB Active High ∞ 200Ω 50pF
Active Low 200Ω 200Ω 50pFC Active High ∞ 200Ω 5pF
Active Low 200Ω 200Ω 5pF
Specifications GAL16V8
1996 Data Book18
SWITCHING TEST CONDITIONS, CONTINUED
*CL includes test fixture and probe capacitance.
ELECTRONIC SIGNATURE
An electronic signature is provided in every GAL16V8 device. Itcontains 64 bits of reprogrammable memory that can contain userdefined data. Some uses include user ID codes, revision num-bers, or inventory control. The signature data is always availableto the user independent of the state of the security cell.
NOTE: The electronic signature is included in checksum calcu-lations. Changing the electronic signature will alter the checksum.
SECURITY CELL
A security cell is provided in the GAL16V8 devices to prevent un-authorized copying of the array patterns. Once programmed, thiscell prevents further read access to the functional bits in the de-vice. This cell can only be erased by re-programming the device,so the original configuration can never be examined once this cellis programmed. The Electronic Signature is always available tothe user, regardless of the state of this control cell.
LATCH-UP PROTECTION
GAL16V8 devices are designed with an on-board charge pumpto negatively bias the substrate. The negative bias minimizes thepotential of latch-up caused by negative input undershoots.Additionally, outputs are designed with n-channel pull-ups insteadof the traditional p-channel pull-ups in order to eliminate latch-updue to output overshoots.
DEVICE PROGRAMMING
GAL devices are programmed using a Lattice Semiconductor-approved Logic Programmer, available from a number of manu-facturers. Complete programming of the device takes only a fewseconds. Erasing of the device is transparent to the user, and isdone automatically as part of the programming cycle.
OUTPUT REGISTER PRELOAD
When testing state machine designs, all possible states and statetransitions must be verified in the design, not just those requiredin the normal machine operations. This is because, in systemoperation, certain events occur that may throw the logic into anillegal state (power-up, line voltage glitches, brown-outs, etc.). Totest a design for proper treatment of these conditions, a way mustbe provided to break the feedback paths, and force any desired(i.e., illegal) state into the registers. Then the machine can besequenced and the outputs tested for correct next state conditions.
GAL16V8 devices include circuitry that allows each registeredoutput to be synchronously set either high or low. Thus, anypresent state condition can be forced for test sequencing. Ifnecessary, approved GAL programmers capable of executing textvectors perform output register preload automatically.
INPUT BUFFERS
GAL16V8 devices are designed with TTL level compatible inputbuffers. These buffers have a characteristically high impedance,and present a much lighter load to the driving logic than bipolarTTL devices.
The GAL16V8 input and I/O pins have built-in active pull-ups. Asa result, unused inputs and I/O's will float to a TTL "high" (logi-cal "1"). Lattice Semiconductor recommends that all unusedinputs and tri-stated I/O pins be connected to another active input,VCC, or Ground. Doing this will tend to improve noise immunityand reduce ICC for the device.
Typical Input Pull-up Characteristic
1 . 0 2 . 0 3 . 0 4 . 0 5 . 0- 6 0
0
- 2 0
- 4 0
0
In p u t Vo ltag e (V o lt s)
Inp
ut
Cu
rre
nt
(uA
)
TEST POINT
Z0 = 50Ω, CL = 35pF*FROM OUTPUT (O/Q)UNDER TEST
+1.45V
R1
GAL16V8D-3 Output Load Conditions (see figure at right)
Test Condition R 1 CL
A 50Ω 35pFB High Z to Active High at 1.9V 50Ω 35pF
High Z to Active Low at 1.0V 50Ω 35pFC Active High to High Z at 1.9V 50Ω 35pF
Active Low to High Z at 1.0V 50Ω 35pF
Specifications GAL16V8
1996 Data Book19
Typ. Vref = 3.2V
Typical Output
Typ. Vref = 3.2V
Typical Input
INPUT/OUTPUT EQUIVALENT SCHEMATICS
POWER-UP RESET
Circuitry within the GAL16V8 provides a reset signal to all reg-isters during power-up. All internal registers will have their Qoutputs set low after a specified time (tpr, 1µs MAX). As a result,the state on the registered output pins (if they are enabled) willalways be high on power-up, regardless of the programmedpolarity of the output pins. This feature can greatly simplify statemachine design by providing a known state on power-up. Be-cause of the asynchronous nature of system power-up, some
Vcc
PIN
Vcc Vref
Active Pull-up Circuit
ESD ProtectionCircuit
ESD ProtectionCircuit
Vcc
PIN
Vcc
PIN
VrefTri-StateControl
Active Pull-up Circuit
Feedback(To Input Buffer)
PIN
Feedback
Data Output
Vcc
CLK
INTERNAL REGISTERQ - OUTPUT
FEEDBACK/EXTERNALOUTPUT REGISTER
Vcc (min.)
tprInternal RegisterReset to Logic "0"
Device PinReset to Logic "1"
twl
tsu
conditions must be met to guarantee a valid power-up reset of thedevice. First, the VCC rise must be monotonic. Second, the clockinput must be at static TTL level as shown in the diagram duringpower up. The registers will reset within a maximum of tpr time.As in normal system operation, avoid clocking the device until allinput and feedback path setup times have been met. The clockmust also meet the minimum pulse width requirements.
Specifications GAL16V8
1996 Data Book20
GAL 16V8D-3: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
0.8
0.9
1
1.2
4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Nor
mal
ized
Tpd
Normalized Tco vs Vcc
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Nor
mal
ized
Tco
Normalized Tsu vs Vcc
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Nor
mal
ized
Tsu
Normalized Tpd vs Temp
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Nor
mal
ized
Tpd
Normalized Tco vs Temp
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Nor
mal
ized
Tco
Normalized Tsu vs Temp
0.7
0.9
1
1.1
-55 -25 0 25 50 75 100 125
Temperature (deg. C)N
orm
aliz
ed T
su
PT H->LPT L->H
PT H->LPT L->H1.1
PTH->LPT L->H
1.3
1.2
0.8
RISEFALL
PT H->LPT L->H
RISEFALL
Delta Tpd vs # of OutputsSwitching
-0.4
-0.3
-0.2
-0.1
0
1 2 3 4 5 6 7 8
Number of Outputs Switching
Del
ta T
pd (
ns)
Delta Tco vs # of OutputsSwitching
-0.4
-0.3
-0.2
-0.1
0
1 2 3 4 5 6 7 8
Number of Outputs Switching
Del
ta T
co (
ns)
Delta Tpd vs Output Loading
-2
10
12
14
0 50 100 150 200 250 300
Output Loading (pF)
Del
ta T
pd (
ns)
Delta Tco vs Output Loading
-2
0
14
12
10
8
6
4
2
0 50 100 150 200 250 300
Output Loading (pF)
Del
ta T
co (
ns)
RISEFALL
RISEFALL
RISEFALL
RISEFALL
8
6
4
2
0
Specifications GAL16V8
1996 Data Book21
GAL 16V8D-3: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
0
0.25
0.5
0.75
1
0 10 20 30 40
Iol (mA)
Vol
(V
)
Voh vs Ioh
0
1
2
3
4
5
0 10 20 30 40 50
Ioh (mA)
Voh
(V
)
Voh vs Ioh
2.5
2.75
3
3.25
0 1 2 3 4
Ioh (mA)
Voh
(V
)
Normalized Icc vs Vcc
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Nor
mal
ized
Icc
Normalized Icc vs Temp
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Nor
mal
ized
Icc
Normalized Icc vs Freq.
0.9
0.95
1
1.05
1.1
1.15
1.2
0 25 50 75 100
Frequency (MHz)
Nor
mal
ized
Icc
Delta Icc vs Vin (1 input)
0
2
4
6
8
10
0 0.5 1 1.5 2 2.5 3 3.5 4
Vin (V)
Del
ta Ic
c (m
A)
Input Clamp (Vik)
0
10
20
30
40
50
60
70
80
90-2 -1.5 -1 -0.5 0
Vik (V)
Iik (
mA
)
Specifications GAL16V8
1996 Data Book22
GAL 16V8D-10 (and Slower): TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Nor
mal
ized
Tpd PT H->L
PT L->H
Normalized Tco vs Vcc
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)N
orm
aliz
ed T
co
RISEFALL
Normalized Tsu vs Vcc
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Nor
mal
ized
Tsu PT H->L
PT L->H
Normalized Tpd vs Temp
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Nor
mal
ized
Tpd
PT H->LPT L->H
Normalized Tco vs Temp
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Nor
mal
ized
Tco
RISEFALL
Normalized Tsu vs Temp
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Temperature (deg. C)N
orm
aliz
ed T
su
PT H->LPT L->H
Delta Tpd vs # of Outputs Switching
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
1 2 3 4 5 6 7 8
Number of Outputs Switching
Del
ta T
pd (
ns)
RISEFALL
Delta Tco vs # of Outputs Switching
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
1 2 3 4 5 6 7 8
Number of Outputs Switching
Del
ta T
co (
ns)
RISEFALL
Delta Tpd vs Output Loading
-6
-4
-2
0
2
4
6
8
10
12
0 50 100 150 200 250 300
Output Loading (pF)
Del
ta T
pd (
ns) RISE
FALL
Delta Tco vs Output Loading
-4
-2
0
2
4
6
8
10
12
0 50 100 150 200 250 300
Output Loading (pF)
Del
ta T
co (
ns) RISE
FALL
Specifications GAL16V8
1996 Data Book23
GAL 16V8D-10 (and Slower): TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
0
0.2
0.4
0.6
0 10 20 30 40
Iol (mA)
Vol
(V
)
Voh vs Ioh
0
1
2
3
4
5
0 10 20 30 40 50
Ioh (mA)V
oh (
V)
Voh vs Ioh
3
3.2
3.4
3.6
3.8
4
0 1 2 3 4
Ioh (mA)
Voh
(V
)
Normalized Icc vs Vcc
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Nor
mal
ized
Icc
Normalized Icc vs Temp
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Nor
mal
ized
Icc
Normalized Icc vs Freq.
0.8
0.9
1
1.1
1.2
1.3
1.4
0 25 50 75 100
Frequency (MHz)N
orm
aliz
ed Ic
c
Delta Icc vs Vin (1 input)
0
2
4
6
8
0 0.5 1 1.5 2 2.5 3 3.5 4
Vin (V)
Del
ta Ic
c (m
A)
Input Clamp (Vik)
0
10
20
30
40
50
60-2 -1.5 -1 -0.5 0
Vik (V)
Iik (
mA
)
Specifications GAL16V8
1996 Data Book24
Delta Tpd vs # of OutputsSwitching
Number of Outputs Switching
Del
ta T
pd (
ns)
-1
-0.75
-0.5
-0.25
0
1 2 3 4 5 6 7 8
RISE
FALL
Delta Tco vs # of OutputsSwitching
Number of Outputs Switching
Del
ta T
co (
ns)
-1
-0.75
-0.5
-0.25
0
1 2 3 4 5 6 7 8
RISE
FALL
Delta Tpd vs Output Loading
Output Loading (pF)
Del
ta T
pd (
ns)
-2
0
2
4
6
8
0 50 100 150 200 250 300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Del
ta T
co (
ns)
-2
0
2
4
6
8
0 50 100 150 200 250 300
RISE
FALL
Normalized Tpd vs Vcc
Supply Voltage (V)
Nor
mal
ized
Tpd
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
PT H->L
PT L->H
Normalized Tco vs Vcc
Supply Voltage (V)N
orm
aliz
ed T
co
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)
Nor
mal
ized
Tsu
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
PT H->L
PT L->H
Normalized Tpd vs Temp
Temperature (deg. C)
Nor
mal
ized
Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25 0
25
50
75
10
0
12
5
PT H->L
PT L->H
Normalized Tco vs Temp
Temperature (deg. C)
Nor
mal
ized
Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25 0
25
50
75
10
0
12
5
RISE
FALL
Normalized Tsu vs Temp
Temperature (deg. C)N
orm
aliz
ed T
su
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55
-25 0
25
50
75
10
0
12
5
PT H->L
PT L->H
GAL 16V8C-5/-7: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Specifications GAL16V8
1996 Data Book25
GAL 16V8C-5/-7: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
Iol (mA)
Vol
(V
)
0
0.5
1
1.5
2
0.00 20.00 40.00 60.00 80.00
Voh vs Ioh
Ioh(mA)
Voh
(V
)0
1
2
3
4
5
0.00 10.00 20.00 30.00 40.00 50.00
Voh vs Ioh
Ioh(mA)
Voh
(V
)
3.25
3.5
3.75
4
4.25
0.00 1.00 2.00 3.00 4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Nor
mal
ized
Icc
0.80
0.90
1.00
1.10
1.20
4.50 4.75 5.00 5.25 5.50
Normalized Icc vs Temp
Temperature (deg. C)
Nor
mal
ized
Icc
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Normalized Icc vs Freq.
Frequency (MHz)N
orm
aliz
ed I
cc
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
0 25 50 75 100
Delta Icc vs Vin (1 input)
Vin (V)
Del
ta I
cc (
mA
)
0
2
4
6
8
10
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Input Clamp (Vik)
Vik (V)
Iik (
mA
)
0
5
10
15
20
25
30
35
40
45
-2.00 -1.50 -1.00 -0.50 0.00
Specifications GAL16V8
1996 Data Book26
GAL 16V8B-7/-10: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
Supply Voltage (V)
Nor
mal
ized
Tpd
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
PT H->L
PT L->H
Normalized Tco vs Vcc
Supply Voltage (V)N
orm
aliz
ed T
co0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)
Nor
mal
ized
Tsu
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
PT H->L
PT L->H
Normalized Tpd vs Temp
Temperature (deg. C)
Nor
mal
ized
Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25 0
25
50
75
10
0
12
5
PT H->L
PT L->H
Normalized Tco vs Temp
Temperature (deg. C)
Nor
mal
ized
Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55
-25 0
25
50
75
10
0
12
5
RISE
FALL
Normalized Tsu vs Temp
Temperature (deg. C)N
orm
aliz
ed T
su
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55
-25 0
25
50
75
10
0
12
5
PT H->L
PT L->H
Delta Tpd vs # of OutputsSwitching
Number of Outputs Switching
Del
ta T
pd (
ns)
-2
-1.5
-1
-0.5
0
1 2 3 4 5 6 7 8
RISE
FALL
Delta Tco vs # of OutputsSwitching
Number of Outputs Switching
Del
ta T
co (
ns)
-2
-1.5
-1
-0.5
0
1 2 3 4 5 6 7 8
RISE
FALL
Delta Tpd vs Output Loading
Output Loading (pF)
Del
ta T
pd (
ns)
-2
0
2
4
6
8
10
0 50 100 150 200 250 300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Del
ta T
co (
ns)
-2
0
2
4
6
8
10
0 50 100 150 200 250 300
RISE
FALL
Specifications GAL16V8
1996 Data Book27
GAL 16V8B-7/-10: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
Iol (mA)
Vol
(V
)
0
0.25
0.5
0.75
1
0.00 20.00 40.00 60.00 80.00 100.00
Voh vs Ioh
Ioh(mA)
Voh
(V
)0
1
2
3
4
5
0.00 10.00 20.00 30.00 40.00 50.00 60.00
Voh vs Ioh
Ioh(mA)
Voh
(V
)
3.5
3.75
4
4.25
4.5
0.00 1.00 2.00 3.00 4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Nor
mal
ized
Icc
0.80
0.90
1.00
1.10
1.20
4.50 4.75 5.00 5.25 5.50
Normalized Icc vs Temp
Temperature (deg. C)
Nor
mal
ized
Icc
0.8
0.9
1
1.1
1.2
-55 -25 0 25 50 75 100 125
Normalized Icc vs Freq.
Frequency (MHz)N
orm
aliz
ed I
cc
0.80
0.90
1.00
1.10
1.20
1.30
0 25 50 75 100
Delta Icc vs Vin (1 input)
Vin (V)
Del
ta I
cc (
mA
)
0
2
4
6
8
10
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Input Clamp (Vik)
Vik (V)
Iik (
mA
)
0
10
20
30
40
50
60
70
80
90
100
-2.00 -1.50 -1.00 -0.50 0.00
Specifications GAL16V8
1996 Data Book28
GAL 16V8B-15/-25: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
Supply Voltage (V)
Nor
mal
ized
Tpd
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
PT H->L
PT L->H
Normalized Tco vs Vcc
Supply Voltage (V)N
orm
aliz
ed T
co
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)
Nor
mal
ized
Tsu
0.8
0.9
1
1.1
1.2
4.50 4.75 5.00 5.25 5.50
PT H->L
PT L->H
Normalized Tpd vs Temp
Temperature (deg. C)
Nor
mal
ized
Tpd
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
PT H->L
PT L->H
Normalized Tco vs Temp
Temperature (deg. C)
Nor
mal
ized
Tco
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
RISE
FALL
Normalized Tsu vs Temp
Temperature (deg. C)
Nor
mal
ized
Tsu
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-55 -25 0 25 50 75 100 125
PT H->L
PT L->H
Delta Tpd vs # of OutputsSwitching
Number of Outputs Switching
Del
ta T
pd (
ns)
-2
-1.5
-1
-0.5
0
1 2 3 4 5 6 7 8
RISE
FALL
Delta Tco vs # of OutputsSwitching
Number of Outputs Switching
Del
ta T
co (
ns)
-2
-1.5
-1
-0.5
0
1 2 3 4 5 6 7 8
RISE
FALL
Delta Tpd vs Output Loading
Output Loading (pF)
Del
ta T
pd (
ns)
-2
0
2
4
6
8
10
12
0 50 100 150 200 250 300
RISE
FALL
Delta Tco vs Output Loading
Output Loading (pF)
Del
ta T
co (
ns)
-2
0
2
4
6
8
10
12
0 50 100 150 200 250 300
RISE
FALL
Specifications GAL16V8
1996 Data Book29
GAL 16V8B-15/-25: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
Iol (mA)
Vol
(V
)
0
0.5
1
1.5
2
0.00 20.00 40.00 60.00 80.00 100.00
Voh vs Ioh
Ioh(mA)
Voh
(V
)0
1
2
3
4
5
0.00 10.00 20.00 30.00 40.00 50.00 60.00
Voh vs Ioh
Ioh(mA)
Voh
(V
)
3.25
3.5
3.75
4
4.25
0.00 1.00 2.00 3.00 4.00
Normalized Icc vs Vcc
Supply Voltage (V)
Nor
mal
ized
Icc
0.80
0.90
1.00
1.10
1.20
4.50 4.75 5.00 5.25 5.50
Normalized Icc vs Temp
Temperature (deg. C)
Nor
mal
ized
Icc
0.8
0.9
1
1.1
1.2
-55 -25 0 25 50 75 100 125
Normalized Icc vs Freq.
Frequency (MHz)N
orm
aliz
ed I
cc
0.80
0.90
1.00
1.10
1.20
1.30
1.40
0 25 50 75 100
Delta Icc vs Vin (1 input)
Vin (V)
Del
ta I
cc (
mA
)
0
2
4
6
8
10
12
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Input Clamp (Vik)
Vik (V)
Iik (
mA
)
0
10
20
30
40
50
60
70
80
90
100
-2.00 -1.50 -1.00 -0.50 0.00
Copyright © 1996 Lattice Semiconductor Corporation.
E2CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, Lattice Logo, L with Lattice Semiconductor Corp. and L(Stylized) are registered trademarks of Lattice Semiconductor Corporation (LSC). The LSC Logo, Generic Array Logic, In-System Programmability, In-System Programmable, ISP, ispATE, ispCODE, ispDOWNLOAD, ispGDS, ispStarter,ispSTREAM, ispTEST, ispTURBO, Latch-Lock, pDS+, RFT, Total ISP and Twin GLB are trademarks of Lattice SemiconductorCorporation. ISP is a service mark of Lattice Semiconductor Corporation. All brand names or product names mentioned aretrademarks or registered trademarks of their respective holders.
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The specifications and information herein are subject to change without notice. Lattice Semiconductor Corporation (LSC)reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errorscontained herein or to advise any user of this document of any correction if such be made. LSC recommends its customersobtain the latest version of the relevant information to establish, before ordering, that the information being relied upon iscurrent.
LSC warrants performance of its products to current and applicable specifications in accordance with LSC’s standardwarranty. Testing and other quality control procedures are performed to the extent LSC deems necessary. Specific testing ofall parameters of each product is not necessarily performed, unless mandated by government requirements.
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LATTICE SEMICONDUCTOR CORPORATION5555 Northeast Moore CourtHillsboro, Oregon 97124 U.S.A.Tel.: (503) 681-0118FAX: (503) 681-3037http://www.latticesemi.com November 1996
Main DirectoryGAL16V8 Data SheetPin ConfigurationOrdering Information16V8D: DC Electrical Characteristics16V8D: AC Characteristics16V8C: DC Electrical Characteristics16V8C: AC Characteristics16V8B: DC Electrical Characteristics16V8B: AC Characteristics