Upload
verity-kennedy
View
223
Download
1
Embed Size (px)
Citation preview
General Fixed Radix Number Systems
• Nonredundant• Positive radix, ß• n digits in digit set• Vector:
1 2 0( , , , )n n { 1,1}i
i ii allows or
1
0
ni
i ii
X x
i
i iw
General Fixed Radix Number Systems• For Given Radix and n, how many number systems?
• ANSWER: Number equal to all possible permutationsof n choose –1 (or +1),
0 1 2
n n n n
n
0
2n
n
i
n
i
Choose -1
Positive Radix
Negative Radix
• Of these, 1 is Pos. Radix 1 is Neg. Radix
• The following is the Radix-complement:( 1,1,1,1, ,1,1)
General FR Number Systems - Properties
P Largest Representable Integer
1 2 0( )n nP p p p
N Smallest Representable Integer
pi are Digits of P
1, 1
0 ,i
i
ifp
otherwise
1( 1)( 1)
2i ip
General FR Number Systems - Properties
1 1 1
0 0 0
1 1( 1)( 1) ( 1) ( 1)
2 2
n n ni i i
i ii i i
P
Using the pi Expression and Forming the Radix Polynomial for P
1 11
0 0
1 1( 1) ( )
2 2
n ni i i
i i
Q Q
digit
weightDefine as Q
1n
1( 1)
2nP Q
General FR Number Systems - Properties
( 1, 1, 1, , 1)
Q is the value represented by the following n-tuple if all i=1
For N, the Smallest Representable Value:
1 2 1 0( )n nN y y y y
1, 1
0 ,i
i
ify
otherwise
1( 1)( 1)
2i iy
General FR Number Systems - Properties
1 1 1
0 0 0
1 1( 1)( 1) ( 1) ( 1)
2 2
n n ni i i
i ii i i
N
Using Similar Analysis as With the Case of P:
1 11
0 0
1 1( 1) ( )
2 2
n ni i i
i i
Q Q
digit
weightDefine as Q
1n
1( 1)
2nN Q
General FR Number Systems –Symmetry
Summarizing:
N X P Where 1 nP N
• In General These Bounds are Asymmetric
• Measure of Asymmetry is:
| |P N P N Q
• Therefore, Q is a Measure of Asymmetry for GeneralizedFixed Radix Number Systems
GFRNS – Asymmetry Examples
Consider the Negative Radix System:
Asymmetric Range:n even times as many negative as positive values n odd times as many positive as negative values
| |P N P N Q ulp
2’s Complement:
( , 1, 1, 1, 1, )
2 ( 1, 1, 1, 1, , 1)
(1 more negative number)
| |P N P N Q ulp
System:
2 ( 1, 1, 1, 1, , 1)
(1 more positive number)
GFRNS – Complement
Recall that a complement of a digit, xi, is:
The Complement of a Value, X, is Calculated as:
( 1)i ix x
1 1 1
0 0 0
( 1)n n n
i i ii i i i i
i i i
X x x
Q X
X Q X Thus,
( )X X Q X Q
Signed-Digit Number Systems
• Fixed radix (positional)• Allows each digit to carry a sign
{ 1, 2,....,1,0,1,...., 1}ix
i i
example
This signed digit (SD) is a new definition of the digit complement
Signed-Digit Example
{9,8,....,1,0,1,....,8,9}ix
min max99, 99
[ 99,99]
1
X X
X
ulp
for a total of 19 possible digits
If n = 2
199 values, however there are 192 = 361 representations possible which implies this is a redundant number system
10
Signed-Digit Example - Redundancy
[ 99,99]X
19 possible digits
199 values and 192 = 361 representations implies redundancy
{9,8,....,1,0,1,....,8,9}ix
361 199% 81.4%
199redundancy
10(12) (08) ( 8)ix Example redundant representation:
For n = 2, range is
Redundancy Index, = + + 1 – r for digit set is [- , ]Here, = 9 + 9 + 1 – 10 = 9, but if = 0 & =9, then = 0.
Restricting Redundancy{ , 1, ,1,0,1 , }
11, 5 9 ( 10)
2
ix a a a
where
ra r a r
2
6
66 66 133
(13) 169
(12) 8
169 133% 27%, 6 6 1 10 3
133
Let a
Range of x includes numbers
representations
unique
redundancy
Signed-Digit Characteristics
• Positive radix, ß > 0
• X = 0 is unique
• Easy to convert
• Constant Delay for Add/Sub Regardless of Word Size
Breaking the Carry Chain Using SDCan make sum only a function of two digit positions
),,,( 11 iiiii yxyxfs
1
1 ( )
1 ( )
0 )
i i
i i i
i i i
if x y a
t if x y a
if x y a
1i i i iw x y rt
Carry-Free Addition AlgorithmStep 1: Find interim sum wi and transfer digit ti+1 where
and
Step 2: Find final sum si
0: 0i i is w t note t
positional sum pi
Signed Digit Addition Hardware
ix
1ix
1ix
iy
1iy
1iy
is
1is
1is
it
1it
2it
2it
iw
1iw
1iw
SD Addition Example
Let a = 6 for r = 10
1
1
{6, 5, , 1,0,1, ,5,6}
( ) 10
1 ( ) 6
1 ( ) 6
0
i
i i i i
i i
i i i
i i i
x
w x y t
if x y
t if x y
otherwise
s w t
SD Addition Example (Continued)
Let X = 1634, Y = 3366Using normal addition produces a carry chain
1 1 1
1 6 3 4
3 3 6 6
5 0 0 0
X
Y
But by the carry-free algorithm
1 6 3 4
3 3 6 60 1 1 1 0
4 1 1 0
5 0 0 0
i
i
i
X
Yt
w
s
Converting Decimal to SD
Let r = 10, a = 6Consider the value as xi + yi and use algorithm
Converting from SD to decimal – just sum plus and minus weights
2030 – 204 = 1826
1 8 2 6
0 1 0 1 0
1 2 2 4
2 2 3 4
i i
i
i
i
x y
t
w
s
Selecting a to Eliminate Carry Chain in SD
For no carry, require
{ , 1, ,1,0,1, , 1, }
1
1 (1)
, 1
i
i i i
i
i
i i i
s a a a a
s w t a
worst case t restricting
w a equation
must be true for all x y where t
Selecting a to Eliminate Carry Chain in SD1: 2
(2 ) (1) 2
(1)
2 1 1 ( )
2 :
( ) (1) 0
(1)
1
12 1 ( )
2
11
2
i i
i
i i
i
i
Case x y a
w a r a r
By
a r a or a r upper bound
Case x y a
w a r a r
w r a
By
r a a
ra r or a lower bound
ra r
Binary SD Addition
2 , 1, ( , 1,0,1 )
11 2 !
2
For r a only one digit set
rr a impossible for digit set
Implies no guarantee that si = wi + ti will not produce a carry
Looking at algorithm:Step 1:
1
1
( ) 2
1 1
1 1
0 0
i i i i
i i
i i i
i i
w x y t
if x y
t if x y
if x y
Unmodified Binary SD Addition Table
xi,yi
ti+1
wi
11 1111010100
10
0 0 0 0
01
1
11
1
Step 2: Based on calculation of wi and ti+1
10
1 1
0 1 0 1
i i is w t
Note: redundancy allows choices for wi and ti+1
How Useful is Unmodified Table?
Works if operands do not contain If operands contain only 0’s and 1’s, no carry generated.
1
0 1 0 1or or
i i is w t
1 1 .... 1 1 1
0 0 .... 0 0 11 1 1 .... 1 1
1 1 .... 1 1 0
1 0 0 .... 0 0 0
i
i
i
t
w
s
Example
Why not use this approach to break carry chain for unsigned binary number?
Limitations of Table
1 1
1 01
1 01, 11
.
i i i
i i i
i
If w x y
and t x y
s has carry
0 1 1 1 1 1
1 0 0 1 0 1
1 1 1 1 1 1
1 1 1 0 1 0
* * * * 1 0 0
i
i
i
t
w
s
carries
Example (-9)10 + (29)10
Does not work if operands contain 1
SD Addition Table Choices
11
01
01
1 0
0
1
1
1
1000
1011
11
11
01
01
00
00
ix iy
i it w
i it w
1 1 0,1i ix or y
1 1 1i ix or y
Takagi, 1985
Modified Binary SD Addition Table
xi,yi
xi-1,yi-1 -neither is at least
one is neither is at least
one is - -
ti+1
wi
1101 11010100,11
1
0
0
0
0 0
1
1 1
1
1
0 11
01
1
11
1
Repeating Example with Modified Table
Example (-9)10 + (29)10
0 1 1 1 1 1
1 0 0 1 0 1
0 0 0 1 1 1
1 1 1 0 1 0
1 1 0 1 0 0
i
i
i
t
w
s
no carries
Two SD Encodings
x
Encoding 1
xh xl
Encoding 2
xh xl
0 00 00
1 01 01
1 10 11
4!=24 possible encodingsOnly nine are distinct under permutation and logical negation two’s complement
Encoding 1
Satisfies simple relation
x = xl - xh
and 11 has a valid numerical value of 0.
SD to two’s complement conversion performed by two’s complement subtraction
1 2 0
1 2 0
, , ,
, , ,
l l ln n
h h hn n
x x x
x x x
Encoding 2
Satisfies relation
xi = -2xih + xi
l
This means that xil and xi-1
h have the same weight
Also simplified addition table possible by regrouping bits
1 ˆ, ,l hi i ix and x can be regrouped to form x
Two’s Complement/BSD Conversion
Two’s Complement to SDBits can be encoded directly with MSB negative one
BSD to Two’s Complement
1
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
1 0 1 1
1 1 0 1
i i i iy c z c
12i i i iy c z c
One algorithm simpler than complete binary adder zi is two’s complement result c0 = 0
0 1 0 1 01 1 1 1 0 0
1 0 1 1 0
i
i
i
yc
z
Example -1010
Binary SD RepresentationsRepresentation of a value with the minimum number of non-zero digits – Important in multiplication and division since each zero eliminates an operation
8 4 2 1
0 1 0 1
1 0 1 1 .
0 1 1 1
1 1 0 1
1 1 1 1
Minimal SD representation of X = 5
X = 5, n = 4, r = 2
Alternate Class of BSD Addition Tables*
*see M. Thornton, A Signed Binary Addition Circuit Based on an Alternative Class of Addition Tables
xi,yi
ti+1
wi
11 1111010100
10
0 0 0 0
01
1
11
1
Motivation: Previous tables based on calculation ofwhere wi and ti require 2-bit encoding
i i is w t
Alternative restricts these values to {0,1} or {1,0}
Note: In the discussion ci will be used in place of ti and ui for wi
Basic Idea for Alternate SBD Representation
• Restrict
1 1
0,1 1,0
1,0 0,1
2( )
2, 1,0,1,2
i i
i i
i i i i i i
i i i
i i
c u
or
c u
where
x y u c b b
s u c
x y
• Add 2bi+1 since it is “borrowed” from i+1 column• Subtract bi since it is “borrowed” from i-1 column
Basic SD Addition Tables
1 0 1
1 2 1 0
0 1 0 1
1 0 1 2
1 0 1
1 10 01 00
0 01 00 01
1 00 01 10
i i ix y s iy
ix
12i i i ix y u c iy
ix 0 1
1 1
1 0
0 1
0 * 0
Both have inherent propagation limitations
Alternative 1 BSD Addition Table*
iy
ix 1 0 1
11
0 11
0 01
1 1
0 0 1 1 1 0
01
0 00
0 10
0 0
1 1 0 0 1 1
11
1 10
0 00
1 1
1 0 1 1 1 0
bi+1
ci+1 ui
ci+1 ui
bi=1
bi=0
1 1
0,1 1,0 1,0
1 1 2
2( )
1 2 1 2
i i i
i i
i i i i
c u b
x y
u c b b
* Table 2 of Thornton paper
Alternative 2 BSD Addition Table*
iy
ix 1 0 1
10
1 00
1 11
1 0
1 1 0 0 1 1
00
1 10
0 01
1 1
0 0 0 1 0 0
11
1 01
1 11
0 0
1 1 0 0 0 1
bi+1
ci+1 ui
ci+1 ui
bi=1
bi=0
1,0 0,1 0,1
1 0 1 1 1 0 0
0 1 1 0 1 0 11 0 0 0 1 0 0
1 1 0 0
0
0
0 0 1
1 1 1 0 0 0 1
0 0 0 0 0 1
1
1
0
0 0
i i ic u b
X
YBU
C
S
* Table 4 of Thornton paper
Signed Binary Addition Hardware Using Intermediate Borrow and Carry
ix
1ix
1ix
iy
1iy
1iyis
1is
ic
1iciu
1iu
2ix2iy
2ib
2ix2iy
1iu
2ic1
1
1
1
1
1
12
22
2
2
22
2
2
2
2
2
2
2
2
2
2
2
1
1
1
Encoding Scheme For Even Parity*
• Choose 1 00
0 01 11
1 10
or
• Then each successive pair of signed binary digits canbe grouped with even parity
• Single bit error coverage over digit pairs
3 11 0000
2 10 0011
1 01 1100
0 00 0101 1111
1 01 0110
2 10 1001
3 11 1010
value pair encoding
or
*see M. Thornton, Signed Binary Addition Circuitry with Inherent Even Parity Outputs