George Mason University

Volgenau School of Engineering

Senior Design Project 2012

JACOB DILLES, PM

JASON HARTMAN

MARY HATFIELD

KEVIN NICOTERA

ELTON WILLIAMS

DR. QILIANG LI, ECE SUPERVISOR DR. MINGZHEN TIAN, PHYSICS SUPERVISOR DR. PIOTR PACHOWICZ, COURSE COORDINATOR DR. WILLIAM SUTTON, ASSOCIATE CHAIR

TEAM SPECTRUM

Please hold questions / concerns

regarding safety until

the end of the presentation.

We will cover our safety plan in detail.

OSA = Optical Spectrum Analyzer

We have spectrum analyzers to show:

Audio: up to ≈40kHz (10^4)

RF: up to several GHz (10^9)

Optical frequencies: THz (10^15!)

Can’t process these frequencies

electronically

Three components:

1. Scanning Fabry-Pérot Interferometer (SFPI)

2. Controller

3. Oscilloscope

LC = Electrical Resonance

Two Mirrors = Optical Resonance

Distance between sets ω0

Piezoelectric motor (AKA PZT) “tuning”

‘Q’ ‘Finesse’ , Photo detector out

FSR ∝ mirror distance, c/2L

Fixed mirror distance: peaks every FSR

Moving mirrors (L): peaks every FSR

Moves mirrors

Adjustable rate, distance, start position

Amplifies Detector

Adjustable gain

Used as display

Controller: Ramp(time) Motor Voltage

SFPI: Motor Voltage ⥵ ω MODFSR

Scope: Voltage(time) ⥵ Intensity(ω)

Tech has not changed since the 60’s

Digital Age: Analog = Outdated

Four knobs to manipulate display?!?

Setup time

Drift / Aging

No quantitative data

Units?

Not User Friendly

System Cost – Oscilloscope Required

Using only a fraction of functionality:

Large sample memory

Data capture

3+ Channels

Digital OSA Controller (DSC)

Numeric control over PZT voltage (DAC)

Sampled photo detector signal (ADC)

No oscilloscope required, lower cost

Computers are fast:

Real time DSP to clean up signal

Convert units on the fly for display

Modernize the user experience…

REV 0 - 2012.02.26

MODE AUTO

OFF 312V

EXP 63V

CONF 94%

FSR 1.5G

RUN - 5 Hz40 MHz / DIV

RUN/STOP

50µA / DIV

AUTO FSR

PEAK SNAP

CURSOR

AQUIRE

1. Replicate existing functionality

2. Provide additional value

Accuracy

Data capture

Usability

3. Reduce cost

Sounds good to me! But how?

USER INTERFACE MODULE (UIM) – USB to computer with software and/or hardware GUI

DATA CONTROL MODULE (DCM) – System controller; connects other modules, produces output, processes input.

INPUT PROCESSING MODULE (IPM) – Transimpedance amplifier for photodiode detector, 100+ MHz ADC & filter.

SFPI OUTPUT MODULE (SOM) – Low noise, high accuracy DAC converter, HV (500V) supply & amplifier.

CHASSIS – Hardware and enclosure, mains power supply. Study, compact package suitable for daily use in a lab environment.

We will cover a wide range of technologies…

HV DAC, RF Small Signal ADC

Embedded DSP, USB, GUI and FS Storage

Kevin Nicotera, Module Manager, UIM

Request data from DCM

Collect data from DCM

Display information to user

Consistent, easy to read

Intuitive controls

Don’t reinvent the wheel

Store data in CSV format

Embedded and PC based UI options

Embedded: w/Linux Kernel 2.6.31+

PC: Microsoft Windows 2000+

Both use USB interface to DCM

Use C++ for software development

Use cross-platform APIs to share common code

Two-Plot display

The “big” picture – gives context to main plot

The “little” details – high resolution main plot

REV 0 - 2012.02.26

MODE AUTO

OFF 312V

EXP 63V

CONF 94%

FSR 1.5G

RUN - 5 Hz40 MHz / DIV

RUN/STOP

50µA / DIV

AUTO FSR

PEAK SNAP

CURSOR

AQUIRE

Common C++ backend

SDL graphics engine

Leverage Visual Studio

.NET wrapper around common code base

Rapid application development with native

“look and feel”

Mouse-only features for ease of use

Easy to use, easy to develop

lack of mobility

<10” LCD screen to be built into chassis Strive for similar interface as Soft GUI Provide user same intuitive controls as

common bench equipment Move interaction closer to optics table Embedded Single Board PC (SBPC): Raspberry Pi for cheap SBPC Cheap, but feature rich Increased risk due to using ARM based

processor with Linux system

Intel Atom SBPC easy development Pros:

x86 = reduced development time

All low-level system drivers stable

Faster, dual core, 10x more memory

Cons

Space – 4x larger

Power – 10x

Price – about 2x more expensive

Jason Hartman, Module Manager, DCM

Digital implementation of analog controller

Interface with UIM: Change state/

configuration

Provide requested data Interface with SFPI: Determine SOM output

Capture IPM data stream

Provide clock timing Detect error conditions

Parallel FSM Model:

1. UIM process – USB Driven

Handles user input

Display requests

2. Data collection process – High Speed

Data harvesting

Digital equivalent of analog ramp generator

Control voltage to SOM

Accept specifications for data collection

Real-time DSP configuration:

Sample rate/averaging algorithm

When to start retaining data

Number of samples taken

USB Driven – on demand

Fast - Full system clock

SOM output (192 kHz)

IPM input (100+ MHz)

Processing (500+ MHz)

DSP – Basic Example:

Variable window size

averaging

Max Scale 20k:1

Min Scale 1:1

Xilinx Spartan 6 FPGA on Digilent Atlys

Fast - Up to 500 MHz system clock

128 MB DDR2 DRAM

Versatile - 56 DSP slices

VHDL for time-critical I/O

IPM DSP DDR2

Picoblaze for UIMPROC FSM

DDR2 PicoBlaze USB2

Digilent USB stack for UIM interface

Elton Williams, Module Manager, IPM

Input from SFPI photodiode detector:

50Ω BNC-F connector

Low level current-signal

Amplification:

Max gain – 20µA full-scale input

Min gain – 20mA full-scale input

ADC:

16 bit sample width

Oversample input signal, 50-100+MSPS

Wide bandwidth, need DC accuracy

Cookbook transimpedance amplifier

ASIC programmable gain ADC

conditioner/LPF

High speed ADC

Transimpedance amplifier based on

high-speed opamp

Linear Technology LTC2205-2209

DC919A-C demo board

DC-70MHz input bandwidth at 65MSPS

Spurious-Free Dynamic Range (SFDR)

>92dB

50Ω terminated

16 bit parallel bus

Meets DCM timing req.

Mary Hatfield, Module Manager, SOM

Output to piezoelectric motor in SFPI

500V full scale voltage

Low frequency < 100 Hz ramp

High accuracy, linearity

Resolution at least 24 bits for 1khz/LSB

Accept digital input from DCM

DAC - Produce an analog voltage proportional to the binary coded input

Low frequency < 100 Hz ramp

Output to piezoelectric motor in SFPI

500V full scale voltage

High linearity, low noise

Support for future enhancements

High resolution: 24 bit = sub 1kHz steps

Monitor HV Output

High Voltage system MUST Fail-Closed

Serial Input from DCM DAC COTS High Voltage amplifier Monitoring and active safety measures

TI DSD1791 R2R

DAC

VIP PiezoMaster

VP7206

Custom PCB

Jacob Dilles, Project Manger

Mount Points for

Modules:

UIM (&Screen/buttons)

DCM (Demo board)

IPM (custom PCB)

SOM (custom PCB)

Provide DC power

UIM – 12V 120W

DCM – 5V 20W

IPM – +5V 1.5A

SOM - +12, +5, 48V

Fabricated Enclosure

Rugged

Bench Equipment “Feel”

COTS 48V 500W SMPS

Linear regulators for

analog small signal

COTS 48V DC/DC for

all other needs

Module MM MA MT

INPUT PROCESSING MODULE Elton Mary Kevin

SUPPLY/OUTPUT MODULE Mary Jacob Jacob

DATA CONTROL MODULE Jason Elton Mary

USER INTERFACE MODULE – Hardware Kevin Jason Elton

USER INTERFACE MODULE – Software Jacob Kevin Jason

CHASSIES Jacob Team Team

MM = Module Manager, MA = Module Assistant, MT = Module Tester

An optical spectrum analyzer, such as the DSC,

must operate a piezoelectric motor to change

the resonant frequency of the attached SFPI

cavity.

To operate, this motor requires minimal

current, but a high voltage, on the order of 500

VDC.

Meeting this requirement presents a serious

and legitimate safety and liability concern

1. The DC-DC conversion of a low supply rail

voltage (12 or 24V) to a high output voltage

(maximum external 500VDC)

2. Amplification of a low frequency (<100hz),

low level (<2V) analog signal to a

proportional high-voltage analog signal

3. Testing of the supply (1) and amplification (2)

1. Final design review and assembly of HV components by an experienced technician, under advisement by knowledgeable faculty and professional engineers

2. Comprehensive testing of HV components will be performed off of university grounds to ensure all safety requirements have been met

3. All HV components will be potted (sealed in an insulating epoxy) to prevent modification.

4. Student team members will only operate the HV assembly under faculty supervision

5. ECE faculty will conduct regular safety reviews after HV assembly integration

Supplemental SOM requirements: 1. Chassis grounding tied to the “0” V rail and the third

prong of the AC voltage cord, in accordance with National Electrical Code and IEEE recommendations.

2. Fast SCR crowbar of output terminal, with supplemental electromechanical (relay) disconnect of HV supply power and output if an error condition is detected

3. Isolated HV-BNC connector for the HV connection, including a mechanical cable-disconnect interlock switch that prevents power up with no cable attached

4. Current leakage monitoring, crowbarring the HV output if leakage current between the HV output and chassis ground is detected (GFI)

5. Output current monitoring, with output crowbar if total HV current draw exceeds a preset limit

JACOB DILLES, PM

JASON HARTMAN

MARY HATFIELD

KEVIN NICOTERA

ELTON WILLIAMS

DR. QILIANG LI, ECE SUPERVISOR DR. MINGZHEN TIAN, PHYSICS SUPERVISOR DR. PIOTR PACHOWICZ, COURSE COORDINATOR DR. WILLIAM SUTTON, ASSOCIATE CHAIR

TEAM SPECTRUM

THANK YOU!