George Mason University ECE 448 – FPGA and ASIC Design with VHDL

Lecture 18

FPGA Boards& FPGA-based Supercomputers

High Level Language (HLL)Design Methodology

2 ECE 448 – FPGA and ASIC Design with VHDL

ResourcesPCI

http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect

PCI-X

http://en.wikipedia.org/wiki/PCI-X

Reconfigurable SupercomputingT. El-Ghazawi, K. Gaj, D. Buell, D. PointerTutorial at the Supercomputing 2005 conferencehttp://hpcl.seas.gwu.edu/openfpga/tutorial_html/index.html

3 ECE 448 – FPGA and ASIC Design with VHDL

FPGA Device Capacity Trends

Year1985

Xil

inx

Dev

ice

Com

ple

xity

XC200050 MHz1K gates

XC4000100 MHz

250K gates

Virtex200 MHz1M gates

Virtex-II 450 MHz8M gates

Spartan80 MHz

40K gates

Spartan-II200 MHz

200K gates

Spartan-3326 MHz5M gates

19911987

XC300085 MHz

7.5K gates

Virtex-E240 MHz4M gates

XC520050 MHz

23K gates

1995 1998 1999 2000 2002 2003

Virtex-II Pro450 MHz8M gates*

2004 2006

Virtex-4500 MHz

16M gates*

Virtex-5550 MHz

24M gates*

Source: http://class.ece.iastate.edu/cpre583/lectures/Lect-01.ppt

George Mason University ECE 448 – FPGA and ASIC Design with VHDL

FPGA Boards

5 ECE 448 – FPGA and ASIC Design with VHDL

General Architecture of an FPGA-Based Board

BU

S

ProcessingElement(PE#0)

ProcessingElement(PE#1)

ProcessingElement(PE#N-1)

COMMON MEMORY / INTERCONNECT NETWORK

LOCALMEMORY

LOCALMEMORY

LOCALMEMORY

CLK

BUS INTERFACE CONTROLLER

I/O CARD

6 ECE 448 – FPGA and ASIC Design with VHDL

Reconfigurable Computing Boards

• Boards may have one or several interconnected FPGA chips

• Support different bus standards, e.g. PCI, PCI-X, USB, etc.

• May have direct real-time data I/O through a daughter board

• Boards may have local onboard memory (OBM) to handle large data while avoiding the system bus (e.g. PCI) bottleneck

7 ECE 448 – FPGA and ASIC Design with VHDL

• Many boards per node can be supported

• Host program (e.g. C) to interface user (and P) with board via a board API

• Driver API functions may include functionalities such as Reset, Open, Close, Set Clocks, DMA, Read, Write, Download Configurations, Interrupt, Readback

Reconfigurable Computing Boards

8 ECE 448 – FPGA and ASIC Design with VHDL

Common Interface - PCI

PCI = Peripheral Component Interconnect

32-bit bus 64-bit bus

9 ECE 448 – FPGA and ASIC Design with VHDL

PCI - Conventional hardware specifications

• 32-bit or 64-bit bus width • 33.33 MHz clock with synchronous transfers • peak transfer rate of 133 MB per second for 32-

bit bus width (33.33 MHz × 32 bits × (1 byte ÷ 8 bits) = 133 MB/s)

• peak transfer rate of 266MB/s for 64-bit bus width • 32-bit address space (4 gigabytes) • 32-bit port space • 5-volt signaling

10 ECE 448 – FPGA and ASIC Design with VHDL

PCI-X (PCI eXtended)

• PCI-X doubles the width to 64-bit, revises the protocol, and increases the maximum signaling frequency to 133 MHz (peak transfer rate of 1014 MB/s)

• PCI-X 2.0 permits a 266 MHz rate (peak transfer rate of 2035 MB/s) and also 533 MHz rate, adds a 16-bit bus variant and allows for 1.5 volt signaling

11 ECE 448 – FPGA and ASIC Design with VHDL

Some Reconfigurable Boards Vendors

• ANNAPOLIS MICRO SYSTEMS, INC. (www.annapmicro.com) • University of Southern California -USC/ISI

(http://www.east.isi.edu). • AMONTEC (www.amontec.com/chameleon.shtml) • XESS Corporation (www.xess.com) • CELOXICA (www.celoxica.com) • CESYS (www.cesys.com) • TRAQUAIR (www.traquair.com) • SILICON SOFTWARE: (www.silicon-software.com) • COMPAQ: (www.research.compaq.com/SRC/pamette/) • ALPHA DATA: (www.alpha-data.com) • Associated Professional Systems: (www.associatedpro.com) • NALLATECH: (www.nallatech.com)

12 ECE 448 – FPGA and ASIC Design with VHDL

WILDSTAR™ II Pro

Reproduced and displayed with permission

13 ECE 448 – FPGA and ASIC Design with VHDL

WILDSTAR™ II Pro

Reproduced and displayed with permission

George Mason University ECE 448 – FPGA and ASIC Design with VHDL

Reconfigurable Supercomputers

15 ECE 448 – FPGA and ASIC Design with VHDL

Scalable Reconfigurable Systems

• Large numbers of reconfigurable processors and microprocessors

• Everything can be configured• Functional units• Interconnects• Interfaces

• High-level of scalability• Suitable for a wide range of applications • Everything can be reconfigured over and over at run time

(Run-Time Reconfiguration) to suite underlying applications• Can be easily programmed by application scientists, at least

in the same way of programming conventional parallel computers

16 ECE 448 – FPGA and ASIC Design with VHDL

Interface

P memory

P memory

. . .

P P . . .

I/O Interface

FPGA memory

FPGA memory

. . .

FPGA FPGA . . .

I/O

Microprocessor system Reconfigurable system

Early Reconfigurable Architecture

17 ECE 448 – FPGA and ASIC Design with VHDL

Current Reconfigurable Architecture

. . .

Shared Memory and or NIC

FPGA memory

FPGA

P memory

P

FPGA memory

FPGA

P memory

P

18 ECE 448 – FPGA and ASIC Design with VHDL

Possible Classes of Reconfigurable Supercomputers

μP Board RP Board

…μP 1 μP N …RP 1 RP N

Joint μP/RP Board

…μP 1 μP N …RP 1 RP N

Tighter Integration

Independent BoardDesign

Joint BoardDesign

19 ECE 448 – FPGA and ASIC Design with VHDL

Possible Classes of Reconfigurable Supercomputers – cont.

Tighter Integration

μP inside of RP

Design

RP inside of μP

Design

Joint μP/RP Board

μP 1 …RP 1

μP N

RP N

Joint μP/RP Board

RP 1 …μP 1

RP N

μP N

20 ECE 448 – FPGA and ASIC Design with VHDL

FPGA based supercomputers

Machine Released

SRC 6 fromSRC Computers

Cray XD1 fromfrom Cray

SGI Altix fromSGI

SRC 7 fromSRC Computers, Inc,

2002

2005

2005

2006

21 ECE 448 – FPGA and ASIC Design with VHDL

How to choose the system that best suits your needs?

Typical users’ criteria:

1. Clock speed

2. Amount of memory

3. Cost of Ownership

22 ECE 448 – FPGA and ASIC Design with VHDL

How to choose the system that best suits your needs?

Recommended users’ criteria:1. Tools

- right level of abstraction- ease of development & verification- progress & backward compatibility

2. Libraries- basic operations- examples of full applications

3. Technical support

23 ECE 448 – FPGA and ASIC Design with VHDL

How to choose the system that best suits your needs?

Recommended users’ criteria (cont.):

4. Data Bandwidth

Reconfigurable Processor

System

Psystem

externalI/O devices

24 ECE 448 – FPGA and ASIC Design with VHDL

How to choose the system that best suits your needs?

Recommended users’ criteria (cont.):

5. Scalability

- variable power and price - efficient communication among the modules

25 ECE 448 – FPGA and ASIC Design with VHDL

Recommended users’ criteria (cont.):

6. Transfer of control overhead

Theoreticalbehavior

Actualbehavior

P FPGA

time

P FPGA

Control transferoverhead

George Mason University ECE 448 – FPGA and ASIC Design with VHDL

High Level Language (HLL)Design Methodology

Handel C

27 ECE 448 – FPGA and ASIC Design with VHDL

Behavioral Synthesis

Algorithm

I/O Behavior

Target Library

Behavioral Synthesis

RTL Design

LogicSynthesis

Gate level Netlist

Classic RTL Design Flow

28 ECE 448 – FPGA and ASIC Design with VHDL

Need for High-Level Design

• Higher level of abstraction• Modeling complex designs• Reduce design efforts• Fast turnaround time• Technology independence• Ease of HW/SW partitioning

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Advantages of Behavioral Synthesis

• Easy to model higher level of complexities• Smaller in size source compared to RTL code• Generates RTL much faster than manual method• Multi-cycle functionality• Loops• Memory Access

30 ECE 448 – FPGA and ASIC Design with VHDL

High-Level Languages

• C/C++-Based • Handel C – Celoxica Ltd., UK

• Impulse C – Impulse Accelerated Technologies

• Catapult C – Impulse Accelerated Technologies

• System C – The Open SystemC Initiative

• Java-based• Forge – Xilinx

• JHDL – Brigham Young University

31 ECE 448 – FPGA and ASIC Design with VHDL

Other High-Level Design Flows

• Matlab-based• System Generator for DSP – Xilinx

• AccelChip DSP Synthesis – AccelChip

• GUI Data-Flow based • Corefire – Annapolis Microsystems

• RC Toolbox – DSPlogic

32 ECE 448 – FPGA and ASIC Design with VHDL

Handel C

Design Flow

33 ECE 448 – FPGA and ASIC Design with VHDL

Design Flow

Executable Specification

Handel-C

Synthesis

Place & Route

VHDL

EDIFEDIF

34 ECE 448 – FPGA and ASIC Design with VHDL

Handel-C/ANSI-C Comparisons

Preprocessorsi.e. #define

Structures

ANSI-C Constructsfor, while, if, switch

Functions

Arrays

Pointers

Arithmetic operators

Bitwise logical operators

Logical operators

ANSI-C Standard Library

Side Effectsi.e. X = Y++

Recursion

Floating Point

Handel-C Standard Library

Parallelism

Arbitrary width variables

RAM, ROMSignals

Channels

Interfaces

Enhanced bit manipulation

ANSI-C HANDEL-C

35 ECE 448 – FPGA and ASIC Design with VHDL

Variables

• Only one fundamental type for variables: intint 5 x;unsigned int 13 y;

• Default typeschar 8 bitsshort 16 bitslong 32 bits

36 ECE 448 – FPGA and ASIC Design with VHDL

Type Summary

Type Width

char 8 bits

unsigned char 8 bits

short 16 bits

unsigned short 16 bits

long 32 bits

unsigned long 32 bits

int Compiler

unsigned int Compiler

int n n bits

unsigned int n n bits

unsigned n n bits

37 ECE 448 – FPGA and ASIC Design with VHDL

Arrays

• Same way as in ANSI-Cint 6 x[7];

7 registers of 6 bits wide

unsigned int 6 x [4] [5] [6]; 120 registers of 6 bits wide

• Index must be a compile time constant. If random access is required, consider using RAM or ROM

38 ECE 448 – FPGA and ASIC Design with VHDL

Internal RAMs and ROMs

• Using ram and rom keywordsram int 6 a [43];

a RAM consisting of 43 entries of 6 bits wide

rom int 16 b [4];a ROM consisting of 4 entries of 16 bits wide

• RAMs and ROMs are accessed the same way that arrays are accessed in ANSI-C

• Index need not be a compile time constant

39 ECE 448 – FPGA and ASIC Design with VHDL

Restrictions on RAMs and ROMs

• RAMs and ROMs are restricted to performing operations sequentially. Only one element may be addressed in any given clock cycleram unsigned int 8 x [4];x [1] = x [3] + 1; illegalif (x [0] == 0)

x [1] = 1; illegal

40 ECE 448 – FPGA and ASIC Design with VHDL

Multi-port RAMs

static mpram Fred{

ram <unsigned 8> ReadWrite[256]; (read/write port)

rom <unsigned 8> Read[256];(read only port)

}Now we can read and write in a given clock cycle

41 ECE 448 – FPGA and ASIC Design with VHDL

Dual Port Memory

42 ECE 448 – FPGA and ASIC Design with VHDL

Handel-C Language (1)

• A subset of ANSI-C

• Sequential software style with a “par” construct to implement parallelism

• A channel “chan” statement allows for communication and synchronization between parallel branches

• Level of design abstraction is above RTL but below behavioral

43 ECE 448 – FPGA and ASIC Design with VHDL

Handel-C Language (2)

• Each assignment and delay statement take one clock cycle

• Automatic generation of the state machine from an algorithmic description of the circuit in terms of parallel and sequential blocks

• Automatic scheduling of parallel and sequential blocks, that is the code following a group is scheduled only after that whole group has completed

44 ECE 448 – FPGA and ASIC Design with VHDL

Parallelism

Parallel blocks

Statement

45 ECE 448 – FPGA and ASIC Design with VHDL

Par construct - Examples

46 ECE 448 – FPGA and ASIC Design with VHDL

Par constructs - timing

47 ECE 448 – FPGA and ASIC Design with VHDL

Par construct – shift register

48 ECE 448 – FPGA and ASIC Design with VHDL

Handel C vs. C - functions

Functions may not be called recursively, since all logic must beexpanded at compile-time to generate hardware

You can only call functions in expression statements. These statements must not contain any other calls or assignments.

Variable length parameter lists are not supported.Old-style ANSI-C function declarations (where the type of the parameters is not specified) are not supported.

main() functions take no arguments and return no values.

Each main() function is associated with a clock. If you have more than one main() function in the same source file,they must all use the same clock.

49 ECE 448 – FPGA and ASIC Design with VHDL

Handel-C Overview

• High-level language based on ISO/ANSI-C for the implementation of algorithms in hardware

• Allows software engineers to design hardware without retraining• Clean extensions for hardware design including flexible data widths,

parallelism and communications• Based on Communicating Sequential Process model

• Independent parallel processes• “par” construct to specify parallel computation blocks within a

process• Well defined timing model

• Each statement takes a single clock cycle• Includes extended operators for bit manipulation, and high-level

mathematical macros (including floating point)