Georgia Tech Seminar 1 Keith A. Bowman Circuit Research Lab, Intel [email protected] April 18, 2006 Keith A. Bowman Circuit Research Lab, Intel

Georgia Tech SeminarGeorgia Tech SeminarGeorgia Tech SeminarGeorgia Tech Seminar 11

Keith A. BowmanCircuit Research Lab, Intel

[email protected]

April 18, 2006

Keith A. BowmanCircuit Research Lab, Intel

[email protected]

April 18, 2006

Impact of Variation Sources on Circuit Performance and Power & Design Techniques for Variation

Tolerance

Impact of Variation Sources on Circuit Performance and Power & Design Techniques for Variation

Tolerance


OutlineOutline

• Technology Trends

• Sources of Variability

• Impact of Variations on Circuit Design

• Variation Tolerance & Control

• Variation Compensation Techniques

• Technology Trends

• Sources of Variability

• Impact of Variations on Circuit Design

• Variation Tolerance & Control

• Variation Compensation Techniques


Technology OutlookTechnology Outlook

Medium High Very HighMedium High Very HighVariabilityVariability

Energy scaling will slow downEnergy scaling will slow down>0.5>0.5>0.5>0.5>0.35>0.35Energy/Logic Op Energy/Logic Op scalingscaling

0.5 to 1 layer per generation0.5 to 1 layer per generation88--9977--8866--77Metal LayersMetal Layers

1111111111111111RC DelayRC Delay

Reduce slowly towards 2Reduce slowly towards 2--2.52.5<3<3~3~3ILD (K)ILD (K)

Low Probability High ProbabilitLow Probability High ProbabilityyAlternate, 3G etcAlternate, 3G etc

128

1111

20162016

High Probability Low ProbabilitHigh Probability Low ProbabilityyBulk Planar CMOSBulk Planar CMOS

Delay scaling will slow downDelay scaling will slow down>0.7>0.7~0.7~0.70.70.7Delay = CV/I Delay = CV/I scalingscaling

256643216842Integration Integration Capacity (BT)Capacity (BT)

88161622223232454565659090Technology Node Technology Node (nm)(nm)

20182018201420142012201220102010200820082006200620042004High Volume High Volume ManufacturingManufacturing

Medium High Very HighMedium High Very HighVariabilityVariability

Energy scaling will slow downEnergy scaling will slow down>0.5>0.5>0.5>0.5>0.35>0.35Energy/Logic Op Energy/Logic Op scalingscaling

0.5 to 1 layer per generation0.5 to 1 layer per generation88--9977--8866--77Metal LayersMetal Layers

1111111111111111RC DelayRC Delay

Reduce slowly towards 2Reduce slowly towards 2--2.52.5<3<3~3~3ILD (K)ILD (K)

Low Probability High ProbabilitLow Probability High ProbabilityyAlternate, 3G etcAlternate, 3G etc

128

1111

20162016

High Probability Low ProbabilitHigh Probability Low ProbabilityyBulk Planar CMOSBulk Planar CMOS

Delay scaling will slow downDelay scaling will slow down>0.7>0.7~0.7~0.70.70.7Delay = CV/I Delay = CV/I scalingscaling

256643216842Integration Integration Capacity (BT)Capacity (BT)

88161622223232454565659090Technology Node Technology Node (nm)(nm)

20182018201420142012201220102010200820082006200620042004High Volume High Volume ManufacturingManufacturing


Technology TrendsTechnology Trends

1) More transistors per chip

2) Deliver higher performance systems

3) Power is the limiter

4) Larger delay and power variability

1) More transistors per chip

2) Deliver higher performance systems

3) Power is the limiter

4) Larger delay and power variability


Sources of VariabilitySources of Variability

ProcessProcess Circuit OperationCircuit Operation Simulation ToolsSimulation Tools

Channel LengthChannel Length TemperatureTemperature Timing AnalysisTiming Analysis

Channel WidthChannel Width Supply VoltageSupply Voltage RC ExtractionRC Extraction

Threshold VoltageThreshold Voltage Aging (NBTI)Aging (NBTI) Cell ModelingCell Modeling

I-V CurvesI-V Curves

Overlap CapacitanceOverlap Capacitance Cross-Coupling Cross-Coupling CapacitanceCapacitance

Circuit SimulationsCircuit Simulations

InterconnectInterconnect Multiple Input Multiple Input SwitchingSwitching

Process FilesProcess Files

Transistor ModelsTransistor Models


Scale of VariationsScale of Variations

Within-Die (WID) Within-Die (WID) VariationsVariations

SystematicSystematic

Die-to-Die (D2D) Die-to-Die (D2D) VariationsVariations

Feature ScaleFeature ScaleDie ScaleDie Scale

RandomRandom

Wafer ScaleWafer Scale


Sub-Wavelength LithographySub-Wavelength Lithography

0.01

0.1

1

1980 1990 2000 2010 2020

micron

10

100

1000

nm

193nm193nm248nm248nm

365nm365nmLithographyLithographyWavelengthWavelength

65nm65nm

90nm90nm

130nm130nm

GenerationGeneration

GapGap

45nm45nm

32nm32nm

13nm 13nm EUVEUV

180nm180nm

• WID became significant at 250nm generation Gate Length < Litho Wavelength (=248nm)

• WID became significant at 250nm generation Gate Length < Litho Wavelength (=248nm)


Die-to-Die VariationDie-to-Die Variation Examples: Processing temperatures, equipment Examples: Processing temperatures, equipment

properties, polishing, wafer placement, resist properties, polishing, wafer placement, resist thickness thickness

Systematic Within-Die VariationSystematic Within-Die Variation Long range WID variation (e.g., mm range) Long range WID variation (e.g., mm range)

Variation depends on correlation distanceVariation depends on correlation distance

Variation profile varies randomlyVariation profile varies randomly

Examples: Lens aberrations, mid-range flare, stepper Examples: Lens aberrations, mid-range flare, stepper non-uniformities, scanner overlay control, multiple non-uniformities, scanner overlay control, multiple dies per reticle, wafer topographydies per reticle, wafer topography

Random Within-Die VariationRandom Within-Die Variation Short range WID variation Short range WID variation

Fluctuates independent of device locationFluctuates independent of device location

Examples: Patterning limitations, short-range flare, Examples: Patterning limitations, short-range flare, line edge roughnessline edge roughness Source: Nagib Hakim

Source: Steve Duvall

Gate Length VariationGate Length Variation


Systematic-WID VariationSystematic-WID Variation

Source: H. Masuda, et al., IEEE CICC 2005.

• From circuit design perspective, systematic WID behaves as a correlated random-WID variation

• From circuit design perspective, systematic WID behaves as a correlated random-WID variation


Gate Length Variation TrendsGate Length Variation Trends

250 180 130 90 65 45

Total D2D & WID

Total WID

Systematic WID

Random WID

250 180 130 90 65 45

Total D2D & WID

Total WID

Systematic WID

Random WID

=248nm =193nm

250 180 130 90 65 45

Technology Generation (nm)

Rel

ativ

e C

D V

aria

tio

n

• Total CD control ~ fixed % of nominal gate length• Random variations increase with scaling

• Total CD control ~ fixed % of nominal gate length• Random variations increase with scaling


250 180 130 90 65 45

Technology Generation (nm)

Co

rrel

atio

n L

eng

th Correlation Length

Ideal Scaling

Systematic-WID Correlation LengthSystematic-WID Correlation Length

=248nm =193nm


Poly/Diffusion Rounding and MisalignmentPoly/Diffusion Rounding and MisalignmentPoly/Diffusion Rounding and MisalignmentPoly/Diffusion Rounding and Misalignment

Channel Width VariationChannel Width Variation

Xtr 1

Xtr 2

Poly

Diffusion

Source: S. Tyagi


200

600

1000

0 10 20 30 401/area (a.u.)

VT

(/

)2(a

.u.)

200

600

1000

0 10 20 30 401/area (a.u.)

VT

(/

)2(a

.u.)

Deviates from 1/area dependency

Random dopant fluctuation (RDF) 1/area

Oxide charge fluctuation (OCF) 1/area

Line edge roughness (LER)1/L?1/W?

Other ? ??

Threshold Voltage VariationThreshold Voltage Variation


Random Dopant FluctuationRandom Dopant Fluctuation

10

100

1000

10000

1000 500 250 130 65 32

Technology Node (nm)

Me

an

Nu

mb

er

of

Do

pa

nt

Ato

ms

10

100

1000

10000

1000 500 250 130 65 32

Technology Node (nm)

Me

an

Nu

mb

er

of

Do

pa

nt

Ato

ms

Source: X. Tang


Interconnect VariationsInterconnect Variations• Depth of Focus Variation

Optical Proximity Correction (OPC) resizes interconnect widths to guarantee printability

Depends on neighboring interconnects

• Chemical Mechanical Polishing (CMP) Depends on local area metal density Metal density requirements significantly reduce variation

• Etching Variation expected to be smaller than depth of focus & CMP

variation

• Depth of Focus Variation Optical Proximity Correction (OPC) resizes interconnect widths

to guarantee printability Depends on neighboring interconnects

• Chemical Mechanical Polishing (CMP) Depends on local area metal density Metal density requirements significantly reduce variation

• Etching Variation expected to be smaller than depth of focus & CMP

variation


Impact of OPC on Isolated LinesImpact of OPC on Isolated Lines

CD

FocusFocus Window

150nm

100nm

Max CD

Min CD

Bossung Plot Example (Isolated Drawn Lines)Bossung Plot Example (Isolated Drawn Lines)

Chip Topography

Focus Variations

Light Source

FP2FN2


Temperature & Supply VoltageTemperature & Supply Voltage

Junction TemperatureJunction Temperature Supply Voltage (IR Drop)Supply Voltage (IR Drop)

Deterministic Variation Die MapsDeterministic Variation Die Maps

Source: G. Yuan


Su

pp

ly V

olt

age

(V)

Vmax: reliability & power

Vmin: frequency

Time (usec)

Su

pp

ly V

olt

age

(V)

Vmax: reliability & power

Vmin: frequency

Time (usec)

Supply Voltage VariationsSupply Voltage Variations

• Chip activity change

• Current delivery RLC

• Dynamic: ns to 10-100us

• Chip activity change

• Current delivery RLC

• Dynamic: ns to 10-100us


Source: M. Agostinelli, et al., IEEE Intl. Reliability Physics Symp., 2005.

• PMOS VT degrades from bias & temperature stress• Impact of NBTI depends on gate area

• PMOS VT degrades from bias & temperature stress• Impact of NBTI depends on gate area

0

1

2

3

4

5

6

0.001 0.01 0.1 1

Small Device Area(=WxL) in m2

%Id

sat a

t Vcc

=1.

0V

Aging (NBTI)Aging (NBTI)Negative Bias Temperature Instability (NBTI)Negative Bias Temperature Instability (NBTI)


Cost of VariationsCost of Variations

Overestimating VariationsOverestimating Variations

• Increases design timeIncreases design time

• Larger die sizeLarger die size

• Rejection of otherwise good design Rejection of otherwise good design optionsoptions

• Missed market windowsMissed market windows

Increases design effortIncreases design effort

Underestimating VariationsUnderestimating Variations

• Functional yield lossFunctional yield loss

• Performance reductionPerformance reduction

• Increases silicon debug timeIncreases silicon debug time

Increases manufacturing effortIncreases manufacturing effort


Impact of WID VariationsImpact of WID Variations

• As Ncp increases, WID distribution mean increases and variance decreases

• As Ncp increases, WID distribution mean increases and variance decreases

0

5

10

15

20

25

0.8 0.9 1.0 1.1 1.2

Normalized Maximum Critical Path Delay

Pro

bab

ilit

y D

ensi

tyD2D

WID: Ncp=1

WID: Ncp=2

WID: Ncp=10

WID: Ncp=100

WID: Ncp=1000

WID: Ncp=10000

Ncp Ncp Number of Independent Critical Paths Number of Independent Critical Paths


Impact of WID & D2D VariationsImpact of WID & D2D Variations

0

20

40

60

80

100

0.7 0.8 0.9 1.0 1.1 1.2 1.3

Normalized FMAX

Cu

mu

lati

ve D

istr

ibu

tio

n (

%)

Model: Only WID Model: Only WID VariationsVariations

Model: Only D2D Model: Only D2D VariationsVariations

Model: D2D & WID Model: D2D & WID VariationsVariations

• WID variations primarily impact FMAX mean• D2D variations primarily impact FMAX variance

• WID variations primarily impact FMAX mean• D2D variations primarily impact FMAX variance

0

20

40

60

80

100

-4 -3 -2 -1 0 1 2 3 4

Measured DataModel: D2D & WIDModel: D2DModel: WID

Measured DataMeasured Data

Mean FMAX Mean FMAX ReductionReduction


0.0

0.2

0.4

0.6

0.8

1.0

1 10

Normalized Leakage

Cu

mu

lati

ve

Nominal @ tttt

WID

D2D

D2D & WID

WID DistributionWID Distribution

Nominal LeakageNominal Leakage

D2D DistributionD2D Distribution

D2D & WID DistributionD2D & WID Distribution

Impact of WID & D2D VariationsImpact of WID & D2D Variations

• WID variations impact leakage median• D2D variations impact leakage variance

• WID variations impact leakage median• D2D variations impact leakage variance


0

50

100

150

200

250

300

2.1 2.2 2.4 2.6 2.7 2.9 3.0

Bin Fmax (GHz)

Die

Co

un

t

0

1

2

3

4

Pri

ce

(n

orm

ali

zed

)

0.1

1

10

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1

Fmax (GHz)

Le

ak

ag

e (

A)

Power & Burn-In Limit

Power & Burn-In Limit

FMAX BinningFMAX BinningPerformance & PowerPerformance & PowerPerformance & PowerPerformance & Power

Variation Range

FMAX ~30%

Leakage ~5X

Variation Range

FMAX ~30%

Leakage ~5X


Deeper PipelinesDeeper Pipelines

386486

Pentium(R)

Pentium Pro(R)

Pentium(R) II

MPC750604+604

601, 603

21264S

2126421164A

2116421064A

21066

10

100

1,000

10,000

19

87

19

89

19

91

19

93

19

95

19

97

19

99

20

01

20

03

20

05

Mh

z

1

10

100

Ga

te D

ela

ys

/ Clo

ck

Intel

IBM Power PC

DEC

Gate delays/clock

Processor freq scales by 2X per

generation


Impact of Logic DepthImpact of Logic Depth

GATE

T

GATE

T

CP

T

TNT

N

TGATEGATECP

12

N12

N

Critical PathCritical PathCritical PathCritical Path

Systematic-WID Variations (Systematic-WID Variations (=1)=1)Systematic-WID Variations (Systematic-WID Variations (=1)=1)

Random-WID VariationsRandom-WID VariationsRandom-WID VariationsRandom-WID Variations

GATE

T

GATE

T

CP

T

TN1

NT

N

TGATEGATECP

• Random-WID variation averages across N stages• Random-WID variation averages across N stages


• Impact of random WID grows with deeper pipelining• Impact of systematic WID insensitive to pipelining

• Impact of random WID grows with deeper pipelining• Impact of systematic WID insensitive to pipelining

Impact on Logic DepthImpact on Logic Depth

0%

5%

10%

15%

20%

2 4 8 12 20

Logic depth

% m

ean

Fm

ax lo

ss Systematic + randomRandom only

Deeper pipelineDeeper pipeline


Impact of Steep Speedpath WallsImpact of Steep Speedpath Walls

0%

5%

10%

15%

20%

10 100 200 1000 10000

# critical paths

% m

ean

Fm

ax

loss

• Mean FMAX reduces as a logarithmic function of NCP• Mean FMAX reduces as a logarithmic function of NCP

32CP10 Nlog2Loss FMAX Mean %


Vss

Vdd

OpIp

Vss

Vdd

Op

No layout restrictionsNo layout restrictionsNo layout restrictionsNo layout restrictions

Freelance layout of the past…Freelance layout of the past…


Vss

Vdd

OpIp

Vss

Vdd

Op

Transistor orientation restrictionsTransistor orientation restrictions


Op

Vss

Vdd

Ip

Vss

Vdd

Op

Transistor width quantizationTransistor width quantization


Today’s unrestricted routing…Today’s unrestricted routing…


Future metal restrictionsFuture metal restrictions


Dense layout causes hot-spotsDense layout causes hot-spotsDense layout causes hot-spotsDense layout causes hot-spots

Today’s metric…Today’s metric…Maximize Transistor DensityMaximize Transistor DensityMaximize Transistor DensityMaximize Transistor Density


Balanced DesignBalanced DesignBalanced DesignBalanced Design

Tomorrow’s metric…Tomorrow’s metric…Optimizing Transistor & Power DensityOptimizing Transistor & Power DensityOptimizing Transistor & Power DensityOptimizing Transistor & Power Density


250

500

750

1000

1250

1500

1750

2000

0.9 1.1 1.3 1.5 1.7Vcc (V)

Fm

ax (

MH

z)

Body bias chipwith 450 mV FBB

NBB chip& body biaschip withZBBTj ~ 60°C

250

500

750

1000

1250

1500

1750

2000

0 5 10 15 20

Active power (W)F

max

(M

Hz)


Body biaschip withZBB

T j ~ 60°C250

500

750

1000

1250

1500

1750

2000

0 5 10 15 20

Active power (W)F

max

(M

Hz)


Body biaschip withZBB

T j ~ 60°C

Supply & Body Bias KnobsSupply & Body Bias Knobs


Adaptive SupplyAdaptive Supply

1

10

100

0.85 0.9 0.95 1 1.05 1.1

Frequency (normalized)

40°C

0.5 W/cm20

200

400

8

9

1010 W/cm2

1.05V 110°C : 0.030 0

Sta

nd

by

le

aka

ge

p

ow

er(n

orm

aliz

ed

)

To

tal

po

we

r(n

orm

aliz

ed

)

Sw

itc

he

d

ca

pac

ita

nc

e(n

orm

aliz

ed

)

1

10

100

0.85 0.9 0.95 1 1.05 1.1

Frequency (normalized)

40°C

0.5 W/cm20

200

400

8

9

1010 W/cm2

1.05V 110°C : 0.030 0

Sta

nd

by

le

aka

ge

p

ow

er(n

orm

aliz

ed

)

To

tal

po

we

r(n

orm

aliz

ed

)

Sw

itc

he

d

ca

pac

ita

nc

e(n

orm

aliz

ed

)

0%0%0%

20%40%60%80%

100%

0.9 0.95 1 1.05Frequency Bin

Die

co

un

t

0%0%0%

20%40%60%80%

100%


Die

co

un

t

0%

0%

74%

79%

20%

60%

100%


Die

co

un

t

0%

0%20%

60%

100%


Die

co

un

t

0%

0%

74%

79%

20%

60%

100%


Die

co

un

t

0%

0%20%

60%

100%


Die

co

un

t

Adaptive supply Adaptive body bias

0%

0%

74%

79%

20%

60%

100%


Die

co

un

t

0%

0%20%

60%

100%


Die

co

un

t

0%

0%

74%

79%

20%

60%

100%


Die

co

un

t

0%

0%20%

60%

100%


Die

co

un

t

Adaptive supply Adaptive body biasAdaptive supplyWithout adaptive supply


Adaptive Body Bias (ABB)Adaptive Body Bias (ABB)N

um

be

r o

f d

ies

Frequency

too slow

ftarget

too leaky

ftarget

ABB

FBB RBB

Nu

mb

er

of

die

s

Frequency

too slow

ftarget

too leaky

ftarget

ABB

FBB RBB


Static Adaptive BiasingStatic Adaptive Biasing

0.1

1

10

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1

Fmax (GHz)

Le

ak

ag

e (

A)

ABB: forward body bias

Adaptive supply: nothing

ABB: forward body bias

Adaptive supply: nothing

AB

B:

reve

rse

bo

dy

bia

s

Ad

apti

ve s

up

ply

: lo

wer

Vcc

AB

B:

reve

rse

bo

dy

bia

s

Ad

apti

ve s

up

ply

: lo

wer

Vcc

Power limit: 110oCPower limit: 110oC

Reduce Impact of D2D VariationsReduce Impact of D2D VariationsReduce Impact of D2D VariationsReduce Impact of D2D Variations


0%

0%

74%

79%

20%

60%

100%


Die

co

un

t

0%

0%20%

60%

100%


Die

co

un

t

0%

0%

74%

79%

20%

60%

100%


Die

co

un

t

0%

0%20%

60%

100%


Die

co

un

tAdaptive supply Adaptive body bias

0%

0%

79%

71%

20%

60%

100%


Die

co

un

t

0%

0%20%

60%

100%


Die

co

un

t

0%

0%

79%

71%

20%

60%

100%


Die

co

un

t

0%

0%20%

60%

100%


Die

co

un

t

Adaptive body bias Adaptive supply + body bias

-0.4

-0.2

0

0.2

0.4

-0.4

-0.2 0

0.2

0.4

NMOS body bias (V)

PM

OS

bo

dy

bia

s (

V)

P FBBN RBB

P RBBN RBB

P FBBN FBB

P RBBN FBB

Adaptive VBS

-0.4

-0.2 0

0.2

0.4

NMOS body bias (V)

P FBBN RBB

P RBBN RBB

P FBBN FBB

P RBBN FBB

Adaptive VDD+VBS

-0.4

-0.2 0

0.2

0.4

NMOS body bias (V)

P FBBN RBB

P RBBN RBB

P FBBN FBB

P RBBN FBB

Adaptive VDD+VBS

PM

OS

bo

dy

bia

s (

V)

-0.4

-0.2

0

0.2

0.4

…2% 25%…2% 25%

Effectiveness of Adaptive BiasingEffectiveness of Adaptive Biasing


Effectiveness of Adaptive BiasingEffectiveness of Adaptive Biasing• Slower Parts (Lower Power)

Leakage is a small percentage of total power Trade-off leakage increase for performance gain More effective to apply a forward body bias (FBB)

• Faster Parts (Higher Power) Active and leakage contribute significantly to total power Vcc reduction lowers both active and leakage power More effective to reduce supply voltage

• Slower Parts (Lower Power) Leakage is a small percentage of total power Trade-off leakage increase for performance gain More effective to apply a forward body bias (FBB)

• Faster Parts (Higher Power) Active and leakage contribute significantly to total power Vcc reduction lowers both active and leakage power More effective to reduce supply voltage


PLLPLLPLLPLL

Clock distribution network

WID ABB ConceptWID ABB ConceptWID ABB ConceptWID ABB Concept

0%

20%

40%

60%

80%

0.85 0.90 0.95 1.00 1.05

Bin Fmax (normalized)D

ie C

ou

nt

Static ABB for WID VariationsStatic ABB for WID Variations

WID ABB EffectivenessWID ABB EffectivenessWID ABB EffectivenessWID ABB Effectiveness150nm technology testchip

Adaptive supply + ABB

Adaptive supply + ABB

Ad

apti

ve

sup

ply

+

WID

AB

B

Ad

apti

ve

sup

ply

+

WID

AB

B

200% more chips in highest bin200% more chips in highest bin

• No body bias for clock• Needs triple-well process

• No body bias for clock• Needs triple-well process

Body bias 3Body bias 3

Body bias 2Body bias 2

Bo

dy

bia

s 1

Bo

dy

bia

s 1


SummarySummary• Technology trends are expected to amplify

circuit performance & power variability

• As technology scales, number of variation sources are increasing

• WID variations impact FMAX mean & leakage median

• D2D variations impact FMAX & leakage variances

• Adaptive techniques enable opportunity to mitigate impact of D2D & WID variations

• Technology trends are expected to amplify circuit performance & power variability

• As technology scales, number of variation sources are increasing

• WID variations impact FMAX mean & leakage median

• D2D variations impact FMAX & leakage variances

• Adaptive techniques enable opportunity to mitigate impact of D2D & WID variations

Documents

Georgia Tech Seminar 1 Keith A. Bowman Circuit Research Lab, Intel [email protected] April 18, 2006 Keith A. Bowman Circuit Research Lab, Intel