Germanium and compound semiconductor manufacturing for advanced CMOS

A. Dimoulas

MBE Laboratory, NCSR DEMOKRITOS, Athens Greece; dimoulas@ims.demokritos.gr

Keywords: High mobility CMOS, Germanium, InGaAs

AbstractThe present work presents a review of the progress in

all parts of high mobility (Ge and III-V) advancedCMOS, from the engineered substrates and co-integration schemes, to the channel device structure thegate dielectric and the source and drain contacts. Theaim is to identify the main challenges and the prospectivesolutions which will allow the manufacturing in a Si-compatible flow for volume production.

INTRODUCTION

The world is rapidly moving into the mobile informationage were mobile internet devices (MID) like tablets andsmartphones are at the center of attention for consumers,integrated device manufacturers and technology developers.For MIDs and other multimedia applications, control ofpower consumption at an acceptable level without losingspeed is an important requirement. To fulfill thisrequirement, transistors are made to operate at low powersupply voltage, which however leads to performancedegradation. Performance boosters such as strained siliconhave been extensively used until now, but they are alreadyout of steam so that new solutions are urgently needed.Germanium and III-V compound semiconductors come at arescue, offering high carrier mobility for the replacement ofsilicon in the transistor channel to manufacture the nextgeneration advanced CMOS. At present, there is no clearmaterial winner, however a dual channel solution is favoredin which p FETs comprise Ge (SiGe) channel while n FETsrequire InGaAs channel materials [1,2].

MAIN CHALLENGES

1) Co-integration on large area Si substrates: The maintechnological challenge is the co-integration of the dissimilarchannel materials on the same large area (300 mm or larger)Si substrate in a scalable and manufacturable process whichwill ensure volume production. There are two main routes(Fig. 1) for co-integration: (a) direct growth on bulk Si via aselective heteroepitaxial growth, (b) semiconductor-on-insulator approach. The obvious advantage of the firstapproach is its compatibility with Si CMOS manufacturing,low cost and IP re-use. On the other hand, the secondapproach offers better electrostatic control of the channel, animportant requirement to maintain performance inaggressively scaled devices.

(a)

(b)

Fig. 1 Schematic representation of dual channel CMOS (a)integration on bulk Si (b) semiconductor-on-insulatorintegration scheme. QW denotes the Ge and InGaAsquantum well channel. BOX stands for buried oxideisolation and GOI stands for germanium on insulator.

The focus here is on the first approach, which suffers fromthe well-known problems of heteroepitaxy of III-Vcompounds on silicon such as antiphase domains (APD),misfit and threading dislocations and thermal stress. Wediscuss one of the possible solutions, using Aspect RatioTrapping (ART) technology [3]. The latter takes advantageof the well known “necking” effect during growth onpatterned substrates where threading dislocations and otherdefects are confined at the bottom of deep and narrowtrenches leaving the top part defect free for devicedefinition. As technology progresses to smaller dimensions,ART becomes more effective and more important. As shownin Fig. 2, the fabrication of ART-engineered substrates startswith standard STI Si wafers followed by etching to definethe narrow trenches. A key enabler is the selective epitaxy ofGe and III-V semiconductors by MOCVD to fill the trenchesand produce high quality channel layers. A last chemical andmechanical polishing (CMP) step is needed in order to level-off the grown structures and produce smooth surfacemorphologies. Filling the trenches with good quality III-Vdevice layers is challenging.

In a process pioneered by imec, a Ge starting/seed layeris deposited directly on Si (Figs. 2 and 3) offering bettercompatibility with the MOCVD reactor growth processes

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facilitating also the local formation of double-steppedmisoriented surfaces in the trench so as to minimize APDs.

Fig. 2. Process sequence for the co-integration of Ge and III-V devices on the same ART-engineered Si substrates usingselective epitaxy in deep and narrow STI trenches

An InP buffer with or without a lattice matched InAlAsbarrier followed by a lattice matched (In composition of53%) InGaAs channel layer and a dielectric/metal gate stackcomplete the device layer structure (Fig. 3).

Most defects are trapped at the bottom of the trenches [4]and their density and propagation through the top activechannel layer are minimized (Fig. 3). During the earlydevelopment stage, severe faceting in the channel wasobserved which is progressively getting under control. Firstgeneration of functional n-FETs give satisfactorily high ON-state currents indicating that the channel is of sufficientquality. However, the OFF-state current is way too highhampering transistor performance. While reduction of

defectivity in the channel (dislocations and other defects) isalways the first priority, leakage currents through the InP orInP/InAlAs buffer or through the Si substrate is an additionalbig problem requiring an intense effort to find appropriatesolution.

Substantial innovations in the MOCVD tools areessential with regard to the susceptor design for temperaturehomogeneity, exhaust configuration for particle reductionand lower process pressures, and quartz cover plate designfor uniform showerhead temperature and particle reduction.These features ensure good selectivity and make theequipment compatible with large area (300 mm) waferprocessing in compliance with the strict contaminationavoidance rules of existing Si CMOS processing lines.

2) Surface passivation and ultrathin gate dielectrics. Asecond important challenge is to develop suitable surfacepassivation methodologies and gate dielectrics which shouldbe preferably common for both Ge (SiGe) pFET and InGaAsnFET to minimize manufacturing complexity [5]. This hasbeen demonstrated by imec using sulfur passivated Ge andInGaAs surfaces followed by rather thick (8-10 nm) Al2O3

gate dielectrics (Fig. 4).

(a)

0.7

0.6

0.5

0.4

0.3

0.2

Cap

aci

tan

ce(µ

F/c

m2)

-3 -2 -1 0 1 2 3

Gate voltage (V)

(b)

0.8

0.6

0.4

0.2Capacita

nce

(µF

/cm

2)

2.01.00.0-1.0

Gate voltage (V)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.810

11

1012

1013

Low Dit region:Enabls high drivecurrent on InGaAsn-MOSFET

Interface trap densities for InGaAs and Ge MOSCAPwith common gate stack design

Energy level above valence band edge (eV)

Dit

(ev

-1c

m-2

)

Low Dit region:Enables high drivecurrent on Gep-MOSFET

Fig. 4. After Ref. [5]. High frequency Capacitance-Voltagecurves of MOSCAPs with 8-10 nm Al2O3 gate dielectrics onSulfur- treated surfaces for InGaAs nMOS (a) and GepMOS (b) devices, showing symmetric behavior withminimum frequency dispersion in accumulation. Thebottom graph shows the interface density of states Dit in theenergy gap.

Fig. 3. Imec data, partly published in Ref [4]. SEMmicrographs showing in cross-section (a), (b) and top view(c) a III-V device layer structure selectively grown in anarrow and deep trench on Silicon. The Ge starting/seedlayer, the InP buffer and the InGaAs active channel areshown in (a).

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Although sulfur-passivated Al2O3 gate could besuitable for both type of devices (Ge pMOS and InGaAsnMOS) scaling to low enough equivalent oxide thickness(EOT) may be challenging, therefore optimization researchis on-going. The research for gate dielectrics for Ge MOSdevices has matured although a suitable gate dielectric hasnot been selected yet. The consensus is that a good qualityGeO2 (or GeOx) is essential at least as a thin interfacial layerfollowed by a metal oxide cap layer. The situation is lessclear for InGaAs MOS devices, since the MOS capacitordevice characteristics are far from ideal in most cases, forreasons which are not fully understood. Nevertheless,satisfactory InGaAs MOSFETs with relaxed EOT (~2.2 nm)have been demonstrated [6] indicating that gate dielectricsdo not present a fundamental problem. The biggest challengeat present is to scale the dielectric to low EOT values (1 nmor lower) as required, without jeopardizing the interfacequality between the dielectric and the semiconductor.Perhaps the most promising solution is proposed by U.Tokyo researchers [7] for Ge MOS: A 1-1.5 nm thick Al2O3

layer is first deposited by ALD followed by post oxidationtreatment using an ECR plasma source which produces anultrathin GeOx interfacial layer controlled by the Al2O3

oxidation barrier thickness. A good compromise betweeninterface quality and low EOT is obtained at a GeOxthickness of 0.5 nm yielding ~ 1nm EOT Ge p-MOSFETswith very good mobilities ~ 437-526 cm2/Vs.

3) Self-aligned S/D regions and metal contacts. A thirdimportant challenge is to develop very high quality ohmiccontacts for the source and drain regions for both types ofFETs [8]. The contacts should meet the stringent technologyrequirements targeting specific contact resistance Rc less

than 10-8 -cm2 -and a sheet resistance Rs < 21 /sq fortechnology nodes beyond 22 nm.

Fig. 5. After Ref. [9]. The barrier height as a function ofmetal workfunction in metal/n-type Ge Schottky diodes,showing that diode behavior is away from the ideal Scottkylimit (line (a)) and closer to the strong pinning Bardeen limit(line (b)). The Fermi level is pinned near the valence bandmaximum (inset).

In metal/semiconductor junctions, the electron barrierheight

eb, is connected to the pinning factor S, the metal

work functionm , the semiconductor affinity

s and the

charge neutrality levelLCN via sCNLCNLmeb S

,.

S=1 represents the ideal Schottky limit whereeb,

varies

linearly withm , while S=0 represents the Bardeen strong

pinning case whereeb,

is essentially independent of the

metal workfunction [8]. In Ge the Fermi level is stronglypinned (S factor~0.05-0.02) very close to the CNL which isonly 0.08-0.09 eV above the top of the valence band (VB)(see Fig. 5) [9]. This means that the Schottky barrier heightfor holes is very small facilitating the formation of goodohmic contacts in p-type S/D regions for Ge p-FETs.Similarly, good ohmic contacts for InGaAs n-FETs arefavored due to a small Schottky barrier of electrons at metal/n-type InGaAs interfaces.

The biggest challenge is to fabricate the contacts ina self-aligned way and in a Si CMOS compatible flow toensure the lateral scaling of these devices to gate lengthslower than 20 nm as required for the future technologynodes. For the case of Ge a self-aligned definition istypically achieved by blanket metal (e.g. Ni) deposition overthe device area, followed by annealing at higher temperatureto form NiGe alloy on the exposed S/D regions, andsubsequently removing the unreacted Ni over the gate orother places of the transistor by selective etching (Fig. 6)[10]. Self-aligned NiGe contacts developed and optimizedby imec have given low Rs ~9 /sq and state of the art shortchannel Ge (65nm) [11] pFETs with very good performance.

SiO2 isolationGermanide overgrowthon SiO2 isolation

NiGe on Ge

Small defectMassive voiding

330°C/Selective Etch 250°C/Selective Etch/330°C

(a) (b)

1 μm

Fig. 6. After Ref. [10]. SEM micrograph showing (a)germanide overgrowth on isolation areas and massivevoiding after a one-step RTP and (b) improved contactsafter a two-step optimized RTP.

For the case of InGaAs n-FETs, it is less clear at presentwhether a self-aligned S/D and “silicide-like” metal contacttechnology can be implemented at short channel lengths.Nevertheless, significant progress has been made by severalgroups [12, 13] focusing on Ni-InGaAs alloy (“nickelide”)contacts which offer low Rs (~25 /sq) as already shown byresearchers at Tokyo U [12]. Very recently, researchers atIBM-Zurich [13] have demonstrated MOVPE-grown raisedn+ InGaAs S/D regions of high crystalline quality withexcellent growth selectivity over the gate area. Self-aligned

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Ni-InGaAs metal contacts were realized [13] with optimizedprocess conditions leading to Rs=16.3 Ω/sq and Rc=105 Ω-μm2, although Rc is still two orders of magnitude larger thanthat expected for 11 nm node technology. Electricalproperties have been demonstrated to be stable up to 500°Cmaking this process suitable for standard BEOL/interconnectprocessing. It is worth noting that the raised S/D regions andcontact formation are compatible with ET-III-V-OIintegration platform (Fig. 1(b)). Finally, long channel(15m) FETs made with Ni-InGaAs contacting schemeshow satisfactory performance characteristics with onlyslight degradation observed after alloy foming temperaturetreatment. The specific contact resistance needs to be furtherreduced by increasing n+ InGaAs doping to meetspecifications for advanced nodes. Shorter channel FETs inthe 10nm scale need to be fabricated to prove suitability forself-aligned processing.

Fig. 7. After Ref [13]. SEM cross section of the gatepatterned substrates after S/D epitaxy, Ni-alloying andunreacted Ni removal. 10 nm Ni on 50 nm raised InGaAsannealed at 350 C for 5 min. Enhanced Ni migration close tothe gate edge is shown, which however can be minimizedusing 25 nm Ni on 100 nm raised n+ InGaAs and optimizeddouble step anneal process.

CONCLUSIONS

Development of high mobility (Ge and III-V) dualchannel CMOS faces some important challenges. First, co-integration on ART-engineered Si substrates faces theproblems of heteroepitaxy. Although faceting and threadingdefects in the InGaAs channel have been minimized, excessOFF-state leakage through the InP buffer (or Si substrate),hampers transistor performance. Second, in the area of gatedielectrics, combining good quality surface passivation withlow EOT (~1nm) is a challenge, however it is not consideredas a show stopper and significant progress has beendemonstrated. Defining S/D regions and low specific contactresistance metal contacts in a self aligned way, is a thirddifficult challenge which is currently faced using NiGe andNi-InGaAs alloy contact technology for Ge pFET andInGaAS nFET respectively.

ACKNOWLEDGEMENTS

The author acknowledges financial support from EUproject DUALLOGIC-214579 “Dual channel CMOS for(sub)-22 nm high performance logic”. Also the author wouldlike to thank M. Meuris, D. Lin, N. Waldron and M. Caymaxof imec as well as J. Fompeyrine and L. Czornomaz of IBM-Zurich and F. Schulte of AIXTRON for making availablesome of their recent results.

REFERENCES[1] International Technology Roadmap for Semiconductors (ITRS 2010

update) http://www.itrs.net/links/2010itrs/home2010.htm[2] M. Heyns and W. Tsai, “Ultimate Scaling of CMOS Devives with Ge

and III-V Materials” MRS Bulletin 34, 485 (2009)[3] Florentza et al., “Trenches Turbocharge Silicon” Compound

Semiconductors July 2009 issue, p. 21[4] G. Wang et al., “Growth of high quality InP layers in STI trenches on

miscut Si (001) substrates” J. Cryst. Growth 315, 32 (2011)[5] D. Lin et al., “Enabling the high-performance InGaAs/Ge CMOS: a

common gate stack solution” IEDM 2009 Tech. Dig. p. 327[6] M. Radosavljevic et al., “Advanced High-K Gate Dielectric for High-

Performance Short-Channel In0.7Ga0.3As Quantum Well Field EffectTransistors on Silicon Substrate for Low Power Logic Applications”,IEDM 2009, p. 319

[7] R. Zhang et al., “High mobility Ge pMOSFETs with ~1 nm thin EOTusing Al2O3/GeOx/Ge gate stacks fabricated by plasma post oxidation”

VLSI 2011 Tech. Dig. p. 56[8] A. Dimoulas, A. Toriumi, S.E. Mohney “Source and Drain Contacts

for Ge and III-V FETs for Digital Logic” MRS Bulletin 34, 522 (2009)and references therein

[9] A. Dimoulas et al, “Fermi level pinning and charge neutrality level inGe” Appl. Phys. Lett. 89, 252110 (2006)

[10] D.P. Brunco et al., “Ge MOSFET devices: advances in Materialsunderstanding, process development, and electrical performance” J.Electrochem Soc. 155, H552 (2008)

[11] J. Mitard, et al. “Record Ion/Ioff performance for 65 nm Ge pMOSFETand novel Si passivation scheme for improved EOT scalability” IEDMTech. Dig. (2008)

[12] S.H. Kim et al., “Self-aligned metal source/drain InxGa1-xAs n-MOSFETs using Ni-InGaAs alloy”, IEDM 2010 Tech. Dig. p. 596

[13] L. Chrnomaz et al., “Self-aligned S/D regions for InGaAs MOSFETs”,Proceedings ESSDERC 2011, p. 219; L. Czornomaz et al., “CMOScompatible self-aligned S/D regions for implant-free InGaAsMOSFETs” Solid-State Electronics, in press (2012)

ACRONYMS

MID: Mobile Internet DevicesFET: Field Effect TransistorsCMOS: Complementary Metal-Oxide- SemiconductorART: Aspect Ratio TrappingSTI: Shallow Trench IsolationAPD: Antiphase DomainsCMP: Chemical and Mechanical PolishingMOCVD: Metal Organic Chemical Vapor DepositionEOT: Equivalent Oxide ThicknessCNL: Charge Neutrality LevelRTP: Rapid Thermal ProcessingALD: Atomic Layer DepositionS/D: Source-DrainET-III-V-OI: Extremely thin III-V on Insulator.BEOL: Back-End of Line

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