Giao tiếp SPI_AVR

7/28/2019 Giao tip SPI_AVR

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Bi 7 - Giao tip SPI

Ni dung Cc bi cn tham kho trc

1. Gii thiu.

2. Chun truyn thng SPI.

3. Truyn thng SPI trn AVR.

Download v d

Cu trc AVR.

AVRStudio.

C cho AVR.

M phng vi Proteus.

Text LCD

I. Gii thiu.

Bi ny gip cc bn bit cch s dng cch truyn thng ni tip ng b SPI.Cng c chnh cng l 2 b phn mm AVRStudio (+gcc-avr) v Proteus. Thccht ngn ng lp trnh vn l gcc-avr nhng ti khng dng Programmer Notepad bit code nh thng thng, thay vo ti dng AVRStudio lm trnh bintp, bn tham kho thm phn Lp trnh C bng AVRStudio trong bi hng dns dng AVRStudio bit thm cch thc hin. Ti s dng chip ATmega32 lmminh ha.

Sau bi ny, ti hy vng bn c th hiu v thc hin c: Nguyn l truyn thng ni tip SPI. S dng module SPI trong AVR cc ch Master v Slave.

II. Chun truyn thng SPI,

SPI (Serial Peripheral Bus) l mt chun truyn thng ni tip tc cao dohang Motorola xut. y l kiu truyn thng Master-Slave, trong c 1 chipMaster iu phi qu trnh tuyn thng v cc chip Slaves c iu khin biMaster v th truyn thng ch xy ra gia Master v Slave. SPI l mt cch truyn

song cng (full duplex) ngha l ti cng mt thi im qu trnh truyn v nhn cth xy ra ng thi. SPI i khi c gi l chun truyn thng 4 dy v c 4ng giao tip trong chun ny l SCK (Serial Clock), MISO (Master InputSlave Output), MOSI (Master Ouput Slave Input) v SS (Slave Select). Hnh 1 thhin mt kt SPI gia mt chip Master v 3 chip Slave thng qua 4 ng.
http://www.hocavr.com/index.php/en/lectures/spihttp://www.hocavr.com/index.php/lectures/spi#gioithieuhttp://www.hocavr.com/index.php/lectures/spi#spihttp://www.hocavr.com/index.php/lectures/spi#avrspihttp://www.hocavr.com/index.php/thaoluan?func=view&catid=5&id=32#32http://www.hocavr.com/index.php/lectures/cautrucavrhttp://www.hocavr.com/index.php/software/avr-studiohttp://www.hocavr.com/index.php/software/c-cho-avrhttp://www.hocavr.com/index.php/software/c-cho-avrhttp://www.hocavr.com/index.php/software/protueshttp://www.hocavr.com/index.php/software/protueshttp://www.hocavr.com/index.php/app/textlcdhttp://www.hocavr.com/index.php/lectures/spi#gioithieuhttp://www.hocavr.com/index.php/lectures/spi#spihttp://www.hocavr.com/index.php/lectures/spi#avrspihttp://www.hocavr.com/index.php/thaoluan?func=view&catid=5&id=32#32http://www.hocavr.com/index.php/lectures/cautrucavrhttp://www.hocavr.com/index.php/software/avr-studiohttp://www.hocavr.com/index.php/software/c-cho-avrhttp://www.hocavr.com/index.php/software/protueshttp://www.hocavr.com/index.php/app/textlcdhttp://www.hocavr.com/index.php/en/lectures/spi


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Hot ng: mi chip Master hay Slave c mt thanh ghi d liu 8 bits. Cmi xung nhp do Master to ra trn ng gi nhp SCK, mt bit trong thanh ghid liu ca Master c truyn qua Slave trn ng MOSI, ng thi mt bittrong thanh ghi d liu ca chip Slave cng c truyn qua Master trn ngMISO. Do 2 gi d liu trn 2 chip c gi qua li ng thi nn qu trnh truynd liu ny c gi l song cng. Hnh 2 m t qu trnh truyn 1 gi d liuthc hin bi module SPI trong AVR, bn tri l chip Master v bn phi l Slave.

Hnh 2. Truyn d liu SPI.

Cc ca xung gi nhp, phase v cc ch hot ng: cc ca xung gi nhp(Clock Polarity) c gi tt l CPOL l khi nim dng ch trng thi ca chnSCK trng thi ngh. trng thi ngh (Idle), chn SCK c th c gi mccao (CPOL=1) hoc thp (CPOL=0). Phase (CPHA) dng ch cch m d liuc ly mu (sample) theo xung gi nhp. D liu c th c ly mu cnh lnca SCK (CPHA=0) hoc cnh xung (CPHA=1). S kt hp ca SPOL v CPHAlm nn 4 ch hot ng ca SPI. Nhn chung vic chn 1 trong 4 ch nykhng nh hng n cht lng truyn thng m ch ct sao cho c s tngthch gia Master v Slave.

III. Truyn thng SPI trn AVR.

Module SPI trong cc chip AVR hu nh hon ton ging vi chun SPI m ttrong phn trn. V th, nu hiu cch truyn thng SPI th s khng qu kh

thc hin vic truyn thng ny vi AVR. Phn bn di ti trnh by mt s imquan trng khi iu khin SPI trn AVR.

Cc chn SPI: Cc chn giao tip SPI cng chnh l cc chn PORT thng thng,v th nu mun s dng SPI chng ta cn xc lp hng cho cc chn ny. Trnchip ATmega32, cc chn SPI nh sau:


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SCK PB7 (chn 8)MISO PB6 (chn 7)MOSI PB5 (chn 6)SS PB4 (chn 5)

Khi chip AVR c s dng lm Slave, bn cn set cc chn SCK input, MOSIinput, MISO output v SS input. Nu l Master th SCK output, MISO output,MOSI input v khi ny chn SS khng quan trng, chng ta c th dng chn ny iu khin SS ca Slaves hoc bt k chn PORT thng thng no.

Thanh ghi: SPI trn AVR c vn hnh bi 3 thanh ghi bao gm thanh ghiiu khin SPCR , thanh ghi trng thi SPSR v thanh ghi d liu SPDR.

SPCR(SPI Control Register): l 1 thanh ghi 8 bit iu khin tt c hot ngca SPI.

* Bit 7- SPIE (SPI Interrupt Enable)bit cho php ngt SPI. Nu bit ny cset bng 1 v bit I trong thanh ghi trng thi c set bng 1 (sei), 1 ngt s xy rasau khi mt gi d liu c truyn hoc nhn. Chng ta nn dng ngt (nht li vi chip Slave) khi truyn nhn d liu vi SPI.

* Bit 6 SPE (SPI Enable). set bit ny ln 1 cho php b SPI hot ng. NuSPIE=0 th module SPI dng hot ng.

* Bit 5 DORD (Data Order) bit ny ch nh th t d liu cc bit ctruyn v nhn trn cc ng MISO v MOSI, khi DORD=0 bit c trng s lnnht ca d liu c truyn trc (MSB) ngc li khi DORD=1, bit LSB ctruyn trc. Tht ra khi giao tip gia 2 AVR vi nhau, th t ny khng quantrng nhng phi m bo cc bit DORD ging nhau trn c Master v Slaves.

* Bit 4 MSTR (Master/Slave Select) nu MSTR =1 th chip c nhn din lMaster, ngc li MSTR=0 th chip l Slave..

* Bit 3 v 2 CPOL v CPHA y chnh l 2 bit xc lp cc ca xung gi nhpv cnh sample d liu m chng ta kho st trong phn u. S kt hp 2 bit

ny to thnh 4 ch hot ng ca SPI. Mt ln na, chn ch no khngquan trng nhng phi m bo Master v Slave cng ch hot ng. V th cth 2 bit ny bng 0 trong tt c cc chip. Hnh 3 trnh by cch sample d liutrong 4 ch ca SPI trn AVR.


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ra khi giao tip gia 2 AVR vi nhau, th t ny khng quantrng nhng phi m bo cc bit DORD ging nhau trn cMaster v

Slaves.CPHA=0

CPHA=1

Hnh 3. Cc ch hot ng ca SPI.

* Bit 1:0 CPR1:0 hai bit ny kt hp vi bit SPI2X trong thanh ghi SPSRcho php chn tc giao tip SPI, tc ny c xc lp da trn tc ngunxung clock chia cho mt h s chia. Bng 1 tm tt cc tc m SPI trong AVRc th t. Thng thng, tc b ny khng c ln hn 1/4 tc xung nhp chochip.


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SPSR(SPI Status Register): l 1 thanh ghi trng thi ca module SPI. Trongthanh ghi ny ch c 3 bit c s dng. Bit 7 SPIF l c bo SPI, khi mt gid liu c truyn hoc nhn t SPI, bit SPIF s t ng c set len 1. Bit 6

WCOL l bt bo va chm d liu (Write Colision), bit ny c AVR set ln 1

nu chng ta c tnh vit 1 gi d liu mi vo thanh ghi d liu SPDR trong khiqu trnh truyn nhn trc cha kt thc. Bit 0 SPI2X gi l bit nhn i tc truyn, bit ny kt hp vi 2 bit SPR1:0 trong thanh ghi iu khin SPCR xc lptc cho SPI.

SPDR(SPI Data Register): l thanh ghi d liu ca SPI. Trn chip Master,ghi gi tr vo thanh ghi SPDR s kch qu trnh tuyn thng SPI. Trn chip Slave,

d liu nhn c t Master s lu trong thanh ghi SPDR, d liu c lu sntrong SPDR s c truyn cho Master.

S dng SPI trn AVR: SPI trn AVR hot ng khng khc nguyn l chungca chun SPI l my. Vn hnh SPI trn AVR c thc hin da trn vic ghi vc 3 cc thanh ghi SPCR, SPSR v SPDR. Trc khi truyn nhn bng SPI chngta cn khi ng SPI, qu trnh khi ng thng bao gm chn hng giao tipcho cc chn SPI, chn loi giao tip: Master hay Slave, chn ch SPI (SPOL,SPHA) v chn tc giao tip. Truyn thng SPI lun c khi xng bi chipMaster, khi Master mun giao tip vi 1 Slave no , n s ko chn SS ca

Slave xung mc thp (gi l chn a ch) v sau vit d liu cn truyn vothanh ghi d liu SPDR, khi d liu va c vit vo SPDR xung gi nhp sc t ng to ra trn SCK v qu trnh truyn nhn bt u. i vi cc chipSlave, khi chn SS b ko xung n s sn sng cho qu trnh truyn nhn. Khi

pht hin xung gi nhp trn SCK, Slave s bt u sample d liu n trn ngMOSI v gi d liu di trn MISO.


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minh ha cho cch truyn v nhn d liu SPI trn AVR, ti s thc hinmt v d truyn nhn 1 chiu vi 1 chip Master v 3 chip Slaves. Tt c cc chipc dng l ATmega32, chip Master s iu khin cc chip Slaves thng qua 3ng chn chip PB0, PD1 v PD2. Cng vic thc hin trong v d ny nh sau:Master s ln lt chn 1 trong 3 chip Slaves v gi cc gi d liu tng ng nchng, chip Slave0 s nhn c cc con s t 0 n 80, Slave1 nhn 80 n 160v Slave2 nhn d liu t 160 n 240. Cc Slave s hin th gi tr m mnh nhnc trn cc Text LCD kt ni vi PORTD mi Slave. S mch in v

bng Proteus cho v d ny c trnh by trong hnh 4.


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Hnh 4. M phng v d giao tip SPI trn AVR.

Trong bi ny, ti s dng phn mm AVRStudio kt hp vi gcc-avr trongWinAVR lp trnh bng ngn ng C cho AVR. Bn hy tham kho thm bi


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AVRStudio bit cch to 1 Project lp trnh C cho AVR bng AVRStudio. Hyto 2 Project ring, 1 Project c tn SPI_Master cho chip Master v 1 Project ctn SPI_Slave dng chung cho c 3 Slaves. Copy file myLCD.h dng cho iukhin Text LCD c to trong bi Text LCD vo c 2 th mc cha 2 Projectsmi to. Vit on code trong list 0 vo file SPI_Master.c v on code trong list 1vo file SPI_Slave.c.

List 1. on code cho SPI Master.


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Ti s gii thch s lt mt s im chnh trong on code cho chip Master.Cc phn nh ngha t dng th 10 n dng 17 ch c tc dng lm cho chngtrnh d c hiu hn v c tnh tng thch cao hn, v d nu bn mun s dng

v d ny cho cc chip khc bn ch cn thay i cc nh ngha ny m khng phithay i trong ni dung cc chng trnh con. Chng ta nh ngha chnPORTB iu khin cc ng chn chip SS ca Slave (gi l cc ng a ch),dng 18 nh ngha Slave(i) l th t chn trn PORT dng cho chip Slave th i.D hiu hn, ng SS trn Slave0 s c kt ni v iu khin bi chn 0 caPORTB (chn PB0 v tng t cho cc Slaves cn li. Bin wData nh ngha trndng 20 l mt mng 3 phn t cha cc con s 8 bits s truyn n cc Slaves.

Chng trnh con void SPI_MasterInit(void): Chng trnh ny khi ngcho chip Master, vic khi ng trc ht l set hng cho cc chn SPI. i vi

Master, cc chn to xung gi nhp SCK v chn truyn d liu MOSI cn cset Output nh trong dng 24, cc chn SPI cn li l input. Dng 25 gip ko intr ko ln chn nhn d liu MISO ca Master. Dng lnh 26SPCR=(1


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Chng trnh chnh: chng trnh chnh cho chip Master SPI tng i ngin, trc ht chng ta cn gi chng trnh con khi ng SPI dng 43. Trongvng lp v tn while, ln lt gi cc gi tr n cc Slaves. Dng 46 gi chngtrnh con gi gi tr bin wData[0] n Slave0, dng 50 truyn bin wData[1] choSlave1 v dng 54 truyn bin wData[2] cho Slave2

List 2.on code cho Slave SPI.


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on code trong list 2 l on code cho chip Slaves, ch dng 3 chng tainclude file header interrupt.h v vic nhn d liu SPI ca SLave c thc hin

bng ngt SPI. Cc nh ngha bin trong cc dng code t 8 n 15 tng t nhtrong chng trnh cho chip Master. Ti s tp trung gii thch cc im khc bitcho Slaves.

Chng trnh con void SPI_SlaveInit(void): Chng trnh ny khi ngcho chip Slave, cng ging nh trng hp ca Master, vic khi ng trc ht lset hng cho cc chn SPI. i vi Slave, ch c chn truyn d liu MISO l cnc set Output nh trong dng 19, cc chn SPI cn li l input. Dng 20 gipko in tr ko ln cc chn nhn d liu MOSI ca Slave, v chn chn SlaveSS. Vic tip theo l ci t cc thanh ghi SPI nh trong dng lnh 21,SPCR=(1


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ng LCD dng 29 v kt thc. Khng c vic g cn thc hin trong vng lpwhile().

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Giao tiếp SPI_AVR