ng

ngin

eeri

nspla

yEn

Thin Film Transistor

on t

oD

isnfo

rmatio

In

TFT-LCD DRAM ng TFT-LCD DRAM

ngin

eeri

n TFT LCD DRAM

Substrate c-Si

spla

yEn

TFT, Cs, Transistor, Capacitor

Gate & Data Bit & Word Line

on t

oD

is

Line-by-Line Random access

nfo

rmatio

,

Design Rule ( 4m) (nano scale)

In

Chip /

TFT-array ng

35 chip/ 100 chip/

ngin

eeri

nspla

yEn

Chip

on t

oD

isnfo

rmatio

=91.4% (32/35) =97.0% (97/100)

Chip

In

Chip

Chip Chip

LCD: chip .

TFT-array ng 12 panel/

(A)

(b)

ngin

eeri

n

6 panel/

1 panel/

G4 G5 a)

spla

yEn

(B

)

(a

TFT-array ng

1 6

1.8

2.0

(m)

G72200x1870

1800x1500

ngin

eeri

n

1.0

1.2

1.41.6

G5

G6 1.48

1800x1500

1300x1100

spla

yEn

0.2

0.4

0.60.8

G1

G3G4

G5

G2

1.89

2.13

830x650720x60 3.5th

920x730650x550

370x470300x250

on t

oD

is

0.2 0.60.4 1.00.8 1.41.2 1.81.6 2.0 2.42.2 (m)

G1

720x600

3.5th

nfo

rmatio

3 3.5 4 5 6 7

650x550 720x600 920x730 1300x1100 1800x1500 2200x1870

In 12.1x615.0x4

14.1x6

17.0x4

14.1x9

15.4Wx8

17.0x6

21.3x4

15.0x16

17.0x12

19.0x9

23Wx8

17.0x24

26Wx12

32Wx8

37Wx6

23Wx24

26Wx18

32Wx12

40Wx8

26Wx6 46Wx6

(:mm, )

LCD LCD

< Segment dot Matrix >

of

LC

s

- direct (static ): -

- multiplex

Phys

ics

Matrix Display

< Passive Matrix LCD & Active Matrix LCD >

Memory mode

of

LC

s

- dot matrix display passive matrix active matrix multiplex

Phys

ics active matrix multiplex .

- multiplex (Scanning electrode) (signal electrode) .`

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

Structure of TFT

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

Silicon (Si) Energy Band

ng < > < >

ngin

eeri

nspla

yEn

Conductionband

Ed

Dangling bondsTerminated byhydrogen atoms

5.43

on t

oD

is band Eg

Donor level

Fermi level

Acceptor level

Ea

Localized states5.43

nfo

rmatio

Valenceband

0Acceptor level

(a) c-Si (b) a-Si (c) a-Si:H

- - - 4 nearest neighbor &12 next nearest neighborband gap energy : 1 1 eV at 300KIn

(Hydrogenated Amorphous Silicon (a-Si:H)

- band gap energy : 1.1 eV at 300K

Dangling bond Localized State a-Si:H : (1979 Lecomber a-Si:H TFT )

Si H TFT ( TFT 1979)

ng

a-Si:H TFT ( TFT, 1979)

ngin

eeri

n -

-

spla

yEn

-

(TFT/ )

on t

oD

is (TFT/, , )

-

tt (

< (a-Si:H) >

ng

< (a Si:H) >

- PECVD a-Si:H

ngin

eeri

n

Physical parameters Typical values

Dark conductivity 310-10 S/

spla

yEn Activation energy 0.76 eV

Photoconductivity 110-4 S/

Optical band gap ~1.8 eV

on t

oD

is

Electron mobility 0.5 ~ 1.0 /V-sec

Hole mobility 1 ~ 510-3 /V-sec

Electron affinity 3.93 eV

nfo

rmatio

Refraction index 4.3

Density 2.2 g/

Hydrogen content 10 ~ 15 wt %

In

Hydrogen content 10 15 wt.%

Crystallization temperature 675

Valence band tail slope ~ 45 meV

Conduction band tail slope 25 meVConduction band tail slope ~ 25 meV

< MOSFET TFT >

ng

ngin

eeri

n Planar vs. Staggered TFT

spla

yEn

on t

oD

isnfo

rmatio

In

- C-Si wafer - Gate & Source-Drain

- glass a-Si:H - Gate & Source-DrainGate & Source Drain

Gate & Source Drain

< Top Gate Bottom Gate TFT >ng

Staggered vs. Inverted Staggered TFT

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

PECVD SiNx a Si:H n+ a si:H In - PECVD - Subcutaneous reaction: Si rich SiNx SiNx a-Si:H TFT (TFT )Backlight

- SiNx, a-Si:H, n+ a-si:H PECVD

- a-Si:H/SiNx - Backlight

- Backlight

< Etch Back Type TFT Etch Stopper Type TFT >

ng

< Etch Back Type TFT Etch Stopper Type TFT >

ngin

eeri

nspla

yEn

on t

oD

is

n+ a-Si:H

a-Si:H PECVD(1) SiNx(E/S)

n+ a-Si:H PECVD(2nd)

nfo

rmatio

- n+ a-Si:H a-Si:H

a Si:HSiNx

PECVD(1) SiNx(E/S)

a-Si:HSiNx

PECVD(1st)

- Channel a-Si:H

In

n+ a Si:H a Si:H Active layer

- a-Si:H 200~300 : .

- n+ a-Si:H

Channel a Si:H a-Si:H

- PECVD , (50)

- ( ) n a Si:H .

( ) - PECVD

< Self-Align E/S Type TFT TFT >

ng

< Self Align E/S Type TFT TFT >

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

Etch-Stopper Gate a-Si

(a) Self-Align E/S (b) Self-Align E/S Type TFT

In

- TFT array Source-Drain overlap TFT Gate mask - TFT Gate mask

TFT

ng TFT -

active layer Gate

- Gate a-Si:H layer threshold voltage TFT off

ngin

eeri

n - active layer Gate - Gate - Ohomic ( Source-Drain )- W/L

mobility

- threshold voltage TFT off- threshold voltage free electron

(mobile carrier) , Source-Drain TFT on a Si:H

spla

yEn - mobility

< a-Si:H TFT >V I

- a-Si:H , band-gap trap ,

- Source carrierinjection . (Source-Drain )

on t

oD

is

carrier injectionn+ a-Si:H(ohmic )

VDS IDS )

nfo

rmatio

carrier accumulationn a Si:H(ohmic )

a-Si:H( )

In

carrier moving SiNx()

GateVG

< TFT - (I-V) >< TFT (I V) >

of

LC

s

Gate Source (hole) TFT off TFT off -5V Gate

[MOSFET -(I-V) ]VG 20V VD 10V Vth 5V (VG > VD +Vth) TFT on

Phys

ics

TFT off .

< TFT I-V >

of

LC

s

- K: TFT - TFT (VG > VD +Vth)

Phys

ics

- Source-Drain Id Gate VG plot K, x TFT Vth

ng

ngin

eeri

nspla

yEn

TFT-LCD

on t

oD

isnfo

rmatio

In

TFT-array ng

B di P d D (3 072)

< XGA Color TFT-array >

ngin

eeri

n Bonding Pad Data (3,072)

spla

yEn Data Unit Pixel

on t

oD

is (ITO, Cs)

TFT

nfo

rmatio

Gate

TFTGate (768)

In

TFT Array Panel

ng

ngin

eeri

n

- - Cs on gate

spla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

Gate pulse width = (mf)-1p ( )where m: # of gate line

f : frame rate

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

Unit cell ng

RED GREEN BLUE

t -V21 -V22 -V23+V11

V

-V12

V

-V13

V

ngin

eeri

n

+VCOM

t V21 22 23-V31 -V32 -V33

D1 D2 D3

V Vt

spla

yEn -

VCOM

(VCOM : CF )

-5V VOFFG1

off offoff+V11 -V12 +V13

on t

oD

is )

20V VON

Selected Gate

G2

onon on-V21 +V22 -V23

nfo

rmatio

VOFFG3

off off off+V31 -V32 +V33

(ITO) (Cs)

-5V

In

Li b Li dd i

(3 x 3) Active Matrix LCD

(ITO) (Cs)

Line-by-Line addressing

Gate refresh Data write

Unit cell ng

Source LDI

ngin

eeri

nspla

yEn

+

on t

oD

is

-

nfo

rmatio

In

(a) Dot (c) V-Line (b) (2X1)

S LDI C t l Source LDI Control

LCD panel ng Source LDI (S/H & D/A)Serial Data

010001010

ngin

eeri

n

0 0 0 0 0 00 0 0

5 555 5 588 8 Volt

010001010

spla

yEn 0 0 0 0 0 00 0 0

0 0 0 0 0 00 0 0

0 0 1 1 1 00 0 0

0 0 0 1 1 01 1 1

on t

oD

is 0 0 1 1 1 00 0 00 1 0 0 1 00 0 1

1 1 1 0 1 01 1 0

1 0 0 1 0 00 0 0 Selecte

nfo

rmatio 1 0 0 1 0 00 0 0

1 0 0 0 0 00 1 1

1 1 1 0 0 01 1 0

ScanSelected Line

(I LCD )In (Bit image in Graphic memory) (Image on LCD screen )

S LDI C t l Source LDI Control

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

R: 8 level, G: 8 level, B: 8 level # of Colors : 8 x 8 x 8 = 512

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

dotColor

ng

G R G

dot

pixel

ngin

eeri

n

R BG

R BG

R BG R G

R B G

R BG R BG

R

R G

G

B

R RG GB

spla

yEn R BG R BG

R BG R BG

R

B

G

R G

R BG R BG

R BG R BG

R G

R

R

R

R

RG

G

G

GB

B

B

RB G

on t

oD

is

BR BGR BG R G R BGBG R G R RG

B R G B

B G

( ) S i (b) M i ( ) D lt

nfo

rmatio

(a) Stripe (b) Mosaic (c) Delta

(3 x 3) Active Matrix LCD

In Stripe

CF

TFT-array

RGB

Line-by-Line RGB

Mosaic

RGB

Image

Delta

TFT-LCD

Line by Line RGB scan line

Image

OA

Data line

Color ng 12 1XGA : 0 080 mm x 0 240mm (106ppi)

dot-0.1mm(Unit Pixel )

ngin

eeri

n

R BG12.1 XGA : 0.080 mm x 0.240mm (106ppi)

14.1XGA : 0.09325 mm x 0.27975mm (91ppi)

17 0SXGA : 0 090 mm x 0 270mm (94ppi)

-0.3mm

spla

yEn 17.0 SXGA : 0.090 mm x 0.270mm (94ppi)

21.3UXGA : 0.090 mm x 0.270mm (94ppi)

Sub-pixel

on t

oD

is

~ 0.014

~40cm

ppi: pixel per inch

Retina

nfo

rmatio Retina

In < 0.03 Mixed color

RGB color mix

Color ng

Backlight Spectra

Transmitted Lights

ngin

eeri

n

Color Filter Spectra

TFT-Array Color-Filter

spla

yEn

Transmitted Lights

on t

oD

isnfo

rmatio

Backlight

LCD LCD RGB primary color In LCD

RGB

LCD RGB primary color

RGB spectrum BacklightLC layer Color filter RGB primary color Color filter B kli ht t

TFT-LCD Color Generation

Backlight spectrum

Color ng

Color A = rR + gG +bB

r = R /(R + G + B)

ngin

eeri

n

(a) Display A(b)

g = G/(R + G + B)

b = B /(R + G + B)

With r + g+ b = 1

spla

yEn (b)

Display B

on t

oD

isnfo

rmatio

3-D Color Space 2-D Color Corrdinate CIE 1931 x-y NTSC

In

Color Balance

Color Reproducibility or Color Saturation

Color Reproducibility of Display (a) =

Area of (a)Saturation

Color TemperatureArea of (a)

Area of (NTSC)X 100%

ng

ngin

eeri

nspla

yEn

TFT

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

TFT

ng

< TFT Gate Source Drain Overlap >

TFT

TFT-array

ngin

eeri

n < TFT Gate Source-Drain Overlap >

: W/L

*Kickback - TFT

spla

yEn W/L .

W/L , TFT

.

- TFT-LCD Gate

on t

oD

is

Source Drain

TFT .

nfo

rmatio

LIn LL L overlap capacitance .Vp kick back

Staggered TFT 1~2 . kick back (photolithography overlap)

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

-Gate TFT Gate RC-delay

ngin

eeri

n

< TFT-LCD >

TFT LCD Gate

y Gate

spla

yEn

Etch

()

Al ITO

< TFT LCD >

on t

oD

is Cu Wet 2.1

Al Wet or Dry 3.5 -

Al-Nd Wet or Dry ~5 -

nfo

rmatio Al Nd Wet or Dry 5

Mo Wet or Dry 12

MoW Dry 15

In -Ta Dry 25

Cr Wet 25

MoTa Dry 36 MoTa Dry 36

< TFT Gate >ng

ngin

eeri

nspla

yEn

Photo Gate

on t

oD

is Gate .

Photo

nfo

rmatio Photo

.

In .

ng

- ITO Gate Ioverlap) (Cs) .

ngin

eeri

n

< >

Ioverlap) (Cs) . - Cs overlap

spla

yEn < >

Storage-on-Common

on t

oD

isnfo

rmatio

In

TFT

ng

< Cst-on-Gate >

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

TFT

In

- Gate Cs Cs .

- Gate DC Gate

< ITO Cs TFT-array >ng

- (Cs) .

ngin

eeri

n

Source Drain

Cs(Gate )

spla

yEn

Gate

on t

oD

is

Backlight

nfo

rmatio

Source Drain

Cs( ITO)

In

GateGate

Backlight

TFT-array ng

Cs

Line Defects

Pixel Defects

ngin

eeri

n Cs short

Data-ITO short

Pixel Defects (Point Defects)

spla

yEn

open

Cross- TFT

short

on t

oD

is Crossover short

ITO

short

ITO-ITO short

nfo

rmatio

TFT

In

open

TFT-array

open

TFT-array ng

LCD

ngin

eeri

nspla

yEn

Pattern

on t

oD

is Pattern TFT Patterned

Open cross-over short

nfo

rmatio

Dual-TFTDual-Pixel

In

Dual PixelLaser cutting Laser Repair

TFT TFT-array

TFT-array ng

Gate Data

ngin

eeri

n

i i

spla

yEn

CsCst

on t

oD

is

L C t (ITO)

nfo

rmatio

TFT TFT shortLaser Cut

Dual TFT redundancy

In

redundancy

2 TFT

TFT TFT

Laser cutting TFT

TFT-array ng

Data

(1)Data (2)

ngin

eeri

n

(Cs)

(Cs)

spla

yEn

(ITO)

(ITO)

on t

oD

is

TFT

nfo

rmatio

TFT

TFT-array dual-pixel redundancy TFT redundancy

Data In

2 TFT, ,

Data

Data short

Short laser cutting

TFT-array ng

Gate open (Fault-Tolerant)

Data

ngin

eeri

n

Gate (1)

Tolerant)

spla

yEn Gate (1)

Gate (2)

on t

oD

isnfo

rmatio

In

Cross-Over Shot (Laser cut )

Fault-Tolerant

TFT-array ng Laser (welding) Data Display

ngin

eeri

n Laser (welding) Data area

spla

yEn

Laser welding cross-

on t

oD

is Laser welding cross-over short Data

nfo

rmatio

Open

, RC-delay

In

ng

ngin

eeri

n

TFT-LCD

spla

yEn TFT-LCD

on t

oD

isnfo

rmatio

In

TFT-Array ng

TFT-Array

-

ngin

eeri

n

- (ex. Bottom gate E/B type TFT )

spla

yEn

Gate Pattern

a Si:H Pattern

Gate Pattern

a Si:H & S/D Pattern

on t

oD

is a-Si:H Pattern

S/D Pattern

a-Si:H & S/D Pattern

Contact Etch

nfo

rmatio

Contact Etch

ITO Pattern

ITO Pattern

In

* Other steps are same

(a) Conventional 5-mask (b) 4-mask

TFT-Array ng

UV exposure Slit MASK

ngin

eeri

n

under exposure

Slit

spla

yEn

n+ a-Si

S/D

PR

(under exposure)

on t

oD

is

Glass Gate SiNx

a-Si (under exposure)

(a) slit

nfo

rmatio

PR

PR

In

G SiN

a-Si

n+ a-Si

S/D

PR

11 photolithographyphotolithography Glass Gate SiNx

11 photolithography photolithography PR PR

(b) PR

PR

S/D a-Si:H

ng

Gl SiN

a-Si

n+ a-Si

S/D

PR

S/D, a-Si:H

ngin

eeri

n

PR Etch-Back

Glass Gate SiNx

(c) S/D active

spla

yEn

S/D

PR

on t

oD

is

Glass Gate SiNx

a-Si

n+ a-Si

nfo

rmatio

S/D n+ a-Si:H Etch Back

(d) PR Etch-Back Define

In

a Si

n+ a-Si

S/D

PR

Glass Gate SiNx

a-Si

4-mask TFT

(e) S/D n+ a-Si:H Etch Back

ng

ngin

eeri

n

Glass GlassGate Gate

(f) SiNx contact window open (g) ITO

spla

yEn (f) SiNx contact window open (g) ITO

on t

oD

is Slit Mask

- Photolithography

nfo

rmatio

- TFT-Array

In

ng

TFT backlight

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

TFT-LCD

ngin

eeri

n = Backlight LCD (cf. TFT-LCD < 10% )

spla

yEn

=

on t

oD

is

- BLU

nfo

rmatio BLU

- BLU

In

= =

ng (Aperture)

ngin

eeri

nspla

yEn

on t

oD

is

R G B

nfo

rmatio

In

(a) TFT-Array (b) Color filter y

Cell Aperture Area

ng

< Unit Pixel Opaque area Aperture area >

Gate

ngin

eeri

n

Cs

Gate

spla

yEn

Data

BM BM(CF)

on t

oD

is

(ITO)

TFTAperture

CF

nfo

rmatio

Data

TFT

In Data

- TFT, , (opaque area)TFT-array TFT array .

- BM overlap

< BM-on-TFT array >ng

Aperture

BM

ngin

eeri

n Aperture

CF

(~10)

- CF BM 5 &

gap

spla

yEn

BM

TFT

( 10) Fringe-Field

CF BM 10

on t

oD

is

Data

Aperture

- BM-on-TFT array TFT-array

photolithography

nfo

rmatio

CF

(~1)

1~2 .

In BM

D t

TFT

( 1)

Data BM-on-TFT array

ng

(BM)CF

ngin

eeri

n (BM)

spla

yEn

on t

oD

is

nfo

rmatio

coupling In - coupling .

- BM .

-

: coupling .

: BM TFT-Array

Color Filter on Array (COA)ng

yngin

eeri

n

(ITO)

spla

yEn

on t

oD

is

(TFT+C/F)

nfo

rmatio

PR

PR In - PR

-

: PR TFT-Array fringe field

: BM => .

:

Color Filter on Array (COA)ng

ngin

eeri

nspla

yEn

60%

78%

on t

oD

is

27m 12m

nfo

rmatio

In

BM CF COA

ng

ngin

eeri

nspla

yEn

What is Next ?

on t

oD

isnfo

rmatio

In

ng

TFT

A-Si TFT Poly-Si TFT X-Si TFT

ngin

eeri

n A-Si TFT Poly-Si TFT X-Si TFT

spla

yEn

on t

oD

isnfo

rmatio

In

ng

Excimer Laser Annealing of a-Si (XeCl, 308nm, 30~45ns, line beam)

ngin

eeri

nspla

yEn

on t

oD

isnfo

rmatio

In

ng

ngin

eeri

n

Gate Driving IC

S/H

Gate Driving IC Gate Driving IC

spla

yEn a-Si

TFT-LCD Timing

Controller p-SiTFT-LCD

S/H

ControlIC

SLS-SiTFT-LCD

x-Si

on t

oD

is

aa--Si TFTSi TFT xx--Si TFTSi TFTpp--Si TFTSi TFTData Driving IC Control IC Data Driving IC

nfo

rmatio

Mobility : 0.5cm2/VsHighly Uniform TFTsSimple Process

Mobility > 600cm2/ /VsSystem on GlassGlass Semiconductor

Mobility : 50~200cm2 /Vs Integrated Driver 200 ppi High ResolutionIn Simple Process Glass Semiconductor200 ppi High Resolution