gm1601 LCD TV/Monitor Controller - read.pudn.comread.pudn.com/downloads161/doc/project/728929/1601-DataSheet-01F.pdf · PRELIMINARY DATA SHEET gm1601 LCD TV/Monitor Controller C1601-DAT-01F

PRELIMINARY DATA SHEET

gm1601 LCD TV/Monitor Controller

C1601-DAT-01F November 2003

Genesis Microchip Inc. 2150 Gold Street, P.O. Box 2150, Alviso, CA USA 95002, Tel 408-262-6599, Fax 408-262-6365

165 Commerce Valley Dr. West, Thornhill, ON Canada L3T 7V8, Tel 905-889-5400, Fax 905-889-5422 George Thangiah Complex(E), 2nd Flr, 80 Feet Road, Jeevan Bhima Nagar, Bangalore 560 075, India, Tel 91-80-526 3878, Fax 91-80-529 6245

4F, No. 57, Sing Jung Road, NeiHu Taipei, Taiwan 114, R.O.C, Tel 886-2-2791-0118, Fax 886-2-2791-0196 4F, Century Tower, 1337-20 Seocho-Dong, Seocho-Ku, Seoul, Korea, 137-070, Tel 82-2-3486-2071, Fax 82-2-3486-2079 10/F East, Legend Building, High-Tech Industrial Park, Shenzhen, P. R. C., Tel 86-755-26982060, Fax 86-755-26982050

#310-311 Century Financial Tower, No. 1, Su Hua Road, Suzhou Industrial Park, Suzhou, Jiangsu Province, P.R.C., 215021 Tel 86-512-67620380, Fax 86-512-67620385 2-9-5 Higashigotanda, Shinagawa-ku, Tokyo, 141-0022, Japan, Tel 81-3-5798-2758, Fax 81-3-5798-2759

www.genesis-microchip.com

gm1601 Preliminary Data Sheet

Title: gm1601 Preliminary Data Sheet Document: C1601-DAT-01F Date: November 2003 Revision History

Document Description Date

C1601-DAT-01A • Initial release. Jan 2003 C1601-DAT-01B • Display port pin-outs renamed to reflect the dual functionality TTL/LVDS

• Display port GPIO pins changed to TTL outputs • Updated pin listing / pin diagram for consistency • Minor revisions and updates to section 4 • Added typical current measurements to Table 25

April 2003

C1601-DAT-01C • Added Low Power and WXGA current information • Updated Table of Contents and List of Figures • Table 23 (Bootstrap Signals) was updated. • Updated Fig. 29 and Fig. 30 • Split datasheet into one for gm1601 and one for gm1601H

June 3 2003

C1601-DAT-01D • Edited Table 23 • DDC2BI_SEL OCM_ADDR9

‘0’ = Enable DDC2BI on DVI port ‘1’ = Enable DDC2BI on VGA port

Sept 2003

C1601-DAT-01E • Updated Table 24 to incorporate note 5 concerning ESD. • Updated Table 8, Figure 9, Table 26, Table 31, Figure 35, Table 33. • Added notification concerning vertical flip in section 4.9.5

Sept 2003

C1601-DAT-01F • Minor cross-reference updates. • Table 24: Correct soldering temps: 210C for non-LF and 250C for LF • Clarifications to sections: • 1.3: Digital Video/Graphics section: Accepts video and graphics data • 4.6:.one BT-656 stream processed at a time • 4.7 (editorial) • 4.9.7: MADI is only supported in the video processing data path. • 4.14: Six-bit and eight-bit panels... ten-bit... interface • 4.14.3: 24 data bits, three control signals (HS, VS, DE) can be mapped onto LVDS interface • 4.15: variable frequency display clock • Added Section 8: solder reflow profiles: gm1601 and gm1601-LF • Figure 3: 8-bit ITU656 YUV Input; 24-bit input port / 16-bit YUV

Nov 2003

Related documents Chip documents

C1601-PBR-01D gm1601 Preliminary Product Brief C1601-DSL-01C gm1601 Register Listing C1601-SLG-01C gm1601 System Layout Guidelines S0035-GUD-01D Genesis JTAG V0.4 Support in Paradigm C++ Professional Compiler


*** Preliminary Information – Subject to Change *** http://www.genesis-microchip.com

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The following are Trademarks or Registered trademarks of Genesis Microchip Inc.:

GenesisTM Genesis Display PerfectionTM ESMTM RealColor® Ultra-Reliable DVI® Real RecoveryTM SmartScan® Acuity Resizing® DICE® Genscale® Surelock® What’s On® Crystal Cinema SmartTUBE SageTM SmartsetTM Jag-ASMTM SureSyncTM Intelligent Picture Processing™ Adaptive Contrast Control™ Adaptive Backlight Control™ Faroudja® DCDiTM by Faroudja TrueLifeTM IntelliCombTM

Other brand or product names are trademarks of their respective holders. Paradigm C++ Professional Paradigm Systems

Copyright 2003 Genesis Microchip Inc. All Rights Reserved

Genesis Microchip Inc. reserves the right to change or modify the information contained herein without notice. It is the customer’s responsibility to ensure he/she has the most recent revision of this Document. Genesis Microchip Inc. makes no warranty for the use of its products and bears no responsibility for any errors or omissions which may appear in this document.

C1601-DAT-01F November 2003 *** Preliminary Information – Subject to Change ***

http://www.genesis-microchip.com

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Table Of Contents

1. Overview ............................................................................................................................................ 1 1.1 Applications ................................................................................................................................. 1 1.2 gm1601 System Design Example ................................................................................................ 1 1.3 gm1601 Features .......................................................................................................................... 2

2. gm1601 Pinout ................................................................................................................................... 3

3. gm1601 Pin List ................................................................................................................................. 5

4. Functional Description ..................................................................................................................... 21 4.1 Clock Generation ....................................................................................................................... 21

4.1.1 Using the Internal Oscillator with External Crystal............................................................ 22 4.1.2 Using an External Clock Oscillator .................................................................................... 25 4.1.3 Clock Synthesis................................................................................................................... 26

4.2 Hardware Reset .......................................................................................................................... 28 4.3 Software Reset ........................................................................................................................... 28 4.4 Analog to Digital Converter (ADC)........................................................................................... 29

4.4.1 ADC Pin Connection .......................................................................................................... 29 4.4.2 ADC Characteristics ........................................................................................................... 30 4.4.3 Clock Recovery Circuit ...................................................................................................... 30 4.4.4 Sampling Phase Adjustment ............................................................................................... 31 4.4.5 ADC Capture Window........................................................................................................ 31

4.5 Ultra-Reliable Digital Visual Interface Receiver (DVI Rx)....................................................... 32 4.5.1 DVI Receiver Characteristics ............................................................................................. 32 4.5.2 DVI Capture Window......................................................................................................... 32

4.6 Digital Video Graphics Port....................................................................................................... 33 4.6.1 656 Decoder........................................................................................................................ 34 4.6.2 YCbCr Input Clamping....................................................................................................... 34

4.7 Test Pattern Generator (TPG) .................................................................................................... 34 4.8 Input Format Measurement (IFM) ............................................................................................. 35

4.8.1 HSYNC / VSYNC Delay.................................................................................................... 35 4.8.2 Horizontal and Vertical Measurement ................................................................................ 36 4.8.3 Format Change Detection ................................................................................................... 37 4.8.4 Watchdog............................................................................................................................ 37 4.8.5 Internal Odd/Even Field Detection ..................................................................................... 37 4.8.6 Input Pixel Measurement .................................................................................................... 38 4.8.7 Image Phase Measurement ................................................................................................. 38 4.8.8 Image Boundary Detection ................................................................................................. 38 4.8.9 Image Auto Balance............................................................................................................ 38

4.9 RealColorTM Digital Color Controls .......................................................................................... 39



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系统设计实例

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利用内部时钟外部晶体

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利用外部时钟

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综合时钟

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AD转换 4.4.1 ADC管脚连接 4.4.2 ADC特征 4.4.3时钟恢复电路

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4.4.4 相位调整取样 4.4.5 ADC捕获窗口

Edited by Foxit Reader Copyright(C) by Foxit Software Company,2005-2007 For Evaluation Only.

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4.5 超可靠DVI接收器 4.5.1 接收器特性 4.5.2 捕获窗口

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4.6 数字视频图形接口 4.6.1 656解码器 4.6.2 YCbCr 输入钳位

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测试模拟发生器？

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行和场的度量

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4.8.7 图像状态度量？ 4.8.8 图像范围 4.8.9 图像自动调整


4.9.1 RealColor™ Flesh tone Adjustment ................................................................................... 39 4.9.2 Color Standardization and sRGB Support .......................................................................... 39 4.9.3 Zoom Scaling...................................................................................................................... 40 4.9.4 Horizontal and Vertical Shrink ........................................................................................... 40 4.9.5 Image Flip ........................................................................................................................... 40 4.9.6 Inverse 3:2 / 2:2 Pull-down De-Interlacing ........................................................................ 40 4.9.7 Motion Adaptive De-Interlacing (MADI) .......................................................................... 41 4.9.8 Low Angle Diagonal Interpolation ..................................................................................... 41 4.9.9 “3D” Noise Reduction ........................................................................................................ 41 4.9.10 Sharpening Filters ............................................................................................................. 42

4.10 Bypass Options ........................................................................................................................ 43 4.11 Gamma Look Up Table (LUT) ................................................................................................ 43 4.12 Picture-In-Picture (PIP) Display .............................................................................................. 43 4.13 Frame Store Interface............................................................................................................... 44

4.13.1 Supported DDR Devices................................................................................................... 44 4.13.2 Adjustable Frame Store Interface Parameters................................................................... 44 4.13.3 DDR Memory Power On and Initialization Sequence...................................................... 44 4.13.4 DDR Memory Power Down ............................................................................................. 44 4.13.5 Pan and Crop Operations .................................................................................................. 44 4.13.6 Double Buffering Frame Store Bandwidth Requirements ................................................ 45 4.13.7 Freeze Frame..................................................................................................................... 45

4.14 Display Output Interface.......................................................................................................... 45 4.14.1 Display Synchronization................................................................................................... 45 4.14.2 Display Timing Programming .......................................................................................... 45 4.14.3 LVDS Transmitter ............................................................................................................ 47 4.14.4 Panel Power Sequencing (PPWR, PBIAS) ....................................................................... 48 4.14.5 Output Dithering ............................................................................................................... 48

4.15 Energy Spectrum Management (ESMTM) ................................................................................ 49 4.16 OSD.......................................................................................................................................... 49

4.16.1 Color Look Up Tables (CLUT) ........................................................................................ 50 4.17 On-Chip Microcontroller (OCM)............................................................................................. 50

4.17.1 Normal Configuration....................................................................................................... 50 4.17.2 In-System-Programming (ISP) of Flash ROM Devices ................................................... 51 4.17.3 External Chip Select Signals............................................................................................. 51 4.17.4 Interrupts........................................................................................................................... 51 4.17.5 JTAG Interface ................................................................................................................. 52 4.17.6 UART Interface ................................................................................................................ 52 4.17.7 DDC2Bi Interface ............................................................................................................. 52 4.17.8 General Purpose Inputs and Outputs (GPIO).................................................................... 52

4.18 Bootstrap Configuration Pins................................................................................................... 54 4.19 Host Register Interface............................................................................................................. 56



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4.9.1 读颜色Flash调整 4.9.2 颜色标准化和RGB支持 4.9.3 可变缩放比例 4.9.4 行和场收缩 4.9.5 4.9.6反转

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4.14 显示接口 4.14.1 显示同步 4.14.2 显示定时程序 4.14.3 传达LVDS 4.14.4 面板电源先后顺序 4.14.5 输出抖动

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主机寄存器界面



4.20 Miscellaneous Functions.......................................................................................................... 56 4.20.1 2-wire Master Serial Protocol ........................................................................................... 56 4.20.2 Power Down Operation .................................................................................................... 57 4.20.3 Pulse Width Modulation (PWM) Backlight Control ........................................................ 57 4.20.4 Low Bandwidth ADC ....................................................................................................... 57 4.20.5 Infrared receivers .............................................................................................................. 57

5. Electrical Specifications ................................................................................................................... 58 5.1 Preliminary DC Characteristics ................................................................................................. 58 5.2 Preliminary AC Characteristics ................................................................................................. 60

6. Ordering Information ....................................................................................................................... 66

7. Mechanical Specifications................................................................................................................ 67

8. Solder Reflow Profiles ..................................................................................................................... 68



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4.20 各种功能

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5 电气规格 5.1 备用DC特性 5.2 备用AC特性


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机械规格


List Of Tables

Table 1. Analog Input Port........................................................................................................ 5 Table 2. DVI Input Port ............................................................................................................ 5 Table 3. Low Bandwidth ADC Port.......................................................................................... 6 Table 4. OCM Port Address Bus .............................................................................................. 6 Table 5. OCM Port Data Bus .................................................................................................... 8 Table 6. OCM Port Control Signals.......................................................................................... 8 Table 7. Standard Definition Video Port .................................................................................. 9 Table 8. Video Port ................................................................................................................. 10 Table 9. Display Port Controls................................................................................................ 12 Table 10. Display Port .............................................................................................................. 12 Table 11. Display Port Power ................................................................................................... 16 Table 12. Clock Synthesis and Power....................................................................................... 16 Table 13. System....................................................................................................................... 17 Table 14. Frame Store DDR Interface ...................................................................................... 17 Table 15. Digital Power Supply................................................................................................ 19 Table 16. No Connection .......................................................................................................... 20 Table 17. TCLK Specification .................................................................................................. 25 Table 18. Pin Connection for RGB Input with HSYNC/VSYNC ............................................ 29 Table 19. ADC Characteristics ................................................................................................. 30 Table 20. DVI Receiver Characteristics.................................................................................... 32 Table 21. gm1601 GPIs and Alternate Functions ..................................................................... 53 Table 22. gm1601 GPIOs and Alternate Functions .................................................................. 53 Table 23. Bootstrap Signals ...................................................................................................... 55 Table 24. Absolute Maximum Ratings ..................................................................................... 58 Table 25. DC Characteristics .................................................................................................... 59 Table 26. Maximum Speed of Operation.................................................................................. 60 Table 27. 2-Wire Interface Port Timing.................................................................................... 60 Table 28. 24-bit VPORT Timing .............................................................................................. 61 Table 29. SVPORT Timing ...................................................................................................... 61 Table 30. DPORT Timing......................................................................................................... 62 Table 31. OCM PORT (On-chip Turbo186 as Bus Master) .................................................... 63 Table 32. DDR Interface Write Timing .................................................................................... 64 Table 33. DDR Interface Read Timing..................................................................................... 65



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List Of Figures

Figure 1. gm1601 System Design Example ............................................................................... 1 Figure 2. gm1601 Pin out Diagram............................................................................................ 4 Figure 3. gm1601 Functional Block Diagram.......................................................................... 21 Figure 4. Using the Internal Oscillator with External Crystal.................................................. 23 Figure 5. Internal Oscillator Output ......................................................................................... 24 Figure 6. Sources of Parasitic Capacitance .............................................................................. 24 Figure 7. Using an External Single-ended Clock Oscillator .................................................... 25 Figure 8. Internally Synthesized Clocks................................................................................... 27 Figure 9. Example ADC Signal Terminations ......................................................................... 29 Figure 10. gm1601 Clock Recovery........................................................................................... 30 Figure 11. ADC Capture Window.............................................................................................. 31 Figure 12. ITU-R BT656 Input .................................................................................................. 33 Figure 13. 8-bit 4:2:2 YCbCr/YPbPr ......................................................................................... 33 Figure 14. 16-bit 4:2:2 YCbCr/YPbPr ....................................................................................... 33 Figure 15. 24-bit 4:4:4 YCbCr/YPbPr ....................................................................................... 34 Figure 16. 24-bit RGB................................................................................................................ 34 Figure 17. Some Examples of gm1601 Built-in Test Patterns ................................................... 35 Figure 18. Factory Calibration and Test Environment ............................................................... 35 Figure 19. HSYNC Delay .......................................................................................................... 36 Figure 20. Active Data Crosses HSYNC Boundary................................................................... 36 Figure 21. ODD/EVEN Field Detection .................................................................................... 37 Figure 22. RealColor® Digital Color Controls ........................................................................... 39 Figure 23. Inverse 3:2 Pulldown Processing .............................................................................. 41 Figure 24. Display Windows and Timing .................................................................................. 46 Figure 25. Single Pixel Width Display Data .............................................................................. 46 Figure 26. Double Pixel Wide Display Data .............................................................................. 47 Figure 27. LVDS Signal Sequencing ......................................................................................... 47 Figure 28. Panel Power Sequencing........................................................................................... 48 Figure 29. OCM External Master and Normal Configurations.................................................. 50 Figure 30. Programming the OCM in normal Configuration..................................................... 51 Figure 31. 2-Wire Protocol Data Transfer.................................................................................. 56 Figure 32. 24-bit VPORT Timing .............................................................................................. 61 Figure 33. SVPORT Timing ...................................................................................................... 61 Figure 34. DPORT Timing......................................................................................................... 62 Figure 35. OCM PORT (On-chip Turbo186 as Bus Master) .................................................... 62 Figure 36. Frame store Write Timing......................................................................................... 64 Figure 37. Frame store Read Timing.......................................................................................... 65 Figure 38. gm1601 416 PBGA Mechanical Drawing ............................................................... 67 Figure 39. gm1601 416 PBGA Solder Reflow Profile (Non-Lead-Free) ................................. 68 Figure 40. gm1601-LF 416 PBGA Solder Reflow Profile (Lead-Free).................................... 69



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1. OVERVIEW

The gm1601 is a dual channel graphics and video processing IC for Liquid Crystal Display (LCD) monitors and televisions incorporating Picture in Picture, up to WUXGA output resolutions. The gm1601 provides all key IC functions required for image capture, processing and display timing control. On-chip functions include a high-speed triple-ADC and PLL, Ultra-Reliable DVI® receiver, high quality zoom and shrink scaling engines, Motion adaptive De-interlacing, Low-angle diagonal processing, an on-screen display (OSD) controller, a 100MHz on-chip X186 micro-controller (OCM), and a selectable double wide TTL or dual channel LVDS transmitter for interface to displays. With all these functions integrated onto a single device, the gm1601 eliminates the need for several system components, simplifying the design and reducing the cost of high-end multimedia LCD monitors and televisions while maintaining a high degree of flexibility and quality.

11..11 AApppplliiccaattiioonnss

•

•

Multi-media LCD monitors up to WUXGA resolutions

LCD, PDP and Rear Projection TV at WXGA, UXGA, WUXGA and HD(720P & 1080P) resolutions

11..22 ggmm11660011 SSyysstteemm DDeessiiggnn EExxaammppllee

Figure 1 below shows a typical high resolution multi-media LCD monitor/TV system based on the gm1601. Designs based on the gm1601 have reduced system cost, simplified hardware and firmware design and increased reliability because only a minimal number of components are required in the system.

PPWR, PBias

PWM

YpbPr

HDTV

ADC (optional)

Keypad

2 Wire Serial

IR IR

DDR Frame Buffer

2/4/8 M x 32bit

Composite/S-Video

Video Decoder

Back-light

Display

gm1601

Flash/ROM

Analog RGB

DVI

NVRAM

Figure 1. gm1601 System Design Example



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FEATURES • Zoom and shrink scaling • Integrated 8-bit triple-channel ADC / PLL • Integrated Ultra-Reliable DVI® 1.0-compliant receiver • On-chip LVDS transmitter (supports DC balanced mode) • Embedded X186 microcontroller with parallel ROM interface • On-chip versatile OSD engine • Picture in Picture, Graphics on Video, Video on Graphics, split

screen • All system clocks synthesized from a single external crystal • Programmable gamma correction (CLUT) • RealColor® controls provide sRGB compliance • PWM back light intensity control • 3 channel low bandwidth ADC • 5 Volt tolerant inputs • Low EMI and power saving features • Dual Infra-red inputs supporting various remote controls • 32-bit frame store DDR memory interface • Horizontal and Vertical flip of display image

• High-Quality Video Processing • Motion Adaptive De-interlacing up to 1080i on a per-

pixel basis • Motion Adaptive Noise Reduction • Inverse 3:2/2:2 pull down for Film Mode detection • Low Angle Diagonal processing

• High-Quality Advanced Scaling

• Fully programmable zoom ratios • High-quality shrink capability from WUXGA resolution • Moire cancellation • Non-linear scaling for aspect ratio conversion of video

• Analog RGB Input Port • Capturing up to 165MHz (up to UXGA 60Hz and

WUXGA 60Hz reduced blanking) • Captures RGB and Component YPbPr

• Ultra-Reliable DVI® Compliant Input Port • Capturing up to 165 MHz (up to UXGA 60Hz / WUXGA

60Hz reduced blanking) • Direct connect to all DVI compliant digital transmitters

• Digital Video/Graphics Input Port

• 4:4:4/4:2:2/CCIR656/601 8/16/24 bit digital video input port

• Additional CCIR656 digital video input port • Accepts video and graphics data

• RealColor® Technology • Digital brightness and contrast controls • TV color controls including hue and saturation controls • Flesh-tone adjustment • sRGB compliance allows end-users to experience the

same colors as viewed on CRTs and other displays

• On-chip OSD Controller • 12 True color bitmap tiles • 1, 2, 4 and 8-bit per pixel • Horizontal and vertical stretch of OSD menus • Blinking, transparency and blending

• On-chip Micro-controller • Requires no external micro-controller • External parallel ROM interface allows firmware customization

with little additional cost • General-purpose inputs/outputs (GPIOs) available for managing

system devices (keypad, backlight, NVRAM, etc)

• Integrated LVDS Transmitter • Eliminates the need for an external LVDS transmitters thereby

reducing system cost • Fully assignable signal combinations for LVDS output to be able to

interface to any panel data sequence standard

• Programmable TTL or LVDS Output Format • Single / double wide outputs (30/60 or 24/48 bit) up to

WUXGA 60Hz with reduced blanking • Support for 10, 8 or 6-bit display devices (with high-quality

dithering)

• Auto-Configuration / Auto-Detection • Input format detection • Phase and image positioning

• Highly Integrated System-on-a-Chip Reduces Component Count for a Highly Cost Effective Solution

• Integrated X186 processor with default APIs enable quick time to market, minimal software development

• Package 416PBGA



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2. GM1601 PINOUT

The gm1601 is available in a 416-ball Plastic Ball Grid Array (PBGA) package. Figure 2 provides the pin locations for all signals. (Viewed from top of package).

A NC ADC_3.3 ADC_1.8 ADC_1.8 ADC_DGND RXC+ DVI_GND RX0+ RX1+ RX2+ DVI_GND LBADC_IN3 D_GND

B BLUE- BLUE+ ADC_3.3 ADC_DGND DVI_GND RXC- DVI_GND RX0- RX1- RX2- REXT LBADC_IN2 D_GND

C GREEN- GREEN+ SOG ADC_AGND NC DVI_3.3 DVI_GND DVI_3.3 DVI_3.3 DVI_3.3 DVI_3.3 LBADC_IN1 LBADC_33

D RED- RED+ ADC_3.3 ADC_AGND NC DVI_1.8 DVI_GND DVI_1.8 DVI_1.8 DVI_1.8 DVI_GND LBADC_RETURN LBADC_GND

E ADC_AGND ADC_AGND ADC_3.3 ADC_AGND

F NC VDDD33_ PLL

VSSA33_ RPLL

VDDA33_ RPLL

G VDDA33_ FPLL

VSSD33_ PLL TCLK XTAL

H VDDD33_ SDDS

VSSA33_ SDDS

VDDA33_ SDDS

VSSA33_ FPLL

J VDDD33_ DDDS

VSSA33_ DDDS

VDDA33_ DDDS

VSSD33_ SDDS

K RESETn ACS_ RSET_HD NC VSSD33_

DDDS CORE_1.8 CORE_1.8 D_GND D_GND

L OCM_INT2 OCM_INT1 AVSYNC AHSYNC D_GND CORE_1.8 D_GND D_GND

M OCM_UDO OCM_UDI IR0 IR1 D_GND D_GND D_GND D_GND

N VGA_SDA VGA_SCL DVI_SDA DVI_SCL D_GND D_GND D_GND D_GND

P OCM_CS1n OCM_CS2n MSTR_SDA MSTR_SCL D_GND D_GND D_GND D_GND

R ROM_CSn OCM_REn OCM_WEn EXTCLK D_GND D_GND D_GND D_GND

T OCMADDR17

OCMADDR18

OCMADDR19 OCM_CS0n D_GND CORE_1.8 D_GND D_GND

U OCMADDR13

OCMADDR14

OCMADDR15

OCMADDR16

CORE_1.8 CORE_1.8 D_GND D_GND

V OCMADDR9

OCMADDR10

OCMADDR11

OCMADDR12

W OCMADDR6

OCMADDR7

OCMADDR8 IO_3.3

Y OCMADDR3

OCMADDR4

OCMADDR5 IO_3.3

AA OCMADDR0

OCMADDR1

OCMADDR2 IO_3.3

AB OCMDATA13 OCMDATA14 OCMDATA15 IO_3.3

AC OCMDATA10 OCMDATA11 OCMDATA12 IO_3.3 GPIO_G09_ B2(DEGRN0)

IO_3.3 DCLK IO_3.3 GPIO_G07_ B2(DERED4)

IO_3.3 SHIELD[1](DEGRN3)

LVDSB_3.3 LVDSB_GND

AD OCMDATA9 OCMDATA6 OCMDATA3 OCMDATA0 GPIO_G09_ B3(DEGRN1)

GPIO_G08_ B0(DORED0)

DEN GPIO_G08_ B5(DOBLU1)

GPIO_G07_ B3(DERED5)

GPIO_G07_ B6 (DERED8)

SHIELD[2](DEGRN4)

LVDSB_3.3 LVDSB_3.3

AE OCMDATA8 OCMDATA5 OCMDATA2 GPIO_G09_ B0 (DERED0)

GPIO_G09_ B4(DEBLU0)

GPIO_G08_ B1(DORED1)

GPIO_G08_ B3(DOGRN1)



GPIO_G07_ B7 (DERED9)

SHIELD[3](DEGRN5)

BC+ (DEGRN8)

SHIELD[4](DEBLU2)

AF OCMDATA7 OCMDATA4 OCMDATA1 GPIO_G09_ B1 (DERED1)

GPIO_G09_ B5(DEBLU1)


GPIO_G08_ B4(DOBLU0)



SHIELD[0] (DEGRN2)

B3+ (DEGRN6)

B3- (DEGRN7)

BC- (DEGRN9)

1 2 3 4 5 6 7 8 9 10 11 12 13



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SVODD SVDATA6 SVDATA2 SVDV VRED6 VRED2 VCLK VGRN7 VGRN3 VGRN0 VBLU5 VBLU1 PPWR A

SVVSYNC SVDATA5 SVDATA1 VCLAMP VRED5 VRED1 VODD VGRN6 VGRN2 VBLU7 VBLU4 VBLU0 PBIAS B

SVHSYNC SVDATA4 SVDATA0 VRED7 VRED4 VRED0 VVS VGRN5 VGRN1 VBLU6 VBLU3 PWM1 PWM0 C

SVDATA7 SVDATA3 SVCLK IO_3.3 VRED3 VHS_CSYNC VDV VGRN4 IO_3.3 IO_3.3 VBLU2 OCM_ TIMER1

PWM2 D

FS_2.5 FSDATA0 FSDATA1 FSDATA2 E

FS_2.5 FSDATA29 FSDATA30 FSDATA31 F

FSDATA27 FSDATA4 FSDATA28 FSDATA3 G

FS_2.5 FSDATA6 FSDATA26 FSDATA5 H

FS_2.5 FSVREF FSDATA7 FSDATA25 J

D_GND D_GND CORE_1.8 CORE_1.8 VDDA18_ DLL

FSDATA24 VSSA18_DLL

FSVREFVSS K

D_GND D_GND CORE_1.8 D_GND FS_2.5 FSDATA15 FSDATA16 FSDQS L

D_GND D_GND D_GND D_GND FS_2.5 FSDATA18 FSDATA14 FSDATA17 M

D_GND D_GND D_GND D_GND FSDATA20 FSDATA12 FSDATA19 FSDATA13 N

D_GND D_GND D_GND D_GND FS_2.5 FSDATA10 FSDATA21 FSDATA11 P

D_GND D_GND D_GND D_GND FS_2.5 FSDATA23 FSDATA9 FSDATA22 R

D_GND D_GND CORE_1.8 CORE_1.8 FS_2.5 FSDQM3 FSDQM0 FSDATA8 T

D_GND D_GND CORE_1.8 CORE_1.8 FSCLKn FSCLKp FSDQM1 FSDQM2 U

FS_2.5 FSRAS FSCAS FSWE V

FS_2.5 FSVREFVSS FSVREF FSCKE W

FS_2.5 FSADDR8 FSBKSEL0 FSBKSEL1 Y

FS_2.5 FSADDR5 FSADDR6 FSADDR7 AA

FS_2.5 FSADDR11 FSADDR9 FSADDR4 AB

LVDSB_GND LVDSB_GND OEXTR NC GPIO_G06_ B0 (DORED2)

LVDSA_GND LVDSA_GND LVDSA_3.3 LVDSA_3.3 FS_2.5 FSADDR2 FSADDR3 FSADDR10 AC

SHIELD[5] (DEBLU5)

D_GND DVS VSSD33_ LVDS

GPIO_G06_ B1 (DORED3)

LVDSA_GND LVDSA_3.3 GPIO_G05_ B0(DOGRN2)


GPIO_G04_ B0 (DOBLU2)


FSADDR0 FSADDR1 AD

B2- (DEBLU4)

B1- (DEBLU7)

B0- (DEBLU9)

VDDD33_ LVDS

GPIO_G06_ B2 (DORED4)

A3+ (DORED6)

AC+ (DORED8)

A2+ (DOGRN3)

A1+ (DOGRN6)

A0+ (DOGRN8)




AE

B2+ (DEBLU3)

B1+ (DEBLU6)

B0+ (DEBLU)

DHS GPIO_G06_ B3 (DORED5)

A3- (DORED7)

AC- (DORED9)

A2- (DOGRN4)

A1- (DOGRN7)

A0- (DOGRN9)



GPIO_G04_ B5(DOBLU 7)

AF

14 15 16 17 18 19 20 21 22 23 24 25 26

Figure 2. gm1601 Pin out Diagram



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3. GM1601 PIN LIST

I/O Legend: A = Analog, I = Input, O = Output, P = Power, G= Ground

Table 1. Analog Input Port Pin Name I/O Ball # Description

AVSYNC I L3 ADC input vertical sync.

AHSYNC I L4 ADC input horizontal sync or composite sync input.

VGA_SCL

(GPI_05)

I N2 DDC Interface for DDC2Bi communication from a VGA connector. Serial clock signal.

Can also be programmed as a General Purpose Input, GPI_05.

VGA_SDA

(GPI_06)

I/O N1 DDC Interface for DDC2Bi communication from a VGA connector. Serial data signal.


RED+ AI D2 Positive analog input for red channel.

RED- AI D1 Negative analog input for red channel.

SOG AI C3 Sync on green slicer input for green channel. SOG must be AC coupled through series capacitor to the green analog input.

GREEN+ AI C2 Positive analog input for green channel.

GREEN- AI C1 Negative analog input for green channel.

BLUE+ AI B2 Positive analog input for blue channel.

BLUE- AI B1 Negative analog input for blue channel.

ADC_3.3 AP A2, D3, E3, B3

Analog power (3.3V) for ADC (4 pins)

ADC_1.8 AP A3, A4 Analog power (1.8V) for ADC. (2 pins)

ADC_DGND AG A5, B4 Digital ground for ADC. (2 pins)

ADC_AGND AG C4, D4, E1, E2, E4

Analog ground for ADC. (5 pins)

Table 2. DVI Input Port Pin Name I/O Ball # Description

DVI_SCL

(GPI_07)

I N4 DDC Interface for DDC2Bi communication from a DVI connector. Serial clock input signal.


DVI_SDA

(GPI_08)

I/O N3 DDC Interface for DDC2Bi communication from a DVI connector. Serial data signal.


RXC+ AI A6 DVI clock input pair.

RXC- AI B6 DVI clock input pair.

RX0+ AI A8 DVI input pair 0.

RX0- AI B8 DVI input pair 0.







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Pin Name I/O Ball # Description

REXT AI B11 External termination resistor. A 1% 250 ohm resistor must be connected from this pin to DVI_3.3

DVI_3.3 AP C6, C8, C9, C10, C11

Analog VDD (3.3V) for DVI receiver. (5 pins)

DVI_1.8 AP D6, D8, D9, D10

Digital VDD (1.8V) for DVI receiver. (4 pins)

DVI_GND AG A7, A11, B5, B7, C7, D7, D11

Analog ground for DVI receiver. (7 pins)

Table 3. Low Bandwidth ADC Port Pin Name I/O Ball # Description

LBADC_33 AP C13 Analog VDD (3.3V) for low bandwidth ADC

LBADC_IN1 AI C12 Analog input channel 1 for low bandwidth ADC

LBADC_IN2 AI B12 Analog input channel 2 for low bandwidth ADC

LBADC_IN3 AI A12 Analog input channel 3 for low bandwidth ADC

LBADC_RETURN AI D12 Analog ground (signal return path) for channels 1, 2, and 3 of low bandwidth ADC

LBADC_GND AG D13 Analog ground for low bandwidth ADC power supply

Table 4. OCM Port Address Bus Pin Name I/O Ball # Description

OCMADDR19

(GPIO_22)

I/O T3 Address output during normal 8 bit or 16 bit mode.

Can be programmed as GPIO_22.

Also used as bootstrap input to control data bus width to external peripherals

OCMADDR18

(GPIO_21)


Can be programmed as GPIO_21

Also used as bootstrap input to control data bus width to external peripherals.

OCMADDR17

(GPIO_20)



Also used as bootstrap input to control data bus width to external peripherals.

OCMADDR16

(GPIO_19)

I/O U4 Address output during normal 8 bit or 16 bit mode.


Also used as bootstrap input to control oscillator selection.

OCMADDR15

(GPIO_G11_B7)


Can be programmed as GPIO_GROUP_11 [bit 7].

Also used as bootstrap input to control in-circuit debugger options.

OCMADDR14

(GPIO_G11_B6)


Can be programmed as GPIO_GROUP_11[bit 6]


OCMADDR13 I/O U1 Address output during normal 8 bit or 16 bit mode.



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外部外围设备




(GPIO_G11_B5) Can be programmed as GPIO_GROUP_11[bit 5]


OCMADDR12

(GPIO_G11_B4)

I/O V4 Address output during normal 8 bit or 16 bit mode.

Can be programmed as GPIO_GROUP11[bit 4]

Also used as bootstrap input to control display characteristics during power-on reset.

OCMADDR11

(GPIO_G11_B3)



Also used as bootstrap input to control display characteristics during power-on reset.

OCMADDR10

(GPIO_G11_B2)



Also used as bootstrap input to control location of clock source.

OCMADDR9

(GPIO_G11_B1)



Also used as bootstrap input – user configuration.

OCMADDR8

(GPIO_G11_B0)

I/O W3 Address output during normal 8 bit or 16 bit mode.



OCMADDR7

(GPIO_18)

I/O W2 Address output during normal 8 bit or 16 bit mode.



OCMADDR6 I/O W1 Address output during normal 8 bit or 16 bit mode.


OCMADDR5 I/O Y3 Address output during normal 8 bit or 16 bit mode.






OCMADDR2 I/O AA3 Address output during normal 8 bit or 16 bit mode.


OCMADDR1 I/O AA2 Address output during normal 8 bit or 16 bit mode.


OCMADDR0 I/O AA1 Address output during normal 8bit mode. Not used during normal 16 bit mode since all external accesses are treated as 16 bit transfer.


** Note: All 20 bits of the OCMADDR[19:0] bus are used as bootstrapped inputs and cannot be left floating. See Section 4.18



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地址正常输出模式为8位或16位。

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同样使用引导输入控制显示器特有的高电平复位？

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时钟源位置

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同样使用引导输入用户配置。



Table 5. OCM Port Data Bus Pin Name I/O Ball # Description

OCMDATA15

(GPIO_G10_B7)

I/O AB3 Data bus controlled by on chip turbo186 processor. Unused in 8 bit mode.

Can be programmed as GPIO_GROUP_10 bit7.

OCMDATA14

(GPIO_G10_B6)



OCMDATA13

(GPIO_G10_B5)



OCMDATA12

(GPIO_G10_B4)

I/O AC3 Data bus controlled by on chip turbo186 processor. Unused in 8 bit mode.


OCMDATA11

(GPIO_G10_B3)



OCMDATA10

(GPIO_G10_B2)



OCMDATA9

(GPIO_G10_B1)

I/O AD1 Data bus controlled by on chip turbo186 processor. Unused in 8 bit mode.


OCMDATA8

(GPIO_G10_B0)

I/O AE1 Data bus controlled by on chip turbo186 processor. Unused in 8 bit mode.


OCMDATA7 I/O AF1 Data bus controlled by on chip turbo186 processor.

OCMDATA6 I/O AD2 Data bus controlled by on chip turbo186 processor.

OCMDATA5 I/O AE2 Data bus controlled by on chip turbo186 processor.



OCMDATA2 I/O AE3 Data bus controlled by on chip turbo186 processor.



Table 6. OCM Port Control Signals Pin Name I/O Ball # Description

ROM_CSn

(GPI_09)

I/O R1 Chip select output signal to external ROM.

Can be programmed as GPI read only (GPI_9).

OCM_CS0n

(GPIO_23)

I/O T4 Chip select output signal to external peripheral. Can be used to access larger address space for optional external ram.


OCM_CS1n

(GPIO_24)

I/O P1 Chip select output signal to external peripheral.


OCM_CS2n

(GPIO_25)

I/O P2 Chip select output signal to external peripheral.


OCM_REn I/O R2 Read enable output signal to enable external device to drive data pins

OCM_WEn I/O R3 Write enable output signal to enable writing to external devices.

OCM_INT2

(GPI_10)

I/O L1 Interrupt #2 input for generating system interrupt to OCM.

Can be programmed as GPI_10.



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数据总线用芯片186处理器约束，未使用8位模式，能够用GPIO_GROUP_10bit7编程

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芯片选择外部ROM信号输出。

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芯片选择外部外围设备输出信号，能够使用大量地址空间选择外部RAM

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读取使能输出信号，使能外部设备驱动数据管脚。




OCM_INT1

(GPIO_30)

I/O L2 Interrupt #1 input for generating system interrupt to OCM.


OCM_UDO

(GPIO_26)

I/O M1 OCM UART data output.


OCM_UDI

(GPIO_27)

I/O M2 OCM UART data input.


OCM_TIMER1

(GPIO_13)

(PWM3)

I/O D25 Timer In: used as clock or clock enable input to OCMTIMER1


Can also be programmed as pulse width modulated output: PWM3.

Table 7. Standard Definition Video Port Pin Name I/O Ball # Description

SVCLK

(GPI_00)

I D16 Pixel clock input for SV Port.

Can also be programmed as GPI_0.

SVODD

(GPIO_00)

I/O A14 Field status input for interlaced sources driving SV Port.

Can also be programmed as GPIO_00.

SVVSYNC

(GPIO_01)

I/O B14 VSYNC input for SV Port.


SVHSYNC

(GPIO_02)

I/O C14 HSYNC input for SV Port.


SVDV

(GPIO_03)

(VCOAST)

I/O A17 Data Valid input for SV Port, used as a qualifier for valid pixel samples.


Can be programmed to become part of the VPORT interface to output a coast signal to “coast” external PLL during the VSYNC region.

SVDATA7

(GPIO_G00_B7)

I/O D14 ITU 656 data input for SV Port. Y input when SV Port is enabled for 16 bit mode.

Can also be programmed as GPIO_GROUP_00 bit 7.

SVDATA6

(GPIO_G00_B6)

I/O A15 ITU 656 data input for SV Port. Y input when SV Port is enabled for 16 bit mode.


SVDATA5

(GPIO_G00_B5)

I/O B15 ITU 656 data input for SV Port. Y input when SV Port is enabled for 16 bit mode.


SVDATA4

(GPIO_G00_B4)

I/O C15 ITU 656 data input for SV Port. Y input when SV Port is enabled for 16 bit mode.


SVDATA3

(GPIO_G00_B3)

I/O D15 ITU 656 data input for SV Port. Y input when SV Port is enabled for 16 bit mode.


SVDATA2

(GPIO_G00_B2)

I/O A16 ITU 656 data input for SV Port. Y input when SV Port is enabled for 16 bit mode.


SVDATA1

(GPIO_G00_B1)

I/O B16 ITU 656 data input for SV Port. Y input when SV Port is enabled for 16 bit mode.


SVDATA0

(GPIO_G00_B0)

I/O C16 ITU 656 data input for SV Port. Y input when SV Port is enabled for 16 bit mode.




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有效数据输入SV管脚


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能够对管脚编程，通过VPORT接口输出

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标准定义视频接口


** Note: Software programming allows the bit sequence [7:0] to be reversed in the system design to simplify PCB layout. The SVDATA bus may also be combined with 8-bits from the Video Port to form a 16-bit input port. In this 16-bit mode, the SVDATA bus must contain the Y data channel.

Table 8. Video Port Pin Name I/O Ball # Description

VCLK

(GPI_01)

I A20 Pixel clock input for V Port.

Can be programmed as GPI_01.

VHS_CSYNC

(GPIO_04)

I/O D19 HSYNC input for V Port. This represent the HSYNC signal used to recover the pixel clock when an external ADC drives the V Port.

Can also be programmed as GPIO_O4.

VVS

(GPIO_05)

I/O C20 VSYNC input for VPort. When using an external ADC to drive the V Port then drive this input with a separate digital VSYNC (if available).


VODD

(GPIO_06)

(HSOUT)

I/O B20 Field status input for V port when input source is interlaced.


Can also be used to output the separated HSYNC signal as a reference to an external PLL for digitizing pixel clock.

VDV

(GPIO_07)

(VSOG)

I/O D20 Data valid input for V Port, used as a qualifier for valid pixel samples.


When using an external ADC to interface with the V Port, this pin may be used to input the sliced sync-on-green (SOG) signal.

VCLAMP

(GPIO_31)

I/O B17 Clamp enable output for V Port to control back porch clamping for an external ADC which interfaces with the V Port.


VRED7

(GPIO_G01_B7)

I/O C17 Red or V/Cr/Pr pixel data input.

Can be programmed as a GPIO using GPIO_GROUP_01 bit 7.

VRED6

(GPIO_G01_B6)

I/O A18 Red or V/Cr/Pr pixel data input.


VRED5

(GPIO_G01_B5)

I/O B18 Red or V/Cr/Pr pixel data input.


VRED4

(GPIO_G01_B4)



VRED3

(GPIO_G01_B3)

I/O D18 Red or V/Cr/Pr pixel data input.


VRED2

(GPIO_G01_B2)

I/O A19 Red or V/Cr/Pr pixel data input.


VRED1

(GPIO_G01_B1)

I/O B19 Red or V/Cr/Pr pixel data input.


VRED0

(GPIO_G01_B0)



VGRN7 I/O A21 Green or Y pixel data input.



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SVDTAT总线可能也是8位宽度组合，视频管脚到16输入管脚。这是16位模式，SVDATA总线必须包含Y数据信道。



(GPIO_G02_B7) Can be programmed as a GPIO using GPIO_GROUP_02 bit 7.

VGRN6

(GPIO_G02_B6)

I/O B21 Green or Y pixel data input.


VGRN5

(GPIO_G02_B5)

I/O C21 Green or Y pixel data input.


VGRN4

(GPIO_G02_B4)

I/O D21 Green or Y pixel data input.


VGRN3

(GPIO_G02_B3)

I/O A22 Green or Y pixel data input.


VGRN2

(GPIO_G02_B2)

I/O B22 Green or Y pixel data input.


VGRN1

(GPIO_G02_B1)

I/O C22 Green or Y pixel data input.


VGRN0

(GPIO_G02_B0)

I/O A23 Green or Y pixel data input.


VBLU7

(GPIO_G03_B7)

I/O B23 Blue or U/Cb/Pb pixel data input.


VBLU6

(GPIO_G03_B6)

I/O C23 Blue or U/Cb/Pb pixel data input.


VBLU5

(GPIO_G03_B5)

I/O A24 Blue or U/Cb/Pb pixel data input.


VBLU4

(GPIO_G03_B4)



VBLU3

(GPIO_G03_B3)

I/O C24 Blue or U/Cb/Pb pixel data input.


VBLU2

(GPIO_G03_B2)

I/O D24 Blue or U/Cb/Pb pixel data input.


VBLU1

(GPIO_G03_B1)

I/O A25 Blue or U/Cb/Pb pixel data input.


VBLU0

(GPIO_G03_B0)



** Note: Software programming allows the bit sequence [7:0] to be reversed in the system design to simplify PCB layout. Software programming also allows Red/Green/Blue channel sequencing to be arbitrarily mapped (e.g., Blue/Green/Red) to simplify system layout.

** Note: 8-bits from the VPORT may be allocated to the SVPORT to form a resulting 16-bit port.



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Table 9. Display Port Controls Pin Name I/O Ball # Description

PPWR

(GPIO_08)

O A26 Panel Power Control output controlled by Panel Power On Sequencer (see PANEL_POWER_STATUS and PANEL_POWER_TIMING programmable host registers.)

Can be programmed as a GPIO (output only) referenced as GPIO_08.

PBIAS

(GPIO_09)

O B26 Panel Bias Control (Backlight Enable) controlled by Panel Power On Sequencer (see PANEL_POWER_STATUS and PANEL_POWER_TIMING programmable host registers.)

Can be programmed as a GPIO (output only) referenced as GPIO_09.

PWM0

(GPIO_10)

I/O C26 Pulse Width Modulated output.


PWM1

(GPIO_11)

I/O C25 Pulse Width Modulated output.


PWM2

(GPIO_12)

I/O D26 Pulse Width Modulated output.


DHS

(GPIO_14)

I/O AF17 Display output H-sync.

Can be programmed as GPIO_14. Default driven low.

DVS

(GPIO_15)

I/O AD16 Display output V-sync.


DEN

(GPIO_16)

I/O AD7 Display output data enable.


DCLK

(GPIO_17)

I/O AC7 Panel output pixel clock. Clock rate matches the pixel rate for single wide output mode and pixel rate divided by 2 for double wide output mode.


OEXTR AI AC16 External LVDS bias resistor. Connect this pin through 3.4K resistor to LVDSB_GND.

Table 10. Display Port Pin Name I/O Ball # Description

A0-

(DOGRN9)

(GPIO_G05_B7)

AO AF23 Display port LVDS channel A0 negative.

Display port LVTTL green data, odd pixels.

Available as GPIO (output only) in single wide mode TTL/LVDS

A0+

(DOGRN8)

(GPIO_G05_B6)

AO AE23 Display port LVDS channel A0 positive.



A1-

(DOGRN7)

(GPIO_G05_B5)




A1+

(DOGRN6)

(GPIO_G05_B4)




A2-

(DOGRN4)

(GPIO_G05_B2)






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A2+

(DOGRN3)

(GPIO_G05_B1)




A3-

(DORED7)

(GPIO_G06_B5)


Display port LVTTL red data, odd pixels.


A3+

(DORED6)

(GPIO_G06_B4)




AC-

(DORED9)

(GPIO_G06_B7)

AO AF20 Display port LVDS channel A, clock negative signal.



AC+

(DORED8)

(GPIO_G06_B6)

AO AE20 Display port LVDS channel A, clock positive signal.



B0-

(DEBLU9)

AO AE16 Display port LVDS channel B0 negative.

Display port LVTTL blue data, even pixels.

BO+

(DEBLU8)

AO AF16 Display port LVDS channel B0 positive.


B1-

(DEBLU7)



B1+

(DEBLU6)



B2-

(DEBLU4)



B2+

(DEBLU3)



B3-

(DEGRN7)

AO AF12 Display port LVDS channel B3 negative.

Display port LVTTL green data, even pixels.

B3+

(DEGRN6)



BC-

(DEGRN9)

AO AF13 Display port LVDS channel B, clock negative signal.


BC+

(DEGRN8)

AO AE12 Display port LVDS channel B, clock positive signal.


SHIELD[5]

(DEBLU5)

O AD14 Display port LVDS shield 5 output controlled by LVDS_B_SHIELD host register.


SHIELD[4]

(DEBLU2)

O AE13 Display port LVDS shield 4 output controlled by LVDS_B_SHIELD host register.


SHIELD[3]

(DEGRN5)

O AE11 Display port LVDS shield 3 output controlled by LVDS_B_SHIELD host register.




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SHIELD[2]

(DEGRN4)

O AD11 Display port LVDS shield 2 output controlled by LVDS_B_SHIELD host register.


SHIELD[1]

(DEGRN3)

O AC11 Display port LVDS shield 1 output controlled by LVDS_B_SHIELD host register.


SHIELD[0]

(DEGRN2)

O AF10 Display port LVDS shield 0 output controlled by LVDS_B_SHIELD host register.


GPIO_G04_B7

(DOBLU9)

I/O AE26 Display port LVTTL blue data, odd pixels.

Can be enabled as GPIO_GROUP_04 bit 7 (can be configured as HiZ on power up using OCMADDR[12:11]).

GPIO_G04_B6

(DOBLU8)



GPIO_G04_B5

(DOBLU7)

I/O AF26 Display port LVTTL blue data, odd pixels.


GPIO_G04_B4

(DOBLU6)



GPIO_G04_B3

(DOBLU5)



GPIO_G04_B2

(DOBLU4)



GPIO_G04_B1

(DOBLU3)

I/O AD24 Display port LVTTL blue data, odd pixels.


GPIO_G04_B0

(DOBLU2)

I/O AD23 Display port LVTTL blue data, odd pixels.


GPIO_G05_B3

(DOGRN5)

I/O AD22 Display port LVTTL green data, odd pixels.


Available as GPIO_GROUP_05 bit 3 (can be configured as HiZ on power up using OCMADDR[12:11]) in single wide mode TTL only.

GPIO_G05_B0

(DOGRN2)

I/O AD21 Display port LVTTL green data, odd pixels.

Available as GPIO_GROUP_05 bit 0 (can be configured as HiZ on power up using OCMADDR[12:11]) in single wide mode TTL only.

GPIO_G06_B3

(DORED5)

I/O AF18 Display port LVTTL red data, odd pixels.


GPIO_G06_B2

(DORED4)

I/O AE18 Display port LVTTL red data, odd pixels.


GPIO_G06_B1

(DORED3)

I/O AD18 Display port LVTTL red data, odd pixels.




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(DORED2)

I/O AC18 Display port LVTTL red data, odd pixels.


GPIO_G07_B7

(DERED9)

I/O AE10 Display port LVTTL red data, even pixels.

Can be enabled as: GPIO_GROUP_07 bit 7 (can be configured as HiZ on power up using OCMADDR[12:11]).

GPIO_G07_B6

(DERED8)

I/O AD10 Display port LVTTL red data, even pixels.


GPIO_G07_B5

(DERED7)

I/O AF9 Display port LVTTL red data, even pixels.


GPIO_G07_B4

(DERED6)



GPIO_G07_B3

(DERED5)

I/O AD9 Display port LVTTL red data, even pixels.


GPIO_G07_B2

(DERED4)

I/O AC9 Display port LVTTL red data, even pixels.


GPIO_G07_B1

(DERED3)

I/O AF8 Display port LVTTL red data, even pixels.


GPIO_G07_B0

(DERED2)



GPIO_G08_B5

(DOBLU1)

(JTAG_RESET)

I/O AD8 Display port LVTTL blue data, odd pixels (in 10-bit output mode).

Can be enabled as GPIO_GROUP_08 bit5 (can be configured as HiZ on power up using OCMADDR[12:11]).

Can be enabled as JTAG_RESET signal for debug.

GPIO_G08_B4

(DOBLU0)

(JTAG_TDO)

I/O AF7 Display port LVTTL blue data, odd pixels (in 10-bit output mode).


Can be enabled as JTAG_TDO signal for debug.

GPIO_G08_B3

(DOGRN1)

(DVS)

I/O AE7 Display port LVTTL green data, odd pixels (in 10-bit output mode).


Can be enabled as DVS output.

GPIO_G08_B2

(DOGRN0)

(JTAG_TDI)

I/O AF6 Display port LVTTL green data, odd pixels (in 10-bit output mode).


Can be enabled as JTAG_TDI signal for debug.

GPIO_G08_B1

(DORED1)

(JTAG_MODE)

I/O AE6 Display port LVTTL red data, odd pixels (in 10-bit output mode).


Can be enabled as JTAG_MODE signal for debug.



GPIO_G08_B0

(DORED0)

(JTAG_CLK)

I/O AD6 Display port LVTTL red data, odd pixels (in 10-bit output mode).


Can be enabled as JTAG_CLK signal for debug.

GPIO_G09_B5

(DEBLU1)

I/O AF5 Display port LVTTL blue data, even pixels (in 10-bit output mode).

Can be enabled as: GPIO_GROUP_09 bit5 (can be configured as HiZ on power up using OCMADDR[12:11]).

GPIO_G09_B4

(DEBLU0)

I/O AE5 Display port LVTTL blue data, even pixels (in 10-bit output mode).


GPIO_G09_B3

(DEGRN1)

I/O AD5 Display port LVTTL green data, even pixels (in 10-bit output mode).


GPIO_G09_B2

(DEGRN0)

I/O AC5 Display port LVTTL green data, even pixels (in 10-bit output mode).


GPIO_G09_B1

(DERED1)

I/O AF4 Display port LVTTL red data, even pixels (in 10-bit output mode).


GPIO_G09_B0

(DERED0)

I/O AE4 Display port LVTTL red data, even pixels (in 10-bit output mode).


Table 11. Display Port Power Pin Name I/O Ball # Description

LVDSB_3.3 PWR AC12, AD12, AD13

3.3V power supply for LVDSB channel output drivers (3 pins)

LVDSB_GND GND AC13, AC14, AC15

Gnd return for LVDSB channel output drivers (3 pins)

LVDSA_3.3 PWR AC21, AC22, AD20

3.3V power supply for LVDSA channel output drivers (3 pins)

LVDSA_GND GND AC19, AC20, AD19

Gnd return for LVDSA channel output drivers (3 pins)

VDDD33_LVDS AP AE17 3.3V analog power supply to LVDS transmitter PLL

VSSD33_LVDS AG AD17 Analog GND return for LVDS transmitter PLL

Table 12. Clock Synthesis and Power Pin Name I/O Ball # Description

TCLK AI G3 Reference clock input for external crystal connection (14.318 MHz) or can be driven by external oscillator. Mode is controlled by bootstrap pin: OCMADDR16. (high = crystal, low = external oscillator)

XTAL AO G4 Crystal oscillator output. Connect crystal between TCLK pin and XTAL pin.

VDDD33_PLL F2 Digital 3.3V power supply for RCLK and Frame store clock PLL.

VSSD33_PLL G2 Digital ground for RCLK and Frame store clock PLL.



16

Administrator

Pencil



VDDA33_RPLL F4 Analog 3.3V power supply for RCLK PLL.

VSSA33_RPLL F3 Analog ground for RCLK PLL.

VDDA33_FPLL G1 Analog 3.3V power supply for Frame store clock PLL

VSSA33_FPLL H4 Analog ground for Frame store clock PLL

VDDD33_SDDS H1 Digital 3.3V power supply for SCLK PLL.

VSSD33_SDDS J4 Digital ground for SCLK PLL.

VDDA33_SDDS H3 Analog Power for SCLK PLL.

VSSA33_SDDS H2 Analog ground for SCLK PLL.

VDDD33_DDDS J1 Digital 3.3V power supply for DCLK PLL.

VSSD33_DDDS K4 Digital ground for DCLK PLL.

VDDA33_DDDS J3 Analog power for DCLK PLL.

VSSA33_DDDS J2 Analog ground for DCLK PLL.

ACS_RSET_HD K2 Connect a 3.3 K ohm resistor with 1% tolerance from this pin to ground.

Table 13. System Pin Name I/O Ball # Description

RESETn I K1 Hardware reset signal is active low.

IR1

(GPIO_28)

I M4 Infra red input to IR Decoder #2.


IR0

(GPIO_29)

I M3 Infra red input to IR Decoder #1.


MSTR_SCL

(GPI_03)

I/O P4 Master serial interface for communicating with external serial slave peripherals. Serial clock output signal.

Can be enabled as GPI_03 input.

MSTR_SDA

(GPI_04)

I/O P3 Master serial interface for communicating with external serial slave peripherals. Serial data I/O signal.

Can be enabled as GPI_04 input.

EXTCLK

(GPI_02)

I R4 External Clock input for test purposes.

Can be enabled as GPI_02.

Table 14. Frame Store DDR Interface Pin Name I/O Ball # Description

FSCLKp O U24 Differential frame store clock output (positive signal). SSTL2

FSCLKn O U23 Differential frame store clock output (negative signal). SSTL2

FSRAS O V24 Row address strobe output. SSTL2

FSCAS O V25 Column address strobe output. SSTL2

FSWE O V26 Write enable. SSTL2

FSCKE O W26 Clock enable. SSTL2

FSVREF AI J24, W25 Reference voltage for SSTL2 inputs. (2 pins)

FSVREFVSS AI K26, W24 Reference voltage return (ground) for SSTL2 inputs. (2 pins)

FSDQS I/O L26 Data strobe. Data input and outputs are synchronized with both edges of DQS. SSTL2



17



FSDATA31 I/O F26 Data input/output. SSTL2



FSDATA28 I/O G25 Data input/output. SSTL2


FSDATA26 I/O H25 Data input/output. SSTL2

FSDATA25 I/O J26 Data input/output. SSTL2

FSDATA24 I/O K24 Data input/output. SSTL2

FSDATA23 I/O R24 Data input/output. SSTL2


FSDATA21 I/O P25 Data input/output. SSTL2

FSDATA20 I/O N23 Data input/output. SSTL2


FSDATA18 I/O M24 Data input/output. SSTL2


FSDATA16 I/O L25 Data input/output. SSTL2

FSDATA15 I/O L24 Data input/output. SSTL2







FSDATA8 I/O T26 Data input/output. SSTL2

FSDATA7 I/O J25 Data input/output. SSTL2





FSDATA2 I/O E26 Data input/output. SSTL2



FSDQM3 O T24 Data out mask. Only used during write cycles. A logic ‘1’ indicates to external DDR memory that data on FSDATA[31:24] is not to be overwritten. SSTL2

FSDQM2 O U26 Data out mask. Only used during write cycles. A logic ‘1’ indicates to external DDR memory that data on FSDATA[23:16] is not to be overwritten. SSTL2

FSDQM1 O U25 Data out mask. Only used during write cycles. A logic ‘1’ indicates to external DDR memory that data on FSDATA[15:8] is not to be overwritten. SSTL2

FSDQM0 O T25 Data out mask. Only used during write cycles. A logic ‘1’ indicates to external DDR memory that data on FSDATA[7:0] is not to be overwritten. SSTL2

FSBKSEL1 O Y26 Bank select address. Together with FSBKSEL0 selects which of 4 banks is to be active. SSTL2



18



FSBKSEL0 O Y25 Bank select address. Together with FSBKSEL1 selects which of 4 banks is to be active. SSTL2

FSADDR11 O AB24 Row/Column addresses outputs multiplexed onto the same pins. SSTL2

FSADDR10 O AC26 Row/Column addresses outputs multiplexed onto the same pins. SSTL2


FSADDR8 O Y24 Row/Column addresses outputs multiplexed onto the same pins. SSTL2

FSADDR7 O AA26 Row/Column addresses outputs multiplexed onto the same pins. SSTL2






FSADDR1 O AD26 Row/Column addresses outputs multiplexed onto the same pins. SSTL2

FSADDR0 O AD25 Row/Column addresses outputs multiplexed onto the same pins. SSTL2

FS_2.5 E23, F23, H23, J23, L23, M23, P23, R23, T23, V23, W23, Y23, AA23, AB23, AC23

2.5v I/O power supply for SSTL2 I/O. (15 pins)

VDDA18_DLL K23 1.8V power supply for on chip DLL for DDR interface timing control.

VSSA18_DLL K25 Power supply return for on chip DLL.

Table 15. Digital Power Supply Pin Name I/O Ball # Description

CORE_1.8 K10, K11, K16, K17, L11, L16, T11, T16, T17, U10, U11, U16, U17

1.8V VDD for core supply. (13 pins)

IO_3.3 D17, D22, D23, W4, Y4, AA4, AB4, AC4, AC6, AC8, AC10

3.3V VDD for I/O. (11 pins)

D_GND A13, B13, K12, K13, K14, K15, L10, L12, L13, L14, L15, L17, M10, M11, M12, M13, M14, M15, M16, M17, N10, N11, N12, N13, N14,N15, N16, N17, P10, P11, P12, P13, P14, P15, P16, P17, R10, R11, R12, R13, R14, R15, R16, R17, T10,T12, T13, T14,T15, U12, U13, U14,U15, AD15.

Ground for Core 1.8V, SSTL2 2.5V, and I/O 3.3V power supplies. (54 pins)



19


Table 16. No Connection Pin Name I/O Ball # Description

NC AO A1, C5, D5, AC17, K3, F1

No connection (6 pins)

Notes:

(1) VDD pins having “_3.3”, "_2.5", and “_1.8” in their names should be connected to 3.3V, 2.5V, and 1.8V power supplies respectively.

(2) “AP” indicates a power supply that is analog in nature and does not have large switching currents. These should be isolated from other digital supplies that contain large switching currents.

(3) All digital I/O, GPIO’s, shared functionality GPIO’s are 5 volt tolerant.

(4) All unused inputs must be connected to a known logic state.



20


4. FUNCTIONAL DESCRIPTION

A functional block diagram is illustrated below. Each of the functional units shown is described in the following sections.

Infra-red Rx

Low

ndwidBa th Pulse Width Modulator

DDC2Bi DVI

24-bit input port / 16-bit YUV

8-bit ITU656 YUV Input

DVI-Compliant Input

14.318 MHz

Crystal Reference

JTAG

GPIO

2-wire Serial I/F

External X186 Interface

Parallel ROM

IF/external micro

Analog RGBInput

DDC2Bi analog

DCA

Test Pattern Generator

Ultra-Reliable

DVI Rx

Triple ADC and PLL

Image Capture

and Measure

ment

Graphics

Shrink Filter

Clock Generation

Frame Store

Control

ROM I/F

Internal ROM

OSD Controller Color Table

RAMs

OB

Video Shrink Filter

Motion Adapt.

3:2/2:2

detection

Video Zoom Filter

Graphics

Zoom Filter

Image Capture

and Measure

ment

Internal RAM

Micro-controller

Figure 3. gm1601 Functional Block Diagram

DDR SDRAM I/F

44..11 CClloocckk GGeenneerraattiioonn

The gm1601 features 4 clock inputs. All additional clocks are internal clockmore of these:

1. Crystal Input Clock (TCLK and XTAL). This is the input pair to an inteand corresponding logic. A 14.318 MHz TV crystal is required. This is below. Alternatively, a single-ended TTL/CMOS clock oscillator can

C1601-DAT-01F *** Preliminary Information – Subject to Change **


21

l

s

i

RealColorTM

TTL/LVDS

Tx

Display Timing Generator

utput ender

Panel Data /Control

derived from one or

rnal crystal oscillator llustrated in Figure 4 be driven into the

November 2003 *

xupeng

Pencil


TCLK pin (leave XTAL as N/C in this case). This is illustrated in Figure 7 below. This option is selected by connecting a 10KΩ pull-up to OCMADDR10.

2. DVI Differential Input Clock (RC+ and RC-)

3. Video Graphics Clock (4:4:4/4:2:2/CCIR656)

4. Video Graphics Clock (CCIR656)

The gm1601 TCLK oscillator circuitry is a custom designed circuit to support the use of an external oscillator or a crystal resonator to generate a reference frequency source for the gm1601 device.

4.1.1 Using the Internal Oscillator with External Crystal

The recommended option for providing a clock reference is to use the internal oscillator with an external crystal. The oscillator circuit is designed to provide a very low jitter and very low harmonic clock to the internal circuitry of the gm1601. An Automatic Gain Control (AGC) is used to ensure startup and operation over a wide range of conditions. The oscillator circuit also minimizes the overdrive of the crystal, which reduces the aging of the crystal.

When the gm1601 is in reset, the states of the OCMADDR10 ball (ball number V2) and OCMADDR16 ball (ball number U4) are sampled. If the OCMADDR16 ball is pulled high to I/O_3.3 with an external resistor (10KΩ recommended, 15KΩ maximum), then the internal oscillator is enabled, and the output of this oscillator will become the TCLK.

In this mode, a crystal resonator is connected between TCLK (ball G3) and the XTAL (ball G4) with the appropriately sized loading capacitors CL1 and CL2. The size of CL1 and CL2 are dependent on the crystal manufacturer’s specification and must compensate for the parasitic capacitance of the gm1601 device and the printed circuit board traces. The loading capacitors are terminated to the analog VDD power supply. This connection increases the power supply rejection ratio when compared to terminating the loading capacitors to ground.



22



Reset State Logic

XTAL

TCLK

OSC_OUTTCLK Distribution

gm1601

G3

G4

U4

Vdd

180 uA100 K

CL1

CL2

Internal Oscillator Enable

Vdda

Vdda

OCMADDR16

EXTCLK

R4

OCMADDR10

V2

Vddenable

Reset State Logic

1

1

0

0

Figure 4. Using the Internal Oscillator with External Crystal

The TCLK oscillator uses a Pierce Oscillator circuit. The output of the oscillator circuit, measured at the TCLK pin, is an approximate sine wave with a bias of about 2 volts above ground (see Figure 5). The peak-to-peak voltage of the output can range from 250 mV to 1000 mV depending on the specific characteristics of the crystal and variation in the oscillator characteristics. The output of the oscillator is connected to a comparator that converts the sine wave to a square wave. The comparator requires a minimum signal level of about 50-mV peak to peak to function correctly. The output of the comparator is buffered and then distributed to the gm1601 circuits.



23


~ 2 Volts

3.3 Volts

250 mV peak to peakto

1000 mV peak to peak

time

Figure 5. Internal Oscillator Output

One of the design parameters that must be given some consideration is the value of the loading capacitors used with the crystal as shown in Figure 6. The loading capacitance (Cload) on the crystal is the combination of CL1 and CL2 and is calculated by Cload = ((CL1 * CL2) / (CL1 + CL2)) + Cshunt. The shunt capacitance Cshunt is the effective capacitance between the XTAL and TCLK pins. For the gm1601 this is approximately 9 pF. CL1 and CL2 are a parallel combination of the external loading capacitors (Cex), the PCB board capacitance (Cpcb), the pin capacitance (Cpin), the pad capacitance (Cpad), and the ESD protection capacitance (Cesd). The capacitances are symmetrical so that CL1 = CL2 = Cex + CPCB + Cpin + Cpad + CESD. The correct value of Cex must be calculated based on the values of the load capacitances. Approximate values are provided in Figure 6.

XTAL

TCLK

gm1601

G3

G4

Cex1

Cex2

Internal Oscillator

Cpcb

Cshunt

Cpcb Cpin Cpad Cesd

Cpin Cpad Cesd

Vdda

Vdda

CL1 = Cex1 + Cpcb + Cpin + Cpad + Cesd

CL2 = Cex1 + Cpcb + Cpin + Cpad + Cesd

Approximate values:CPCB ~ 2 pF to 10 pF (layout dependent)Cpin ~ 1.1 pFCpad ~ 1 pFCesd ~ 5.3 pFCshunt ~ 9 pF

Figure 6. Sources of Parasitic Capacitance



24


Some attention must be given to the details of the oscillator circuit when used with a crystal resonator. The PCB traces should be as short as possible. The value of Cload that is specified by the manufacturer should not be exceeded because of potential start up problems with the oscillator. Additionally, the crystal should be a parallel resonate-cut and the value of the equivalent series resistance must be less then 90 Ohms.

4.1.2 Using an External Clock Oscillator

Another option to provide the reference clock is by applying a single-ended external clock oscillator. When the gm1601 is in reset, the states of the OCMADDR10 (ball V2) and OCMADDR16 (ball U4) are sampled. If OCMADDR16 is pulled low by connecting it to D_GND through a pull-down resistor, then the internal oscillator is disabled and the external oscillator mode is enabled. If OCMADDR10 is pulled high to I/O_3.3 via a pull-up resistor, the external clock signal is selected as coming from the EXTCLK ball (ball R4), else if OCMADDR10 is pulled low to D_GND via a pull-down resistor the external clock signal is selected as coming from the TCLK ball (ball G3). This is illustrated in Figure 7.

Vdd

GND

Oscillator

InternalOscillator

Reset State Logic

OCMADDR16

XTAL

TCLK

14.318 MHzVdd

OSC_OUTTCLK Distribution

Disable

gm1601

G3

G4

U4

External Oscillator Enable

10 K

EXTCLKR4

OCMADDR10

V2

Reset State Logic

1

1

0

0

Figure 7. Using an External Single-ended Clock Oscillator

Frequency 14.318 MHz Jitter Tolerance 250 ps Rise Time (10% to 90%) 5 ns Maximum Duty Cycle 40-60

Table 17. TCLK Specification



25


4.1.3 Clock Synthesis

The gm1601 synthesizes all additional clocks internally as illustrated in Figure 8 below. The synthesized clocks are as follows:

1. Main Timing Clock (TCLK) is the output of the chip internal crystal oscillator. TCLK is derived from the TCLK/XTAL pad input.

2. Reference Clock (RCLK) synthesized by RCLK PLL using TCLK or EXTCLK as the reference.

3. Frame-Store Clock (FSCLK) synthesized by FCLK PLL using either RCLK or TCLK or EXTCLK as the reference.

4. OCM Clock. The internal x186 CPU clock can be either be the Half Reference Clock (RCLK/2), Quarter Reference Clock (RCLK/4), TCLK, or EXTCLK.

5. DVI Input Clock (DVI_CLK) synthesized by DVI receiver PLL using RC+/RC- pair as the reference.

6. Input RGB Source Clock (SCLK) synthesized by the Source DDS (SDDS) PLL using the input HSYNC as the reference. The SDDS internal digital logic is driven by RCLK.

7. Input Video Source Clock (VCLK) is input directly from an external source.

8. IGPCLK and IVPCLK are selected from any of the above mentioned data source clocks.

9. Display Clock (DCLK) synthesized by the Destination DDS (DDDS) PLL using IGPCLK or IVPCLK as the reference. The DDDS internal digital logic is driven by RCLK.

10. LVDS differential clock is synthesized by an internal PLL using the Display clock as the reference.



26

xupeng

Pencil

xupeng

Pencil

xupeng

Pencil

xupeng

Pencil

xupeng

Pencil

xupeng

Pencil

xupeng

Pencil

xupeng

Pencil


DVIRx

CLK+CLK-

ADC +TPGEN

VPORT

SVPORT

TCLK

EXTCLK

RCLKPLL

RCLK FCLKPLL

FSCLK

DIV1/2

DIV1/2

OCMCLK

SDDS DDDS

656\DEC

IGPCLK

IVPCLK

RCLK/2RCLK/4

AHSYNCGREEN+

SOG

IGP

IVP

MC(memorycontroller

OCM(186 cpu)

ODP_CLK (display clock)

GHS GVS

VHS VVS

ODPVCLK

SVCLK

HREF SCLK

LVDSTx

DCLK

AC+, AC-

Select sourcetiming master

"glitchless" clockswitch

OSC

Bootstrapselection

Other clocksources

BC+, BC-

IFMCLKRCLK / 4

TCLK

DIV1/8

TCLK/8TCLK

Figure 8. Internally Synthesized Clocks

The on-chip clock domains are selected from the synthesized clocks. These include:

1. Input Domain Clock (IGP_CLK). Max = 165MHz, and

(IVP_CLK). Max = 108MHz for progressive scan and interlaced inputs for spatial processing. (IVP_CLK). Max = 75MHz for interlaced inputs for temporal video processing.

2. On-Chip Micro-controller Clock (OCM_CLK). Max = 100MHz

3. Display Pixel Clock (DP_CLK). Max = 165MHz

4. Source Timing Measurement Domain Clock (IFM_CLK). Max = 50MHz

5. ADC Domain Clock (SCLK). Max = 165MHz.



27


The clock selection for each domain as shown is software-configurable.

44..22 HHaarrddwwaarree RReesseett

A Hardware Reset is performed by holding the RESETn pin low for a minimum of 1ms (see diagram below). A TCLK input (see Clock Options above) must be applied during and after the reset. When the reset period is complete and RESETn is de-asserted, the following power-up sequence is applied internally:

1. Reset all registers of all types to their default state (this is 00h unless otherwise specified in the gm1601 Register Listing).

2. Force each clock domain into reset. Reset will remain asserted for at least 64 local clock domain cycles following the assertion of RESETn.

3. Operate the OCMCLK domain at the TCLK frequency.

4. Operate the FSCLK domain at the TCLK frequency.

5. Set the RCLK PLL to generate ~200MHz clock (14.318MHz TCLK crystal required). Set RCLK PLL to be bypassed by TCLK.

6. Set the FCLK PLL to output ~157.3MHz clock (14.318MHz TCLK crystal required). Set FCLK PLL to be bypassed by TCLK

3 . 3 V

2 . 5 V

1 . 8 V

R E S E T /

> 0 s e c

> 1 m s e c

44..33 SSooffttwwaarree RReesseett

Main blocks within the gm1601 may be independently hardware reset via “software” by means of setting software reset bits in the SOFT_RESETS register.



28


44..44 AAnnaalloogg ttoo DDiiggiittaall CCoonnvveerrtteerr ((AADDCC))

The gm1601 chip has three video ADCs (analog-to-digital converters), one for each color (red, green, and blue).

4.4.1 ADC Pin Connection

The analog RGB signals are connected to the gm1601 as described below:

Table 18. Pin Connection for RGB Input with HSYNC/VSYNC Pin Name ADC Signal Name

Red+ Red Red- Terminate in manner similar to Green- channel. Green+ Green. When using Sync-On-Green, this signal also caries the sync pulse Green- Terminate as illustrated in Figure 9 Blue+ Blue Blue- Terminate in manner similar to Green- channel. HSYNC Horizontal Sync (Terminate as illustrated in Figure 9) or Composite Sync VSYNC Vertical Sync (Terminate as with HSYNC illustrated in Figure 9)

SOG Sync on Green slicer input (connect to “GREEN+” only as illustrated in Figure 9)

15Ω

100 nF

GREEN +

gm1601

75Ω

DB15

GRN

GND

52Ω

100 nF

GREEN-

AHSYNCHSYNC

AVSYNCVSYNC

SOG

100 nF470Ω

Figure 9. Example ADC Signal Terminations

Please note that it is very important to follow the recommended layout guidelines for the circuit shown in Figure 9. These are described in "gm1601 Layout Guidelines" document number C1601-SLG-01.



29


4.4.2 ADC Characteristics

The table below summarizes the characteristics of the ADC:

Table 19. ADC Characteristics MIN TYP MAX NOTE Track & Hold Amp Bandwidth 290 MHz Guaranteed by design. Note that the Track &

Hold Amp Bandwidth is programmable. 290 MHz is the maximum setting.

Full Scale Adjust Range at RGB Inputs 0.55 V 0.90 V Full Scale Adjust Sensitivity +/- 1 LSB Measured at ADC Output.

Independent of full-scale RGB input. Zero Scale Adjust Sensitivity +/- 1 LSB Measured at ADC Output. Sampling Frequency (Fs) 10 MHz 165 MHz Differential Non-Linearity (DNL) +/-0.5 LSB +/-0.9 LSB Fs = 162 MHz No Missing Codes Guaranteed by test. Integral Non-Linearity (INL) +/- 1.5 LSB Fs =162 MHz Channel to Channel Matching +/- 0.5 LSB

The gm1601 ADC has a built-in clamp circuit for AC-coupled inputs. By inserting series capacitors (about 100 nF), the DC offset of an external video source can be removed. The clamp pulse position and width are programmable.

4.4.3 Clock Recovery Circuit

The SDDS (Source Direct Digital Synthesis) clock recovery circuit generates the clock used to sample analog RGB data (IP_CLK or source clock). This circuit is locked to the HSYNC of the incoming video signal.

Patented digital clock synthesis technology makes the gm1601 clock circuits resistant to temperature/voltage drift. Using DDS (Direct Digital Synthesis) technology, the clock recovery circuit can generate any IP_CLK clock frequency within the range of 10MHz to 165MHz.

WindowCapture

SDDS

ADCRGB

IPCLKHSYNC HSYNC(delayed)

24

Phase

Image PhaseMeasurement

Temperaturecompensation

Figure 10. gm1601 Clock Recovery



30


4.4.4 Sampling Phase Adjustment

The programmable ADC sampling phase is adjusted by delaying the HSYNC input to the SDDS. The accuracy of the sampling phase is checked and the result is read from a register. This feature enables accurate auto-adjustment of the ADC sampling phase.

4.4.5 ADC Capture Window

Figure 11 below illustrates the capture window used for the ADC input. In the horizontal direction, the capture window is defined in IP_CLKs (equivalent to a pixel count). In the vertical direction, it is defined in lines.

All the parameters beginning with “Source” are programmed gm1601 registers values. Note that the Input Vertical Total is determined solely by the input and is not a programmable parameter.

Reference Point

Inpu

t Ver

tical

Tot

al (l

ines

)

Sour

ce H

eigh

t

Sour

ce

Vsta

rt

Source Horizontal Total (pixels)

Source Hstart

Source Width

Capture Window

Figure 11. ADC Capture Window

The Reference Point marks the leading edge of the first internal HSYNC following the leading edge of an internal VSYNC. Both the internal HSYNC and the internal VSYNC are derived from external HSYNC and VSYNC inputs.

Horizontal parameters are defined in terms of single pixel increments relative to the internal horizontal sync. Vertical parameters are defined in terms of single line increments relative to the internal vertical sync.

For ADC interlaced inputs, the gm1601 may be programmed to automatically determine the field type (even or odd) from the VSYNC/HSYNC relative timing. See Input Format Measurement, Section 4.8.



31


44..55 UUllttrraa--RReelliiaabbllee DDiiggiittaall VViissuuaall IInntteerrffaaccee RReecceeiivveerr ((DDVVII RRxx))

The Ultra-Reliable DVI® receiver block of the gm1601 is compliant with DVI1.0 single link specifications. This block supports an input clock frequency ranging from 20 MHz to 165 MHz.

4.5.1 DVI Receiver Characteristics

Table 20 summarizes the characteristics of the four Receiver Pair inputs. Please note that it is very important to follow the recommended layout guidelines for these signals. These are described in "gm1601 Layout Guidelines" document number C1601-SLG-01.

Table 20. DVI Receiver Characteristics MIN TYP MAX NOTE

DC Characteristics

Differential Input Voltage 150mV 1200mV Input Common Mode Voltage AVDD

–300m V AVDD

-37mV

Behavior when Transmitter Disable AVDD -10mV

AVDD +10mV

AC Characteristics Input clock frequency 20 MHz 165 MHz Input differential sensitivity (Peak-to-peak) 150mV Max differential input (peak-to-peak) 1560 mV Allowable Intra-Pair skew at Receiver 250 ps Allowable Inter-Pair skew at Receiver 4.0 ns

Input clock = 165 MHz

Through register programming, the receiver unit may be placed in either of following states:

• Active: The receiver block is fully on and running.

• Off: The receiver block is powered down.

4.5.2 DVI Capture Window

DE (Display Enable), HSYNC and VSYNC are synthesized internally by examining the active regions of each line and compensating for possible source timing errors and/or embedded HSYNC / VSYNC jitter.

There are two ways to define the DVI capture region:

CREF Capture - In this mode the usual active window parameters must be programmed as with ADC inputs (see Section 4.4.5.).

DE Capture - In this mode the active window code embedded in the DVI signal defines the active window automatically. Only the active width and active length parameters obtained by performing Input Format Measurement (IFM) need be programmed.



32

lifeng

Note

表20是一对输入接受的典型概述

lifeng

Note

请求记录是非常重要的。遵循被推荐的信号设计指导方针



44..66 DDiiggiittaall VViiddeeoo GGrraapphhiiccss PPoorrtt

The following video formats supplied by external video decoders or ADCs are supported by the digital video graphic port:

ITU-BT-656 • • • • •

8-bit 4:2:2 YCbCr or YPbPr 16-bit 4:2:2 YCbCr or YPbPr 24-bit 4:4:4 YCbCr or YPbPr 24-bit RGB

Additionally, a second 8-bit 4:2:2 YCbCr port exists for input from a video decoder. 8 bits from the main video port may be allocated to the second video port, subsequently providing for two 16 bit video ports. (* Note that only one BT-656 stream can be processed at a time.) The timing of these video formats are shown in the following figures.

VCLK

YUV(7:0)(Input) Y0000FF SAV Cb YCr YCb

1171517141713 0 32 541712

Preamble

Timing Reference wordSAV (Start of Active Video)

Active Video

17111710

Blanking YCr Cb 0000FF EAV Blanking

1437 1438 1439 1440 1441 1442 1443

Preamble

Timing Reference wordEAV (End of Active Video)

1444

Figure 12. ITU-R BT656 Input

ACLK

Cb0 Y0 Cr0 Y1 ~ Cr718 Y719YCbCr

Figure 13. 8-bit 4:2:2 YCbCr/YPbPr

CbCr

ACLK

Y0 Y1 Y2 ~ Y717 Y718 Y719

Cb0 Cr0 Cb2 ~ Cr716 Cb718 Cr718

Y




33


Cb

ACLK

Y0 Y1 Y2 ~ Y717 Y718 Y719

Cb0 Cb1 Cb2 ~ Cb717 Cb718 Cb719

Y

Cr Cr0 Cr1 Cr2 ~ Cr717 Cr718 Cr719


G

ACLK

R0 R1 R2 ~ R717 R718 R719

G0 G1 G2 ~ G717 G718 G719

R

B B0 B1 B2 ~ B717 B718 B719

Figure 16. 24-bit RGB

4.6.1 656 Decoder

ITU-BT-656 video format consists of pixel clock and 8 bits of data. No separate HSYNC, VSYNC and odd signals are present. Timing data is embedded in the data stream. The internal 656 decoder will extract the HSYNC, VSYNC and odd signals from the embedded timing data.

4.6.2 YCbCr Input Clamping

YCbCr input to the gm1601 is always automatically clamped to restrict the input data to ITU-R BT601 levels:

Y Bottom clamping: Y data < 16 is clamped to 16.

Y Top clamping: Y data > 235 is clamped to 235.

CbCr Bottom clamping: CbCr data < 16 is clamped to 16.

CbCr Top clamping: CbCr data > 240 is clamped to 240.

44..77 TTeesstt PPaatttteerrnn GGeenneerraattoorr ((TTPPGG))

The gm1601 contains many test patterns, some of which are shown in Figure 17. Once programmed, the gm1601 test pattern generator can replace a video source (e.g. a PC) during factory calibration and test. This simplifies the test procedure and eliminates the possibility of image noise being injected into the system from the source. The foreground and background



34

xupeng

Pencil


colors are programmable. In addition, the gm1601 OSD controller can be used to produce other patterns.

Figure 17. Some Examples of gm1601 Built-in Test Patterns

The DDC2Bi port can be used for factory testing. This is illustrated in Figure 18. The factory test station connects to the gm1601 through the Direct Data Channel (DDC) of the DSUB15 or DVI connectors. Then, the PC can make gm1601 display test patterns (see section 4.7). A camera can be used to automate the calibration of the LCD panel.

DDC

Device-Under-Test Factory Test Station

Camera

Figure 18. Factory Calibration and Test Environment

44..88 IInnppuutt FFoorrmmaatt MMeeaassuurreemmeenntt ((IIFFMM))

The gm1601 has an Input Format Measurement block (the IFM) providing the capability of measuring the horizontal and vertical timing parameters of the input video source. This information may be used to determine the video format and to detect a change in the input format. It is also capable of detecting the field type of interlaced formats.

The IFM features a programmable reset, separate from the regular gm1601 soft reset. This reset disables the IFM, reducing power consumption. The IFM is capable of operating while the gm1601 is running in power-down mode.

Horizontal measurements are measured in terms of the selected IFM_CLK (either TCLK or RCLK/4, or EXTCLK), while vertical measurements are measured in terms of HSYNC pulses.

For an overview of the internally synthesized clocks, see section 4.1.

4.8.1 HSYNC / VSYNC Delay

The active input region captured by the gm1601 is specified with respect to internal HSYNC and VSYNC. By default, internal syncs are equivalent to the HSYNC and VSYNC at the input pins and thus force the captured region to be bounded by external HSYNC and VSYNC timing.



35

xupeng

Pencil

xupeng

Pencil

xupeng

Pencil


However, the gm1601 provides an internal HSYNC and VSYNC delay feature that removes this limitation. This feature is available for use with both the ADC input and the DVI Rx (DE-regeneration mode). By delaying the sync internally, the gm1601 can capture data that spans across the sync pulse.

It is possible to use HSNYC and VSYNC delay for image positioning. (Alternatively, Source_HSTART and Source_VSTART in Figure 11 are used for image positioning of analog input.) Taken to an extreme, the intentional movement of images across apparent HSYNC and VSYNC boundaries creates a horizontal and/or vertical wrap effect.

HSYNC is delayed by a programmed number of selected input clocks.

HS(system) active active

captureHS(internal) capture capture

programmabledelay input block actually

captures across HSYNC Figure 19. HSYNC Delay

Delayed horizontal sync may be used to solve a potential problem with VSYNC jitter with respect to HSYNC. VSYNC and HSYNC are generally driven active coincidentally, but with different paths to the gm1601 (HSYNC is often regenerated from a PLL). As a result, VSYNC may be seen earlier or later. Because VSYNC is used to reset the line counter and HSYNC is used to increment it, any difference in the relative position of HSYNC and VSYNC is seen on-screen as vertical jitter. By delaying the HSYNC a small amount, it can be ensured that VSYNC always resets the line counter prior to it being incremented by the “first” HSYNC.

delayed HS placed safely within blankingactive data crosses HS boundary

Data

HS (system)

Internal Delayed HS

Figure 20. Active Data Crosses HSYNC Boundary

4.8.2 Horizontal and Vertical Measurement

The IFM is able to measure the horizontal period and active high pulse width of the HSYNC signal, in terms of the selected clock period (either TCLK or RCLK/4 or EXTCLK). Horizontal measurements are performed on only a single line per frame (or field). The line used is programmable. It is able to measure the vertical period and VSYNC pulse width in terms of rising edges of HSYNC. C1601-DAT-01F November 2003


36

Administrator

Pencil


Once enabled, measurement begins on the rising VSYNC and is completed on the following rising VSYNC. Measurements are made on every field / frame until disabled.

4.8.3 Format Change Detection

The IFM is able to detect changes in the input format relative to the last measurement and then alert both the system and the on-chip micro-controller. The micro-controller sets a measurement difference threshold separately for horizontal and vertical timing. If the current field / frame timing is different from the previously captured measurement by an amount exceeding this threshold, a status bit is set. An interrupt can also be programmed to occur.

4.8.4 Watchdog

The watchdog monitors input VSYNC / HSYNC. When any HSYNC period exceeds the programmed timing threshold (in terms of the selected IFM_CLK), a status bit is set. When any VSYNC period exceeds the programmed timing threshold (in terms of HSYNC pulses), a second status bit is set. An interrupt can also be programmed to occur.

4.8.5 Internal Odd/Even Field Detection

The IFM has the ability to perform field decoding of interlaced inputs to the ADC via two methods.

The first method consists of internal hardware counting the number of lines between v-sync pulses for the current field. If the count is found to be an “odd” number, then the next field is marked “even”. This first method is recommended to be used.

With the second method the user specifies start and end values to outline a “window” relative to HSYNC. If the VSYNC leading edge occurs within this window, the IFM signals the start of an ODD field. If the VSYNC leading edge occurs outside this window, an EVEN field is indicated (the interpretation of odd and even can be reversed). The window start and end points are selected from a predefined set of values.

HS

window

VS - even

VS - odd

WindowStart

Window End

Figure 21. ODD/EVEN Field Detection



37


4.8.6 Input Pixel Measurement

The gm1601 provides a number of pixel measurement functions intended to assist in configuring system parameters such as pixel clock, SDDS sample clocks per line and phase setting, centering the image, or adjusting the contrast and brightness.

4.8.7 Image Phase Measurement

This function measures the sampling phase quality over a selected active window region. This feature may be used when programming the source DDS to select the proper phase setting.

4.8.8 Image Boundary Detection

The gm1601 performs measurements to determine the image boundary. This information is used when programming the Active Window and centering the image.

4.8.9 Image Auto Balance

The gm1601 performs measurements on the input data that are used to adjust brightness and contrast.



38


44..99 RReeaallCCoolloorrTTMM DDiiggiittaall CCoolloorr CCoonnttrroollss

The gm1601 provides high-quality digital color controls that can be applied independently to the video and RGB data streams. These consist of a full 3x3 RGB matrix multiplication stage, followed by an signed offset stage as shown in Figure 22.

X +/-+/-+/-

Additive Offset

(Brightness)

3x3 Color Conversion

Red In Red Out

Green In Green Out

Blue In Blue Out

Figure 22. RealColor® Digital Color Controls

This structure can accommodate all RGB color controls such as black-level (subtractive stage), contrast (multiplicative stage), and brightness (signed additive offset). In addition, it supports all YUV color controls including brightness (additive factor applied to Y), contrast (multiplicative factor applied to Y), hue (rotation of U and V through an angle) and saturation (multiplicative factor applied to both Y and V).

To provide the highest color purity all mathematical functions use 10 bits of accuracy. The final result is then dithered to eight or six bits (as required by the LCD panel).

4.9.1 RealColor™ Flesh tone Adjustment

The human eye is more sensitive to variations of flesh tones than other colors; for example, the user may not notice if the color of grass is modified slightly during image capture and/or display. However, if skin tones are modified by even a small amount, it is unacceptable. The gm1601 features flesh tone adjustment capabilities. This feature is not based on lookup tables, but rather a manipulation of YUV-channel parameters. Flesh tone adjustment is available for all inputs.

4.9.2 Color Standardization and sRGB Support

Internet shoppers may be very particular about what color they experience on the display. The gm1601 RealColor® digital color controls can be used to make the color response of an LCD monitor compliant with standard color definitions, such as sRGB. sRGB is a standard for color exchange proposed by Microsoft and HP (see www.srgb.com). gm1601 RealColor® controls allow LCD monitors to become sRGB compliant, even if the native response of the LCD panel itself is not.



39

http://www.srgb.com)/


4.9.3 Zoom Scaling

The gm1601 dual zoom/shrink scalers use an advanced scaling technique proprietary to Genesis Microchip Inc., providing simultaneous high quality scaling of real time video and graphics images on both channels. An input field/frame is scalable arbitrarily in both the vertical and horizontal dimensions.

Video Channel

Non-linear scaling is available for aspect ratio conversion of video modes particularly for Panoramic Scaling (4:3 to 16:9) and the reverse (16:9 to 4:3).

Interlaced fields are de-interlaced by a Motion Adaptive process and support advanced film mode field pairing.

Graphics Channel

The gm1601 scaling filter for the graphics channel can combine its advanced scaling with a pixel-replication type scaling function for scaling inputs more than 2X. This is useful for improving the sharpness and definition of graphics when scaling at high zoom factors (such as SVGA to UXGA). Spatial De-interlacing is provided on this channel by vertically scaling and repositioning the input fields to align with the output display’s pixel map.

4.9.4 Horizontal and Vertical Shrink

A shrink function may be arbitrarily performed both horizontally and vertically on the input data. This is an arbitrary active resolution reduction of up to 3 octaves of shrink (i.e. to 1/8 input) for the video channel and up to 5 octaves (i.e. to 1/32 input) for the graphics channel. Cropping is supported during input capture to the frame store while performing vertical flip to the display device.

4.9.5 Image Flip

When the frame buffer is utilized, the display image may be arbitrarily flipped horizontally (left/right) and/or vertically (up/down), via register programming. The OSD image can also be flipped along with the display image when image flip is performed. Vertical flip is not supported with cropping operation on output of frame store.

4.9.6 Inverse 3:2 / 2:2 Pull-down De-Interlacing

Video graphics with 3:2 / 2:2 field sequence are processed with the built-in Adaptive Film Mode controller. The field sequence is first detected by examining the field motion values and once a field sequence is identified, the corresponding film mode processing is applied. The following figure illustrates the inverse 3:2 pull-down processing.



40


60Hz interlaced video fields converted from 24Hz film (3:2 pull-down sequence)

60 Hz progressive frames

Figure 23. Inverse 3:2 Pulldown Processing

4.9.7 Motion Adaptive De-Interlacing (MADI)

Motion adaptive de-interlacing in the gm1601 is a pixel-based 2-phase process. Phase 1 is the detection of motion and the generation of a motion value for each pixel. These pixel motion values are used as a measure of the current “degree of motion”. In phase 2, the pixel motion values are used to select the appropriate de-interlacing technique.

As a result, areas of an image that are not moving will be fully static (flicker free), and moving objects will have smooth edges. MADI is only supported in the video processing data path.

4.9.8 Low Angle Diagonal Interpolation

In addition to the advanced de-interlacing capabilities mentioned in the previous sections, further image enhancement is achieved by applying special processing to moving low angle diagonal pattern in an image.

The diagonal interpolation process involves detecting low angle diagonal patterns in an image and applying special interpolation along the local diagonal pattern. The result is a smooth edge on moving objects with diagonal patterns.

4.9.9 “3D” Noise Reduction

“3D” noise reduction is implemented by applying temporal (inter-field) and spatial (intra-field) noise reduction filters to the video data.

The temporal noise reduction filter is applied first. It takes the values of the same pixel from different fields for noise filtering.

Spatial and “3D” noise reduction filters are available for interlaced standard definition video on the video input channel.



41


4.9.10 Sharpening Filters

The gm1601 provides sharpening filters to enhance high frequency components in the video processing channel. Different levels of sharpening can be implemented by selecting different programmable coefficients for the horizontal and vertical sharpening filters.

Sharpening is not supported in the graphics channel.



42


44..1100 BByyppaassss OOppttiioonnss

The gm1601 has the capability to completely bypass internal processing for the graphics channel only. In this case, captured input signals and data are passed, with a small latency, straight through to the display timing controller. The gm1601 is also able to bypass the zoom filter and the gamma LUT.

44..1111 GGaammmmaa LLooookk UUpp TTaabbllee ((LLUUTT))

The gm1601 provides an 8 to 10-bit look-up table (LUT) for each input color channel intended for Gamma correction and to compensate for a non-linear response of the LCD panel. A 10-bit output results in an improved color depth control. The 10-bit output is then dithered down to 8 bits (or 6 bits) per channel at the display (see section 4.14.4 below). The LUT is user-programmable to provide an arbitrary transfer function. Gamma correction occurs after the zoom / shrink scaling block. If bypassed, the LUT does not require programming.

44..1122 PPiiccttuurree--IInn--PPiiccttuurree ((PPIIPP)) DDiissppllaayy

The gm1601 allows a very flexible PIP display configuration whereby either the graphics or video channel may act as the PIP source to overlay over the other channel. Any one of the inputs ( DVI, analog RGB, 24 bit digital, or 8 bit digital) may be multiplexed to either channel. The PIP display can also be configured for multiple PIP's. A PIP border can be achieved by overlaying an OSD background tile around the PIP window.

Single PIP allows the PIP display to be placed arbitrarily in the display window. It can be placed within the MAIN display, partially overlapped with MAIN display, or fully detached from MAIN display. The size of the PIP display is fully programmable. Also, single PIP display allows 16 levels of alpha blending within the PIP window either with a specified background color or the main channel. A special case of single PIP display is side-by-side configuration. In this case the video and graphics are put side by side in the display in a split screen format.

Multiple PIPs display allows a number of PIP windows to be displayed at the same time depending on display pixel resolution. MAIN and one PIP window will be running at real time. PIP size in multi PIP mode is adjustable in increments of 64 input pixels horizontally and one line vertically.



43


44..1133 FFrraammee SSttoorree IInntteerrffaaccee

The external frame buffer provides the storage required for the frame rate conversion process and the integrated OSD.

The integrated memory controller arbitrates and controls the writing/reading of video data to/from the external memory. Input video data are written into the frame buffer for processing and display data are read back from the frame buffer. Frame buffer addresses are fully programmable so as to provide flexibility for memory allocation of MAIN and PIP display. This flexibility also allows the implementation of various multiple PIP display configurations.

The gm1601 operates with 32 bit DDR (Dual Data Rate) memory devices only.

The FCLK_PLL synthesizes the FS_CLK to drive the FRC logic and Framestore Interface.

4.13.1 Supported DDR Devices

The gm1601 operates seamlessly with commercially available DDR devices at operating frequencies up to 172MHz. The frame store interface is always 32 bits wide.

The gm1601 supports 3 types of memory sizes: 64Mb, 128Mb, and 256Mb.

4.13.2 Adjustable Frame Store Interface Parameters

The gm1601 provides a full set of registers to optimize the timing parameters for a particular memory interface. Most will not require adjustment as the gm1601 automates the process of initialization.

4.13.3 DDR Memory Power On and Initialization Sequence

DDR devices have power-on and initialization sequences that must be performed before they can be reliably accessed. The gm1601 automatically performs these sequences.

4.13.4 DDR Memory Power Down

DDR devices typically have a low power, non-operational mode. The gm1601 supports this feature by providing a power down sequence.

4.13.5 Pan and Crop Operations

Pan and Crop is a function that may be implemented in the Active Window Decoder or via the frame store controller. The frame store controller may be programmed to extract a rectangular portion of the stored image. This rectangular portion of the image may be displayed at native resolution, or scaled to the display resolution. Note that frame tear may result if a single frame buffer is used.



44


4.13.6 Double Buffering Frame Store Bandwidth Requirements

To perform pan, crop and/or flip operations without frame tear, the frame store must be large enough to accommodate two images (double buffering). For example, if the input is SXGA resolution, the frame store must be a minimum of 1280 x 1024 x 24 bits x 2 = 60 Mbits.

4.13.7 Freeze Frame

Freeze frame capability is made available by disabling the input capture during the vertical blanking interval. This does not disrupt the flow of data from the frame store. During freeze frame, adjustments made to the contrast and brightness controls will still have an affect on the displayed image.

44..1144 DDiissppllaayy OOuuttppuutt IInntteerrffaaccee

The Display Output Port provides data and control signals that permit the gm1601 to connect to a variety of display devices using a TTL or LVDS interface. The output interface is configurable for single or dual wide TTL/LVDS in 18, 24 or 30-bit RGB pixels format. Six-bit and eight-bit panels with either LVDS or TTL interface are supported in both single and dual-wide format. Ten-bit panels are supported in both single and dual-wide format but only with TTL interface.

All display data and timing signals are synchronous with the DCLK output clock. The integrated LVDS transmitter is programmable to allow the data and control signals to be mapped into any sequence depending on the specified receiver format. DC balanced operation is supported as described in the Open LDI standard.

4.14.1 Display Synchronization

The gm1601 display synchronization modes:

• Frame Sync Mode: The display frame rate is synchronized to the input frame or field rate. This mode is used for standard operation. Frame rate conversion is optionally performed.

• Free Run Mode: No synchronization. This mode is used when there is no valid input timing (i.e. to display OSD messages or a splash screen) or for testing purposes. In fee-run mode, the display timing is determined only by the values programmed into the display window and timing registers.

• Auto Sync Mode: This mode is used for bypassing very large formats such as WUXGA around the frame buffer for display at native resolution on the display.

4.14.2 Display Timing Programming



45

Display timing signals provide timing information so the Display Port can be connected to an external display device via a TTL or LVDS interface. Based on values programmed in registers, the Display Timing Generator produces the horizontal sync (DHS), vertical sync (DVS), and data enable (DEN) control signals. The figure below provides the registers that define the output display timing.


Horizontal values are in single pixel increment except display horizontal sync end position which is in 4-DCLK increments. When the display is in double-wide mode, horizontal settings should use even numbers. Vertical values are programmed in line increments relative to the leading edge of the vertical sync signal.

Display Active Window

Display Background Window

Vertical Blanking (Back Porch)

VSYNC Region

Hor

izon

tal B

lank

ing

(Bac

k Po

rch)

HSY

NC

regi

on

DV_VS_END

DEN **

DHS

DV_BKGND_START

DV_ACTIVE_START

DV_ACTIVE_LENGTH

DVS

DV_BKGND_END

DV_

TOTA

L

DH_HS_END

DH_BKGND_START DH_BKGND_END

DH_TOTAL

DH_ACTIVE_START

DH_ACTIVE_WIDTH

Vertical Blanking (Front Porch)H

oriz

onta

l Bla

nkin

g (F

ront

Por

ch)

** DEN is not asserted during vertical blanking

Figure 24. Display Windows and Timing

The double-wide output only supports an even number of horizontal pixels.

DCLK

DEN

XXXOR/OG/OB

rgb0 rgb4rgb3rgb2rgb1ER/EG/EB XXX

Figure 25. Single Pixel Width Display Data



46


Figure 26. Double Pixel Wide Display Data

DCLK

DEN

OR/OG/OB

rgb0 rgb8rgb6rgb4rgb2ER/EG/EB XXX

rgb1 rgb9rgb7rgb5rgb3XXX

4.14.3 LVDS Transmitter

Two LVDS channels (A and B) are available on the output of the gm160timing information to the display device.

The gm1601 provides a flexible implementation by which the data and arbitrarily mapped onto the LVDS data stream. As well the odd/even pixeeither channel in the case of dual channel operation.

A0

A1

A2

A3

B0

B1

B2

B3

(A/B)CPrevious Cycle Current Cycle

A0_BIT6 A0_BIT4 A0_BIT3 A0_BITA0_BIT5




B0_BIT6 B0_BIT4 B0_BIT3 B0_BITB0_BIT5




Figure 27. LVDS Signal Sequencing C1601-DAT-01F

*** Preliminary Information – Subject to Change *http://www.genesis-microchip.com

47

1 to transmit data and

timing signals may be ls may be assigned to

A0_BIT02 A0_BIT1

A1_BIT02 A1_BIT1

A3_BIT02 A3_BIT1

A2_BIT02 A2_BIT1

B0_BIT02 B0_BIT1

B1_BIT02 B1_BIT1

B3_BIT02 B3_BIT1

B2_BIT02 B2_BIT1

November 2003 **


As can be seen from the diagram, LVDS channel A0+/- has 7 bit locations which are: A0[6] to A0[0]. These bit locations have internal display signals mapped onto them to match the LVDS receiver interface of the display device being driven. The same is true for the B channel. The mapping of display signals onto LVDS channels and bit locations is programmable so that 24 data bits and the three control signals (HS, VS, DE) can be mapped onto the LVDS interface.

The LVDS transmitter may be configured to operate in DC and non-DC balance mode.

4.14.4 Panel Power Sequencing (PPWR, PBIAS)

The gm1601 has two dedicated outputs PPWR and PBIAS (balls A26 and B26) to control LCD power sequencing once data and control signals are stable. The timing of these signals is fully programmable.

PPWR Output

Panel Data and Control Signals

PBIAS Output

<State0> <State1> <State2> <State3> <State2> <State1> <State0>

TMG1 TMG2 TMG2 TMG1

POWER_SEQ_EN = 1 POWER_SEQ_EN = 0

Figure 28. Panel Power Sequencing

4.14.5 Output Dithering

The Gamma LUT outputs a 10-bit value for each color channel. This value is dithered down to either 8-bits for 24-bit per pixel panels, or 6-bits for 18-bit per pixel panels.

The benefit of dithering is that the human eye tends to average neighboring pixels and a smooth image free of contours is perceived. Dithering works by spreading the quantization error over neighboring pixels both spatially and temporally.

All gray scales are available on the panel output whether using 8-bit panel (dithering from 10 to 8 bits per pixel) or using 6-bit panel (dithering from 10 down to 6 bits per pixel).



48


44..1155 EEnneerrggyy SSppeeccttrruumm MMaannaaggeemmeenntt ((EESSMMTTMM))

High spikes in the electromagnetic interference (EMI) power spectrum can cause LCD monitor products to violate emissions standards. The gm1601 has features that can be used to reduce EMI. These include:

• LVDS transmitter • dual-edge clocking DDR memory interface • single crystal clock source • variable frequency display clock

These features eliminate the costs associated with EMI-reducing components and shielding.

44..1166 OOSSDD

The gm1601 has a fully programmable, true color bitmapped OSD controller capable of displaying up to 12 “tiles” or bitmap windows on the display. The individual tiles are programmable for location, size, and bits per pixel, and have a precedence determining which tiles appear when overlapping occurs on the display. Tile data is stored in the external framestore memory by the system controller in either: 1, 2, 4, or 8 bit per pixel format. On-chip table registers point to the start of tiles in external memory. Two programmable on-chip 256 x 24-bit color lookup tables are provided to map the OSD pixels onto a true 24 bit color space using the first table for one mapping, and the second table for an alternate mapping.

Some general features of the gm1601 OSD controller include:

OSD Position – The OSD menu is comprised of tiles can be positioned anywhere on the display region.

OSD Zoom – The OSD image can be stretched horizontally and vertically by a factor of two (this is not an independent zoom: either zoom both horizontal and vertical, or neither). Pixel and line replication is used to stretch the image.

OSD Blending – Sixteen levels of blending are supported for the bitmapped tiles. Blending can be enabled on a tile-by-tile basis. One host register controls the blend levels for pixels with LUT values of 128 and greater, while another host register controls the blend levels for pixels with LUT values of 127 and lower. OSD color LUT value 0 is reserved for transparency and is unaffected by the blend attribute.

Hi-Light Window – Two independent hi-light windows are available for each tile – hi-light window 1 and hi-light window 2. A hi-light window is specified as a start position and size in pixels and a 4-bit palette index register. A hi-light window is used to hi-light a selected section of a tile. This is achieved by modifying the color indices of pixels within the hi-light window. The hi-light window hardware allows a menu item to be hi-lighted by modifying a small number of SRAM-based registers as opposed to having to re-render the required pixels in SDRAM.



49


4.16.1 Color Look Up Tables (CLUT)

Each pixel of a displayed OSD data is resolved to an 8-bit color code. This selected color code is then transformed to a 24-bit value using a 256 x 24-bit look up table. This LUT is stored in an on-chip RAM. A second identical RAM exists for enabling the programmer to switch to another color definition. Color index value 0x00 is reserved for transparent OSD pixels.

44..1177 OOnn--CChhiipp MMiiccrrooccoonnttrroolllleerr ((OOCCMM))

The gm1601 on-chip micro-controller (OCM) serves as the system micro-controller. It programs the gm1601 and manages other devices in the system such as the keypad, the back light and non-volatile RAM (NVRAM) using general-purpose input/output (GPIO) pins.

The OCM can operate in Normal configuration as illustrated in Figure 29.

Factory Port

On-chip ROM: • Auto mode detection • Auto-configuration • OSD drawing functions • Factory test / calibration functions

Output to LCD Panel

PROM

Analog RGB Input

DVI Input

NVRAM

OCM

gm1601

User settings in NVRAM: • Brightness/contrast settings, etc • On mode-by-mode basis

External ROM: • Contains firmware code and data for all firmware functions • Standard high-quality OSD menus

Figure 29. OCM External Master and Normal Configurations

4.17.1 Normal Configuration

In normal configuration the OCM executes a firmware program running from external ROM, as well as driver-level (or Application Programming Interface – API) functions residing in internal ROM. This is illustrated above. A parallel port with separate address and data busses is available for this purpose. This port connects directly to standard, commercially available ROM or programmable Flash ROM devices in either 8 or 16-bit configurations. 128Kbytes or 256Kbytes of ROM is normally required.

To program the gm1601 with a normal configuration, both firmware and OSD content must be compiled into a HEX file and then loaded onto the external ROM. The OSD content is generated using Genesis Workbench. Genesis Workbench is a GUI based tool for defining OSD menus, navigation, and functionality. This is illustrated in Figure 30.



50


ROM Programmer

External ROM Image File (.hex)

Firmware source files (*.c *.h) OSD Workbench gm1601 Driver

OCM

ROM

Compiler

gm1601

Controller Board

Figure 30. Programming the OCM in normal Configuration

Genesis recommends using Paradigm C++ Pro (http://www.devtools.com) to compile the firmware source code into a hex file. This hex file is then downloaded into the external ROM using commercially available ROM programmers.

4.17.2 In-System-Programming (ISP) of Flash ROM Devices

The gm1601 has hardware to program Flash ROM devices. In particular, the OCM_WEn pin can be connected to the write enable of the Flash ROM. Firmware is then used to perform the writes using the gm1601 host registers.

4.17.3 External Chip Select Signals

The gm1601 provides three chip select signals for addressing external memory or devices. OCM_CS0n can be used in normal mode to address optional external RAM. OCM_CS1n, and OCM_CS2n can be used in normal mode to address external peripherals.

4.17.4 Interrupts

The gm1601 provides two external interrupt pins that can be used to interrupt the internal processor. They are provided on balls GPIO_30/OCM_INT1 (ball L2), and GPIO_10/OCM_INT2 (ball L1). The interrupts may be programmed for either active polarity.



51


4.17.5 JTAG Interface

A JTAG interface is provided to allow in-circuit debugging of the internal OCM via signals:

GPIO_G08_B5/JTAG_RESET ball AD8

GPIO_G08_B4/JTAG_TDO ball AF7

GPIO_G08_B2/JTAG_TDI ball AF6

GPIO_G08_B0/JTAG_CLK ball AD6

GPIO_G08_B1/JTAG_MODE ball AE6

4.17.6 UART Interface

The gm1601 OCM has an integrated Universal Asynchronous Remote Terminal (UART) port that can be used as a factory debug port. In particular, the UART can be used to 1) read / write chip registers, 2) read / write to NVRAM, and 3) read / write to FLASH ROM. The UART is connected to balls OCM_UDI (ball M2) and OCM_UDO (ball M1). Registers within the internal X186 controller determine the baud rate for serial communication.

4.17.7 DDC2Bi Interface

The gm1601 also features hardware support for DDC2Bi communication over the DDC channel of either the analog or DVI input ports. The specification for the DDC2Bi standard can be obtained from VESA (www.vesa.org). The DDC2Bi port can be used as a factory debug port or for field programming. In particular, the DDC2Bi port can be used to 1) read / write chip registers, 2) read / write to NVRAM, and 3) read / write to FLASH ROM.

Two pairs of pins are available for DDC2Bi communication. For DDC2Bi communication over the analog VGA connector pins VGA_SCL and VGA_SDA should be connected to the DDC clock and data pins of the analog DSUB15 VGA connector. For DDC2Bi communication over the DVI connector pins DVI_SCL and DVI_SDA should be connected to the DDC clock and data pins of the DVI connector. The gm1601 contains serial to parallel conversion hardware that is then accessed by firmware for interpretation and execution of the DDC2Bi command set.

Note that DDC2Bi can be active on only one of the inputs at a time.

4.17.8 General Purpose Inputs and Outputs (GPIO)

The gm1601 has 92 potential general-purpose input (GPI) and general-purpose input/output (GPIO) pins. Not all may be available depending on shared functionality of particular pins. These are used by the OCM to communicate with other devices in the system such as keypad buttons, NVRAM, LED, audio DAC, etc. Each GPIO has independent direction control, open drain enable, for reading and writing. Note that the GPIO pins have alternate functionality as described in Table 22 below.



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http://www.vesa.org)/


Table 21. gm1601 GPIs and Alternate Functions GPI Pin Name Pin Number Alternate function GPI_00 SVCLK D16 Pixel clock input for SV Port. GPI_01 VCLK A20 Pixel clock input for V Port. GPI_02 EXTCLK R4 External Clock input GPI_03 MSTR_SDA P3 Master serial interface for communicating with external serial slave peripherals. GPI_04 MSTR_SCL P4 Master serial interface for communicating with external serial slave peripherals. GPI_05 VGA_SDA N1 DDC Interface for DDC2Bi communication from a VGA connector GPI_06 VGA_SCL N2 DDC Interface for DDC2Bi communication from a VGA connector. GPI_07 DVI_SDA N3 DDC Interface for DDC2Bi communication from a DVI connector. GPI_08 DVI_SCL N4 DDC Interface for DDC2Bi communication from a DVI connector. GPI_09 ROM_CS R1 Chip select output signal to external rom during normal mode (OCM is bus master). GPI_10 OCM_INT2 L1 Interrupt #2 input for generating system interrupt to OCM.

Table 22. gm1601 GPIOs and Alternate Functions GPI0 Pin Name Pin Number Alternate function GPI0_00 SVODD A14 Field status input for interlaced sources driving SV Port GPI0_01 SVVSYNC B14 VSYNC input for SV Port GPI0_02 SVHSYNC C14 HSYNC input for SV Port GPI0_03 SVDV A17 Data Valid input for SV Port. Can be used as a qualifier for valid pixel samples GPI0_04 VHS_CSYNC D19 HSYNC input for V Port GPI0_05 VVSYNC C20 VSYNC input for VPort GPI0_06 VODD B20 Field status input for V port when input source is interlaced GPI0_07 VDV D20 Data valid input for V Port GPI0_08 PPWR A26 Panel Power Control output controlled by Panel Power On Sequencer (output only) GPI0_09 PBIAS B26 Panel Bias Control (Backlight Enable) controlled by Panel Power On Sequencer (output only) GPI0_10 PWM0 C26 Pulse Width Modulated output GPI0_11 PWM1 C25 Pulse Width Modulated output GPI0_12 PWM2 D26 Pulse Width Modulated output GPI0_13 OCM_TIMER D25 GPI0_14 DHS AF17 Output Display H-sync GPI0_15 DVS AD16 Output Display V-sync GPI0_16 DEN AD7 Output Display enable GPI0_17 DCLK AC7 Output Display Clock GPI0_18 OCMADDR7 W2 Address output during normal 8 bit or 16 bit mode (OCM is bus master). Address input during

external cpu (dual port sram slave i/f) 8 bit mode. GPI0_19 OCMADDR16 U4 Address output during normal 8 bit or 16 bit mode (OCM is bus master). GPI0_20 OCMADDR17 T1 Address output during normal 8 bit or 16 bit mode (OCM is bus master). GPI0_21 OCMADDR18 T2 Address output during normal 8 bit or 16 bit mode (OCM is bus master). GPI0_22 OCMADDR19 T3 Address output during normal 8 bit or 16 bit mode (OCM is bus master). GPI0_23 OCM_CS0 T4 Chip select output signal to external peripheral during normal mode (OCM is bus master).

Can be used to access larger address space for optional external ram. GPI0_24 OCM_CS1 P1 Chip select output signal to external peripheral during normal mode (OCM is bus master).

Chip select input signal to on chip dual port sram during external cpu mode. GPI0_25 OCM_CS2 P2 Chip select output signal to external peripheral during normal mode (OCM is bus master). Not

used during external cpu mode. GPI0_26 OCM_UD0 M1 OCM UART data output. GPI0_27 OCM_UD1 M2 OCM UART data input. GPI0_28 IR0 M3 Infra red input to IR Decoder #1. GPI0_29 IR1 M4 Infra red input to IR Decoder #2. GPI0_30 OCM_INT1 L2 Interrupt #1 input for generating system interrupt to OCM. GPI0_31 VCLAMP B17 Clamp enable output for V Port to control back porch clamping for an external ADC which

drives the V Port



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Furthermore, up to 6 of 12 GPIO groups may be enabled at any one time as GPIO’s. These group pins are shared with Data Out and OCM pins and may or may not be available depending on the system configuration. These groups and their shared pins are as follows:


GPIO_G00[7:0] (shared with SVDATA[7:0])

GPIO_G01 [7:0] (shared with VRED[7:0])

GPIO_G02 [7:0] (shared with VGRN[7:0])

GPIO_G03 [7:0] (shared with VBLU[7:0])

GPIO_G04 [7:0] available when in single-wide TTL EVEN port data output mode only (shared with output blue data pins) or anytime in LVDS mode.

GPIO_G05 [7:0] available when in single-wide TTL EVEN/LVDS output mode only (bits 1,2,4,5,6,7 shared with LVDS/output green data pins). Bits 7, 6, 5, 4, 2, and 1 are output only.

GPIO_G06 [7:0] available when in single-wide TTL EVEN/LVDS output mode only (bits 4,5,6,7 shared with LVDS/output red data pins, bits 0,1,2,3 are not shared and always available). Bits 7, 6, 5, and 4 are output only.

GPIO_G07 [7:0] available always in LVDS mode else available when in single-wide TTL ODD port output mode only (shared with output red data pins)

GPIO_G08 [5:0] available always in LVDS mode else available when in single-wide TTL EVEN port data output mode only (shared with JTAG and bits[1:0] of red, green, and blue data pins)

GPIO_G09 [5:0] available always in LVDS mode else available when in single-wide TTL ODD port output mode only (shared with bits[1:0] of red, green, and blue data pins)

GPIO_G10 [7:0] (shared with OCM_DATA[15:8])

GPIO_G11 [7:0] (shared with OCM_ADDR[15:8])

44..1188 BBoooottssttrraapp CCoonnffiigguurraattiioonn PPiinnss

During hardware reset, the external ROM address pins OCM_ADDR[19:0] are configured as inputs. On the rising edge of RESETn, the value on these pins is latched and stored. This value is readable by the on-chip microcontroller to provide system configuration information. This process is called “boot-strapping”.



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Table 23. Bootstrap Signals Signal Name Pin Name Description LATCHEDBOOT (7:0) OCM_ADDR(7:0) Latched from OCM_ADDR(7:0) to provide user information

XROM_CHK_BYP OCM_ADDR8 ‘0’ = Enable checking for valid external ROM signature

‘1’ = Disable checking for valid external ROM signature DDC2BI_SEL OCM_ADDR9 ‘0’ = Enable DDC2BI on DVI port

‘1’ = Enable DDC2BI on VGA port TCLK_SEL OCM_ADDR10 Select pad for input TCLK

‘0’ = TCLK pad/ball will source on chip TCLK after the oscillator ‘1’ = EXTCLK pad/ball will source TCLK

DISPLAYPORT_HIZ_SE (1:0)

OCM_ADDR(12:11) Defines Display Port Characteristics during Power On reset. 00 = DERED[9:0], DEGRN[9:0], DEBLU[9:0], DORED[9:0], DOGRN[9:0], DOBLU[9:0],

GPIO_G09_B[5:0], GPIO_G07_B[7:0], LVDS_SHIELD[5:0], B3+/-, B2+/-, B1+/-, B0+/-, BC+/-, GPIO_G08_B[5:0], GPIO_G06_B[7:0], GPIO_G05_B[7:0], GPIO_G04_B[7:0] are all driven with logic ‘0’ output during power on reset until the host register programming enables display output, or GPIO outputs.

01 = DERED[1:0], DEGRN[1:0], DEBLU[1:0], DORED[1:0], DOGRN[1:0], DOBLU[1:0]

are HiZ during power up reset and remain HiZ until enabled as GPIO’s, test bus outputs, or JTAG/ICD debug port. These pins, thereafter, are not available as LVTTL display port outputs.

GPIO_G09_B[5:0], GPIO_G08_B[5:0] are HiZ during power up reset and remain HiZ until enabled as GPIO’s, or JTAG debug port

10 = DERED[9:2], DERED[1:0], DEGRN[1:0], DEBLU[1:0], DORED[1:0], DOGRN[1:0],

DOBLU[1:0] are HiZ during power up reset and remain HiZ until enabled as GPIO’s, test bus outputs, or JTAG/ICD debug port. These pins, thereafter, are not available as LVTTL display port outputs.

GPIO_G09_B[5:0], GPIO_G08_B[5:0], GPIO_G07_B[7:0] are HiZ during power up reset and remain HiZ until enabled as GPIO’s, or JTAG debug port

11 = DORED[9:2], DOGRN[9:2], DOBLU[9:2] are HiZ during power up reset and remain

HiZ until enabled as GPIO’s or test bus outputs. These pins, thereafter, are not available as LVTTL display port outputs.

GPIO_G06_B[7:0], GPIO_G05_B[7:0], GPIO_G04_B[7:0] are HiZ during power up reset and remain HiZ until enabled as GPIO’s.

ICD_SEL_EN(2:0) OCM_ADDR(15:13) In Circuit Debugger Options.

000 = Serial interface to In Circuit Debugger disabled 001 / 101 = Enable OCM In Circuit Debugger JTAG signals to be mapped onto shared

function pins as follows: GPIO_G08_B4 = JTAG_TDO (101 = open-drain, 001 = active drive) GPIO_G08_B1 = JTAG_MODE GPIO_G08_B0 = JTAG_TCLK GPIO_G08_B2 = JTAG_TDI GPIO_G08_B5 = JTAG_RESET 010 / 100 / 110 / 111 = Reserved

INT_OSC OCM_ADDR16 Internal Oscillator Enable ‘0’ = External oscillator connection ‘1’ = Crystal connection

PERIPHERAL_SEL(2:0) OCM_ADDR(19:17) 000 = 16 bit data bus for OCM access to external peripherals (including external ROM access).

010 = 8-bit data bus for OCM access to external peripherals (including external ROM access).

001, 011, 100, 101, 110, 111 = Reserved



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Note: Install a 10K pull-up resistor to indicate a ‘1’, or a pull-down resistor to indicate a ‘0’. Bootstrap pins must never be left floating in a design.

44..1199 HHoosstt RReeggiisstteerr IInntteerrffaaccee

The gm1601 contains many internal registers that control its operation. These are described in the gm1601 Register Listing (C1601-DSL-01).

These registers are mapped directly into the on chip micro-controller’s memory space see gm1601 register listing for description of the OCM memory map and register descriptions.

44..2200 MMiisscceellllaanneeoouuss FFuunnccttiioonnss

4.20.1 2-wire Master Serial Protocol

The 2-wire protocol consists of a serial clock MSTR_SCL (ball number P4) and bi-directional serial data line MSTR_SDA (ball number P3). The gm1601 acts as bus master and drives MSTR_SCL and either the master or slave can drive the MSTR_SDA line (open drain) depending on whether a read or write operation is being performed.

The 2-wire protocol requires each slave device to be addressable by a 7-bit identification number.

A 2-wire data transfer consists of a stream of serially transmitted bytes formatted as shown in the figure below. A transfer is initiated (START) by a high-to-low transition on MSTR_SDA while MSTR_SCL is held high. A transfer is terminated by a STOP (a low-to-high transition on MSTR_SDA while MSTR_SCL is held high) or by a START (to begin another transfer).

ADDRESS BYTE

MSTR_SDA

1 2 3 7 8 9MSTR_SCL 4 5 6 1 2 8 9

DATA BYTE

ACK ACK

START STOP

Receiver acknowledges by holding SDA low

R/WA6 A1A2A3A4A5 A0 D6D7 D0

Figure 31. 2-Wire Protocol Data Transfer

Each transaction on the MSTR_SDA is in integer multiples of 8 bits (i.e. bytes). The number of bytes that can be transmitted per transfer is unrestricted. Each byte is transmitted with the most significant bit (MSB) first. After the eight data bits, the master releases the MSTR_SDA line and the receiver asserts the MSTR_SDA line low to acknowledge receipt of the data. The master device generates the MSTR_SCL pulse during the acknowledge cycle. The addressed receiver is obliged to acknowledge each byte that has been received.



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lifeng

Note

写控制连续协议



4.20.2 Power Down Operation

The gm1601 provides a low power state in which the clocks to selected parts of the chip may be disabled.

4.20.3 Pulse Width Modulation (PWM) Backlight Control

Many of today’s LCD backlight inverters require both a PWM input and variable DC voltage to minimize flickering (due to the interference between panel timing and inverter’s AC timing), and adjust brightness. Most LCD monitor manufacturers currently use a micro-controller to provide these control signals. To minimize the burden on the external micro-controller, the gm1601 generates these signals directly.

There are three pins available for controlling the LCD backlight, PWM0 (GPIO10), PWM1 (GPIO11) and PWM2 (GPIO12). The duty cycle of these signals is programmable. They may be connected to an external RC integrator to generate a variable DC voltage for a LCD backlight inverter, or may control the inverter directly using pulse width modulation. Panel HSYNC is used as the clock for a counter generating this output signal.

Also there is an additional PWM3 output that can be enabled. It is shared with OCM_TIMER1 function on ball D25.

4.20.4 Low Bandwidth ADC

A low bandwidth ADC is integrated to allow for functions such as keypad scanning or for monitoring system temperature or voltage sensors. The ADC has 8 bits of resolution, and can perform a conversion in 13 TCLK periods (approximately 1 µsec). An analog multiplexer selects one of three analog input pins as the input to the ADC.

4.20.5 Infrared receivers

Two infrared receivers are integrated to allow for the reception of infrared signals from remote control units. Standard protocols are supported such as RECS 80 and RC5. As well the ability exists to analyze raw signal streams for custom protocols. Optional carrier filtering is available.



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5. ELECTRICAL SPECIFICATIONS

55..11 PPrreelliimmiinnaarryy DDCC CChhaarraacctteerriissttiiccss

Table 24. Absolute Maximum Ratings PARAMETER SYMBOL MIN TYP MAX UNITS 3.3V Supply Voltages (1,2) VVDD_3.3 -0.3 3.6 V 2.5V Supply Voltages (1,2) VVDD_2.5 -0.3 2.75 V 1.8V Supply Voltages (1,2) VVDD_1.8 -0.3 1.98 V Input Voltage (5V tolerant inputs) (1,2) VIN5Vtol -0.3 5.5 V Input Voltage (non 5V tolerant inputs) (1,2) VIN -0.3 3.6 V Electrostatic Discharge (3) VESD ±2.0 kV Latch-up ILA ±100 mA Ambient Operating Temperature TA 0 70 °C Storage Temperature TSTG -40 125 °C Operating Junction Temp. (4) TJ 0 125 °C Thermal Resistance (Junction to Air) Natural Convection (5) θJA_1601 16.2 °C/W Thermal Resistance (Junction to Case) Convection θJC_1601 6.5 °C/W Soldering Temperature (30 sec.) (6) TSOL 210 °C -LF -- Soldering Temperature (30 sec.) (6) TSOL 250 °C

NOTE (1): All voltages are measured with respect to GND NOTE (2): Absolute maximum voltage ranges are for transient voltage excursions. NOTE (3): Human Body Model testing with all grounds tied together. +/-1 kV when all grounds are not tied together. PCB-level ESD considerations can be found in the System Layout Guidelines Application Note - C1601-SLG-01.

NOTE (4): Based on the figures for the Operating Junction Temperature, θJC and Power Consumption in Table 27, the typical case temperature is calculated as TC = TJ – P1601 x θJC. NOTE (5): Package thermal resistance is based on a PCB with one signal plane and two power planes. Package θJA is improved on a PCB with four or more layers NOTE (6): Solder Reflow Profiles, Fig. 39 and 40



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Table 25. DC Characteristics PARAMETER SYMBOL MIN TYP MAX UNITS

POWER Power Consumption @ Low Power Mode (1) PLP 0.09 W 3.3V Supply Voltages (AVDD and RVDD) VVDD_3.3 3.15 3.30 3.45 V 2.5V Supply Voltages (VDD and CVDD) VVDD_2.5 2.35 2.50 2.65 V 1.8V Supply Voltages (VDD and CVDD) VVDD_1.8 1.70 1.80 1.90 V Supply Current (WUXGA output) 2.5V digital supply 3.3V digital supply

3.3V analog supply

1.8V digital supply

1.8V analog supply

I1601_2.5_VDD

I1601_3.3_VDD

I1601_3.3_AVDD

I1601_1.8_VDD

I1601_1.8_AVDD

50(2)

130(2) 190(2)

630(2) 40(2)

mA

Supply Current (WXGA output) 2.5V digital supply 3.3V digital supply

3.3V analog supply

1.8V digital supply

1.8V analog supply

I1601_2.5_VDD

I1601_3.3_VDD

I1601_3.3_AVDD

I1601_1.8_VDD

I1601_1.8_AVDD

50(3) 85(3)

160(3)

515(3) 30(3)

mA

INPUTS High Voltage VIH 2.0 VDD V Low Voltage VIL GND 0.8 V Clock High Voltage VIHC 2.4 VDD V Clock Low Voltage VILC GND 0.4 V High Current (VIN = 5.0 V) IIH -25 25 µA Low Current (VIN = 0.8 V) IIL -25 25 µA Capacitance (VIN = 2.4 V) CIN 8 pF

OUTPUTS High Voltage (IOH = 7 mA) VOH 2.4 VDD V Low Voltage (IOL = -7 mA) VOL GND 0.4 V Tri-State Leakage Current IOZ -25 25 µA

NOTE (1): Low power figures result from setting the ADC, DVI, and clock power down bits so that only the micro-controller is running at the TCLK rate of 14.31818 MHz. NOTE (2): Current figures are provided for the purposes of designing appropriate power supply circuitry. Test conditions are as follows: Display input is SXGA @ 85 Hz with ON/OFF pattern and NTSC video input. Display output is WUXGA @ 60 Hz, graphics input zoomed to full screen, with ¼ screen video PIP. All blocks were fully powered during testing. NOTE (3): Current figures are provided for the purposes of designing appropriate power supply circuitry. Test conditions are as follows: Display input is SXGA @ 75 Hz with ON/OFF pattern and NTSC video input. Display output is WXGA @ 60 Hz, graphics input zoomed to full screen, with ¼ screen video PIP. All blocks were fully powered during testing.



59


55..22 PPrreelliimmiinnaarryy AACC CChhaarraacctteerriissttiiccss

All timing is measured to a 1.5V logic-switching threshold. The minimum and maximum operating conditions used were: TDIE = 0 to 125° C, VDD18 = 1.70 to 1.90V, VDD25 = 2.35 to 2.65, VDD33 = 3.15 to 3.45V Process = best to worst, CL = 16pF for all outputs unless otherwise indicated.

Table 26. Maximum Speed of Operation Clock Domain Max Speed of Operation

Main Input Clock (TCLK) 14.318 MHz Required DVI Differential Input Clock 165 MHz ADC Clock (SCLK) 165 MHz VPORT Clock 133 MHz SVPORT Clock 75 MHz 2-wire protocol Clock 400 KHz Input Format Measurement Clock (IFM_CLK) 50MHz Reference Clock (RCLK) 200MHz On-Chip Microcontroller Clock (OCM_CLK) 100 MHz Memory Clock (MCLK) 172 MHz Display Clock (DCLK) 165 MHz

Table 27. 2-Wire Interface Port Timing Parameter Symbol MIN TYP MAX Units SCL HIGH time TSHI 1.25 us SCL LOW time TSLO 1.25 us SDA to SCL Setup TSDIS 30 ns SDA from SCL Hold TSDIH 20 ns Propagation delay from SCL to SDA TSDO3 10 150 ns Note: The above table assumes OCM_CLK = R_CLK / 2 = 100 MHz (default) (ie 10ns / clock)



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VCLK

VDATA/CTRL

TsVCLK PL TsVCLK PH

TVP SU TVP HD

Figure 32. 24-bit VPORT Timing

Table 28. 24-bit VPORT Timing Parameter Symbol MIN TYP MAX Units Data / Control Setup to VCLK edge (VHS, VVS, VODD, Vxxx[7:0])

TVP_SU 2.0 ns

Data / Control Hold time from VCLK edge TVP_HD 1.0 ns

VCLK high pulse width period TVCLK_PH 3.0 ns

VCLK low pulse width period TVCLK_PL 3.0 ns

VCLK max frequency (When Vport selected for ITU 656 decoder, maximum frequency limited to 75 MHz)

FVCLK 133 MHz

VCLK edge is programmable to be rising or falling edge

SVCLK

SVDATA/CTRL

TSVP PL TSVP PH

TSVP SU TSVP HD

Figure 33. SVPORT Timing

Table 29. SVPORT Timing Parameter Symbol MIN TYP MAX Units Data / Control Setup to SVCLK edge (SVHS, SVVS, SVODD, SVxxx[7:0])

TSVP_SU 2.0 ns

Data / Control Hold time from SVCLK edge TSVP_HD 1.0 ns

VCLK high pulse width period TSVCLK_PH 5.0 ns

VCLK low pulse width period TSVCLK_PL 5.0 ns

SVCLK max frequency FVVCLK 75 MHz

SVCLK edge is programmable to be rising or falling edge



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DCLK

DATA/CTRL

TDCLK DC

TDISP PD (max)

TDISP PD (min)

Figure 34. DPORT Timing

Table 30. DPORT Timing Parameter Symbol MIN TYP MAX Units Data / Control Propagation Delay from DCLK. ODPEXT_OUT_TIMING[1:0] = “00” ODPEXT_OUT_TIMING[1:0] = “01” ODPEXT_OUT_TIMING[1:0] = “10” ODPEXT_OUT_TIMING[1:0] = “11”

TDISP_PD 0.0 -1.0 -2.0 -3.0

4.0 3.0 2.0 1.0

ns

DCLK Output Duty Cycle TDCLK_DC 40 60 % (percent)

DCLK Frequency (Single Wide Display) FDCLK_SW 165 MHz

DCLK Frequency (Double Wide Display) FDCLK_DW 82.5 MHz

DCLK edge is programmable to be rising or falling edge

Read Cycle Write Cycle

TRLPW TRAH

A(19:1)

OCM_REn

OCM_WEn

D(15:0)

TBCD/OCM_CS0,/OCM_CS1,/OCM_CS2

TRAS

TWAS TWLPW TWAH

TRDH TWDS TWDH

FROM EXTERNAL DEVICE TO EXTERNAL DEVICE

TBCD

TRDD

TWLZ

TWHZ

Figure 35. OCM PORT (On-chip Turbo186 as Bus Master)



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Table 31. OCM PORT (On-chip Turbo186 as Bus Master) Parameter Symbol MIN TYP MAX Units On chip OCM clock period. TOCMCLK 10 ns Address setup time provided to falling edge of OCM_WEn.

TOCM_WAS K1(TOCMCLK) – 3 ns

Address hold time provided from rising edge of OCM_WEn.

TOCM_WAH TOCMCLK – 3 ns

OCM_WEn active low pulse width TOCM_WLPW K2 (TOCMCLK) ns OCM_DATA valid time to OCM_WEn rising edge (data set-up time provided)

TOCM_WDS K2(TOCMCLK) – 3 ns

OCM_DATA held valid from OCM_WEn rising edge. (data hold time provided)

TOCM_WDH TOCMCLK – 3 ns

OCM_DATA Low-Z after OCM_WEn falling edge. TOCM_WLZ -2.0 3.0 ns OCM_DATA Hi-Z after OCM_WEn rising edge. TOCM_WHZ TOCMCLK – 3 TOCMCLK + 3 ns Address setup time provided to falling edge of OCM_REn.

TOCM_RAS (TOCMCLK) – 3 ns

Address hold time provided from rising edge of OCM_REn.

TOCM_RAH TOCMCLK – 3 ns

OCM_REn low pulse width TOCM_RLPW K2 (TOCMCLK) ns Read data valid before OCM_REn rising edge. TOCM_REnD 10 ns Read data hold after OCM_REn rising edge. TOCM_REnH 0 ns Read access delay to avoid bus contention on data lines. TOCM_BCD K3 (TOCMCLK) ns

CL for OCM_ADDR[19:0] and OCM_DATA[15:0] = 32 pF

K1: is number of OCMCLK clocks determined by programmed value for host register bits: XCS0_WR_AS,

XROM_WR_AS, XCS1_WR_AS, XCS2_WR_AS.

K2: is number of OCMCLK clocks determined by programmed value for host register bits: XROM_WAIT_STATE, XCS0_WAIT_STATE, XCS1_WAIT_STATE, XCS2_WAIT_STATE.

K3: is number of OCMCLK clocks determined by programmed value for host register bits: ROMCS_TO_HIZ_DELAY, XCS0_TO_HIZ_DELAY, XCS1_TO_HIZ_DELAY, XCS2_TO_HIZ_DELAY. The programmed delay is inserted if necessary to ensure that the minimum number of OCMCLK periods occur between one of ROM/CS0/CS1/CS2 being read and the next ROM/CS0/CS1/CS2 so that devices can tri-state their data lines before the next selected device drives the data bus.



63


tDQSD(max)

tWPST

tDQSS

tAP(min)

tAP(min)

tAP(max)

NOP ACT NOP WRITE NOP NOP NOP NOP NOP NOP NOP

CK-

CKE

CK+

Command

Addr

BankAddr

tAP(min)

tAP(max)

tAP(min)tAP(max)

RA

Bank x

Col n

Bank x

tAP(max)

DQS

tCH tCL

tDQSH tDQSL

tWPRE

tDP(min)

tDP(max)

tDQSD(min)

DQ

DM

Figure 36. Frame store Write Timing

Table 32. DDR Interface Write Timing Parameter Symbol MIN TYP MAX Units Clock Period tCK 5.8 ns

Clock High Width tCH 0.45 0.55 tCK

Clock Low Width tCL 0.45 0.55 tCK

Address/Command Propogation tAP 2 4.5 ns

Write command to first DQS latching transition tDQSS 0.75 1.25 tCK

DQS high pulse width tDQSH 0.4 0.6 tCK

DQS low pulse width tDQSL 0.4 0.6 tCK

DQS Write Preamble tWPRE 0.75 tCK

DQS Write Postamble tWPST 0.4 0.6 tCK

DQS-to-Data/DM Propagation tDQSD 0.75 2.5 ns

Clock-to-Data/DM Propagation tDP 0.75 2.5 ns

Conditions: For All DDR pins the CLOAD = 8 pF.



64


tAP(min)

tAP(min)

tAP(max)

NOP ACT NOP READ NOP NOP NOP NOP NOP NOP NOP

CK-

CKE

CK+

Command

Addr

BankAddr

tAP(min)

tAP(max)

tAP(min)tAP(max)

RA

Bank x

Col n

Bank x

tAP(max)

DQS

tCH tCL

tDQSQ

tQH

DQ

Figure 37. Frame store Read Timing

Table 33. DDR Interface Read Timing Parameter Symbol MIN TYP MAX Units Clock High Width tCH 0.45 0.55 tCK

Clock Low Width tCL 0.45 0.55 tCK

Address/Command Propogation tAP 2 4.5 ns

DQS-to-DQ Max Skew tDQSQ 0.5 ns

DQ-to-DQS Min Hold tQH 0.25 tCK + 0.46 ns

Conditions: For All DDR pins the CLOAD = 8 pF.



65


6. ORDERING INFORMATION

Order Code

Application Package Temperature Range

gm1601-BD WUXGA 416 PBGA 0-70°C gm1601-LF-BD WUXGA 416 PBGA 0-70°C



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7. MECHANICAL SPECIFICATIONS

Figure 38. gm1601 416 PBGA Mechanical Drawing

C1601-DAT-01F 67 November 2003 *** Preliminary Information – Subject to Change ***



8. SOLDER REFLOW PROFILES

Figure 39. gm1601 416 PBGA Solder Reflow Profile (Non-Lead-Free)

Peak temperature* 210C +5C/-0C < 10 secs

Time above 180C: 50 to 80 secs max

0.5 to 0.9 C / sec

Pre-heat temperature: 130 C +/- 15C 60 to 120 secs

0.8 to 1.2 C / sec

≤ 6°C/SEC

220

150

130

Regular PBGA max temperature = 210C +5C/-0C




Figure 40. gm1601-LF 416 PBGA Solder Reflow Profile (Lead-Free)

Pre-heat temperature: 155 C +/- 15C 50 to 65 secs

Time above 220C: 75 secs max

≤ 6°C/SEC

Peak temperature* 250C +0C/-5C < 10 secs

0.8 to 1.2 C / sec

1 to 5 C / sec

250

200

150

100

50

Lead-Free PBGA max temperature = 250C +0C/-5C



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gm1601 LCD TV/Monitor Controller - read.pudn.comread.pudn.com/downloads161/doc/project/728929/1601-DataSheet-01F.pdf · PRELIMINARY DATA SHEET gm1601 LCD TV/Monitor Controller C1601-DAT-01F