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Marquette University
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COEN-4710 Computer Hardware
Lecture 3
Processor Part 1: Datapath and Control (Ch.4)
Cristinel Ababei
Marquette University
Department of Electrical and Computer Engineering
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Marquette University
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Goals of this Chapter
❖Design a datapath and control that implement
the RISC-V instruction set architecture (ISA).
❖By the end of this chapter, you should:
◆Be able to design a datapath for an instruction set
◆Be able to design a control logic for the datapath
◆Understand the importance of the clocking
methodology on the processor design
❖We will examine two RISC-V implementations◆A simplified version
◆A more realistic pipelined version
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What are datapath and control?
❖ Datapath
◆The path the “data” follow and undergo computations.
◆Realized by the hardware components connected in a way to
perform operations on data such that machine instructions are
implemented.
❖ Control
◆Control is the sequential logic that reconfigures the Datapath to
allow the “data” to flow properly through the hardware
components.
◆Responsible with the generation of all control signals to
“orchestrate” the correct flow of data through Datapath!
◆Can be implemented as finite state-machine(s).
◆Can also be implemented as a computer inside of a computer
(microcode).
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Design Process
1. Select a subset of the instruction set to
implement. Simple subset, shows most
aspects◆Memory reference: ld, sd
◆Arithmetic/logical: add, sub, and, or
◆Control transfer: beq
2. Order the steps within instruction cycle
(performed during instruction execution)
3. Select the hardware components.
4. Connect the hardware components.
5. Design the control to make the components
work together properly.
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Order the steps: F I D E
❖ FIDE – the sequence of activities that
happens during instruction execution
1. Fetch (the instruction)
2. “Increment” (the Program Counter)
3. Decode (the Instruction Register)
4. Execute (using datapath hardware)
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Fetch and Increment Hardware
PC
Instruction
MemoryInstruction
address
Instruction
Adder
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Fetch and Increment Connections
PCInstruction
MemoryInstruction
addressInstruction
Adder
4
64-bit
register
Increment by
4 for next
instruction
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Decode and Execute
❖Decode
◆Takes the Instruction Register (IR) and computes
the bits needed to control the datapath (R/W flags,
enables, mux selects, etc.)
◆We will work more on the control later
❖Execute
◆Take the inputs specified by the instruction, and
complete the required operation
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Instruction Execution
❖PC → instruction memory, fetch instruction
❖Register numbers → register file, read
registers
❖Depending on instruction class
◆Use ALU to calculate
➢Arithmetic result
➢Memory address for load/store
➢Branch comparison
◆Access data memory for load/store
◆PC target address or PC + 4
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R-format Example: “ADD” Instruction
add x9,x20,x21
❖ For the execute step of FIDE, what hardware
do we need?
funct7 rs2 rs1 rdfunct3 opcode
7 bits 7 bits5 bits 5 bits 5 bits3 bits
0 21 20 90 51
0000000 10101 10100 01001000 0110011
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R-Format Instructions - Hardware
❖Read two register operands
❖Perform arithmetic/logical operation
❖Write register result
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With Hardware Connections
ALUzero
result
rs1 [19-15]
rs2 [24-20]
rd [11-7]
Registers
read reg1
read reg2
write reg
write data
read data2
read data1
0010
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12
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Complete “Add” Datapath
ALUzero
result
Registers
read reg1
read reg2
write reg
write data
read data2
read data1
PC
Instruction
Memory
Adder
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Complete Add Datapath
ALUzero
result
Registers
read reg1
read reg2
write reg
write data
read data2
read data1
PC
Instruction
Memory
Adder
4
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Complete Add Datapath
ALUzero
result
Registers
read reg1
read reg2
write reg
write data
read data2
read data1
PC
Instruction
Memory
Adder
4
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Complete Add Datapath
ALUzero
result
Registers
read reg1
read reg2
write reg
write data
read data2
read data1
PC
Instruction
Memory
Adder
4
rs1 [19-15]
rs2 [24-20]
rd [11-7]
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16
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Complete Add Datapath
ALUzero
result
Registers
read reg1
read reg2
write reg
write data
read data2
read data1
0010
PC
Instruction
Memory
Adder
4
rs1 [19-15]
rs2 [24-20]
rd [11-7]
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Complete Add Datapath
ALUzero
result
Registers
read reg1
read reg2
write reg
write data
read data2
read data1
0010
PC
Instruction
Memory
Adder
4
rs1 [19-15]
rs2 [24-20]
rd [11-7]
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Control of R-format Instructions
❖ Simplicity favors regularity!
◆and, or, add, subtract, set-on-less-than all use the same
datapath
❖ Need to decode the instructions to control the ALU.
◆ Input: Function codes for each (recall from Chapter 2)
◆Output: ALU control lines (will look at later)
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ALU Decoding for R-format
ALU
Control
zero
resultALU
rs1 [19-15]
rs2 [24-20]
rd [11-7]
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R-format Datapath and Control
Registers
read reg1
read reg2
write reg
write data
read data2
read data1
PC
Instruction
Memory
Adder
ALU
Control
zero
resultALU
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R-format Datapath and Control
Registers
read reg1
read reg2
write reg
write data
read data2
read data1
PC
Instruction
Memory
Adder
4ALU
Control
zero
resultALU
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R-format Datapath and Control
Registers
read reg1
read reg2
write reg
write data
read data2
read data1
PC
Instruction
Memory
Adder
4ALU
Control
zero
resultALU
rs1 [19-15]
rs2 [24-20]
rd [11-7]
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R-format Datapath and Control
Registers
read reg1
read reg2
write reg
write data
read data2
read data1
PC
Instruction
Memory
Adder
4ALU
Control
zero
resultALU
rs1 [19-15]
rs2 [24-20]
rd [11-7]
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R-format Datapath and Control
Registers
read reg1
read reg2
write reg
write data
read data2
read data1
PC
Instruction
Memory
Adder
4ALU
Control
zero
resultALU
rs1 [19-15]
rs2 [24-20]
rd [11-7]
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R-format Datapath and Control
Registers
read reg1
read reg2
write reg
write data
read data2
read data1
PC
Instruction
Memory
Adder
4ALU
Control
zero
resultALU
rs1 [19-15]
rs2 [24-20]
rd [11-7]
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R-format Datapath and Control
Registers
read reg1
read reg2
write reg
write data
read data2
read data1
PC
Instruction
Memory
Adder
4ALU
Control
zero
resultALU
rs1 [19-15]
rs2 [24-20]
rd [11-7]
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Load/Store Instructions - Hardware
❖Read register operands
❖Calculate address using 12-bit offset◆Use ALU, but sign-extend offset
❖Load: Read memory and update register
❖Store: Write register value to memory
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I-format Instructions
❖ Immediate arithmetic and load instructions◆ rs1: source or base address register number
◆ immediate: constant operand, or offset added to base address
➢ 2s-complement, sign extended
immediate rs1 rdfunct3 opcode
12 bits 7 bits5 bits 5 bits3 bits
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S-format Instructions
❖ Different immediate format for store instructions◆ rs1: base address register number
◆ rs2: source operand register number
◆ immediate: offset added to base address
➢ Split so that rs1 and rs2 fields always in the same place
rs2 rs1 funct3 opcode
7 bits 7 bits5 bits 5 bits 5 bits3 bits
imm[11:5] imm[4:0]
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Composing the Elements
❖First-cut datapath does an instruction in one
clock cycle
◆Each datapath element can only do one function
at a time
◆Hence, we need separate instruction and data
memories
❖Use multiplexers where alternate data
sources are used for different instructions
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R-Type/Load/Store Datapath
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Branch Instructions
❖Read register operands
❖Compare operands
◆Use ALU, subtract and check Zero output
❖Calculate target address
◆Sign-extend displacement
◆Shift left 1 place (halfword displacement)
◆Add to PC value
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SB-format - Branch Addressing
❖SB format:
◼ PC-relative addressing
◼ Target address = PC + immediate × 2
rs2 rs1 funct3 opcodeimm
[10:5]imm[4:1]
imm[12] imm[11]
❖Branch to a labeled instruction if a condition is true◆Otherwise, continue sequentially
❖beq rs1, rs2, L1◆if (rs1 == rs2) branch to instruction labeled L1
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Branch Instructions
Just
re-routes
wires
Sign-bit wire
replicated
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R-Type/Load/Store Datapath
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Full Datapath
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Overall Control
❖Divide and conquer
1. “ALU Control” unit
➢Uses 2-bit ALUOp generated by Main Control unit
➢Generates output that controls directly the function
executed by the ALU
2. “Main Control” unit
➢Control signals derived from instruction
➢Generates a 2-bit ALUOp used by ALU Control
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1) “ALU Control” unit
❖ALU used for
◆Load/Store: F = add
◆Branch: F = subtract
◆R-type: F depends on opcode
“ALU control” Function
0000 AND
0001 OR
0010 add
0110 subtract
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ALU Control
❖ Generates “ALU Control” signals
◆Based on inputs: ALUOp, Funct7, and Funct3 field of instruction
❖ 2-bit ALUOp derived from opcode by “Main Control” unit
❖ Can be implemented by simple combinational logic
◆By logic synthesis from Truth Table on next slide
Opcode ALUOp Operation Opcode field ALU function
ALUOperat
ion
ld 00 load register XXXXXXXXXXX add 0010
sd 00 store register XXXXXXXXXXX add 0010
beq 01 branch on equal XXXXXXXXXXX subtract 0110
R-type 10 add 100000 add 0010
subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
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ALU Control – Truth Table
❖ Input signals:
◆ALUOp (2 bits), Funct7 (7 bits, Instruction[31-25], Funct3 (3 bits,
Instruction [14-12])
❖ Output signals:
◆ALU Operation (4 bits)
❖Table from Figure 4.13 in Textbook
ALUOperat
ion
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2) “Main Control” unit
❖ Generates control signals for: Register file, data
memory, multiplexers, AND gate (branch related),
ALUOp (2 bits), etc. (will see more later)
❖ Control signals derived from instruction opcode
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❖Table from Figure 4.22 in Textbook
❖ Input signals:
◆Opcode (7 bits, Instruction [6-0])
❖ Output signals:
◆ALUSrc, MemtoReg, RegWrite, etc.
Main Control – Truth Table
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Datapath With Control
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R-Type Instruction
Instr.[31-25,14-12]
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Load Instruction
Instr.[31-25,14-12]
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BEQ Instruction
Instr.[31-25,14-12]
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❖ All of the logic is combinational (“Single cycle”)
❖We wait for everything to settle down, and the right
thing to be done
◆ We use write signals along with clock to determine when to write
❖ Cycle time determined by length of the longest path
Review Control Structure
Note: We are ignoring some details like setup and hold times
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Practice – Performance Analysis❖ Calculate cycle time assuming:
◆ memory (2ns), ALU and adders (2ns), register file access (1ns)
Instr.[31-25,14-12]
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Limitations of single-cycle operations
❖Each instruction uses the ENTIRE datapath,
until it finishes.
◆Clock cycle time based on slowest instruction
◆What if we add more stuff, like floating-point?➢ Worst-case time delay drastically exceeds average
➢ Need really long cycle time to accommodate
❖Goal: Use as much of the hardware as much
of the time as possible◆PIPELINING: Break the datapath into smaller chunks, and let
new instructions start while others are finishing
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