Good 80511

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The MOST 80C51 Derivatives in the World

PhilipsSemiconductors

PHILIPS

80C51Microcontrollers:

A Technical Overiew

PHILIPSPHILIPS

80C5180C51Microcontrollers:Microcontrollers:

A Technical OveriewA Technical Overiew

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AgendaAgendaAgenda

1. 80C51 Basics– Features– Memory– Reset– Special Function

Registers– PSW

– I/O Ports– Timer/Counters– UART Serial

Interface– Interrupts– PCON

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Agenda (Cont'd)Agenda (Cont'd)(Cont'd)

2. 80C51 Instruction Set– Arithmetic– Logic– Data Transfer– Branching

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Part 1

80C51: The Basics

Part 1Part 1

80C51: The Basics80C51: The Basics

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80C51 Features80C51 Features80C51 Features• 8-bit data path and ALU• 16 thru 40 MHz versions available• Easy interfacing• Full instruction set including:

– Multiply and Divide– Bit set, reset, and test

• Variety of addressing modes

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80C51 Features (Cont'd)80C51 Features80C51 Features (Cont'd)(Cont'd)

• 4k X 8 ROM - Program memory

• 128 x 8 RAM - Data memory

• Special Function Registers

• Serial I/O port

• 32 I/O lines

• Two 16-bit counter/timers

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80C51 Logic Symbol80C51 Logic Symbol80C51 Logic SymbolVSS VCC RST

P0.7P0.6P0.5P0.4P0.3P0.2P0.1P0.0

P OR T 0

Addressand

Data Bus

XTAL1

XTAL2

ALE

EA

PSEN

P3.7P3.6P3.5P3.4P3.3P3.2P3.1P3.0

RxDTxDINT0INT1T0T1WRRD

P O R T 3

P2.7P2.6P2.5P2.4P2.3P2.2P2.1P2.0

P O R T 2

Address Bus

P1.7P1.6P1.5P1.4P1.3P1.2P1.1P1.0

P O R T 1

SecondaryFunctions

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80C51 Block Diagram80C51 Block Diagram80C51 Block Diagram

Interrupt Control

External Interrupts

CPU

OSC

Timer 1

Timer 0

SerialPortI/O Ports

BusControl

CounterInputs

P0 P3P1

4k byteROM

128 byteRAM

P2(Address/Data)

TXD RXD

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Addressing SpaceAddressing SpaceAddressing Space

• 64k X 8 ROM - Program Memory

• 64k x 8 RAM - External Data Memory

• 256 x 8 RAM - Internal Data Memory

• 128 x 8 - Special Function Registers (SFRs)

• Bit Addressing of 16 RAM locations and 16SFRs

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Memory OrganizationMemory OrganizationMemory Organization64K

00

255

1284K

64K

ExternalProgramMemory

InternalData Ram

ExternalData Ram

SpecialFunctionRegisters

0FFFFH

00H

80H

FFH

DirectlyAddressable

000H000H000H

1277FH Directly orIndirectlyAddressable

IndirectlyAddressable

whenImplemented80H

FFH 255

128

InternalProgramMemory

0FFFFH

4K0FFFH

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Program MemoryProgram MemoryProgram Memory• 64k byte Address Space

• 16-bit Program Counter

• 16-bit Data Pointer

• Table lookup using relative addressing:– PC + ACC

– DPTR + ACC (also a jump)

• EA pin disables internal ROM and activatesexternal program memory and addressing

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Internal Data MemoryInternal Data MemoryInternal Data Memory

• 128 bytes of RAM

• Directly addressable range - 00 to 7Fhexadecimal

• Indirectly addressable range - 00 to FFhexadecimal

• Bit addressable space - 20 to 2F hexadecimal

• Four register banks - 00 to 1F hexadecimal

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Internal Data MemoryInternal Data MemoryInternal Data Memory

7F

30

2F

20

R0

R1

R2

R3

R4

R5

R6

R7

Register Bank 1

Register Bank 2

End 80C51 Ram

Bit Addressable

Register Bank 3

00

1F

0F

17

18

08

07

20

Register Bank 0

07 . . . . . . . . . 00

7F . . . . . . . . . 78

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External Data MemoryExternal Data MemoryExternal Data Memory

• 64k byte address space

• Indirectly addressable via R0 and R1 in 256byte segments

• Entire space is indirectly addressable viathe Data Pointer

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External Bus ExpansionExternal Bus ExpansionExternal Bus Expansion80C51

PORT 2

PORT 0

ALE

P3.7

P3.6

PSEN

A15 - A8 High byte of address

AD7 - AD0 Data and low byte address

ALE Address latch enable

RD Read strobe

WR Write strobe

PSEN Program store enable

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External Program MemoryExternal Program MemoryExternal Program Memory

80C51

Port 2

ALE

Port 0

PSEN

AddressLatch

EPROM

AddressInputs

DataOutputs

OE

A15 - A8

A7 - A0

D7 - D0

AD7 - AD0

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External Data MemoryExternal Data MemoryExternal Data Memory• 64K byte address space

• Indirectly addressable via R0 and R1 in 256 byte segments

• Entire space in indirectly addressable via the data pointer DPTR

80C51

Port 2

ALE

Port 0

WRRD

RAM(S)or I/O

CE

Data

AddressInputs

R/WOE

AddressLatch

Decode

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80C51 Timing80C51 Timing80C51 TimingState 1 State 2 State 3 State 4 State 5 State 6 State 1 State 2

XTAL2

ALE

_____PSEN

P0

P2

Datasampled

PCL out PCL out

Datasampled

PCL out

Datasampled

PCH out PCH out

P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

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ResetResetReset• RST pin is Schmitt trigger input

• External reset is synchronousto the internal clock

• RST pin must be high for atleast two machine cycles whilethe oscillator is running

• Internal RAM not affected byreset, but indeterminate onpower up

• Port pins in random state untiloscillator starts and algorithmwrite 1's to them

80C51

RST

+5V

8.2K

10uF

80C51

RST

+5V

2.2uF

Typical circuits:

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Special Function Register SpaceSpecial Function Register SpaceSpecial Function Register Space

• 128 byte address space, directly addressableas 80 to FF hex

• 16 bytes are bit addressable

• Contains:– Special purpose CPU registers– I /O control registers– I /O ports

• Allows for expansion of I/O or derivatives

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Special Function RegistersSpecial Function RegistersSpecial Function Registers

CPU Registers– ACC Accumulator– B B register– PSW Program Status

Word– SP Stack Pointer– DPTR Data Pointer

(DPH, DPL)

Interrupt Control– IE Interrupt Enable– IP Interrupt Priority

I/O Ports– P0 Port 0– P1 Port 1– P2 Port 2– P3 Port 3

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Special Function Registers (Cont'd)Special Function RegistersSpecial Function Registers (Cont'd)(Cont'd)

Timers:

– TMOD Timer mode

– TCON Timer control

– TH0 Timer 0 high byte

– TL0 Timer 0 low byte

– TH1 Timer 1 high byte

– TL1 Timer 1 low byte

Serial I/O:– SCON Serial port control

– SBUF Serial data registers

Other:– PCON Power control, etc.

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Special Function Register MapSpecial Function Register MapSpecial Function Register MapF8

F0 B

E8

E0 ACC

D8

D0 PSW

C8

C0

B8 IP

B0 P3

A8 IE

A0 P2

98 SCON SBUF

90 P1

88 TCON TMOD TL0 TL1 TH0 TH1

80 P0 SP DPH DPL PCON

Bit Addressable

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PSW: Program Status WordPSW: Program Status WordPSW: Program Status Word

RS1 RSO Register Bank Address

0 0 0 00H - 07H

0 0 1 08H - 0FH

1 0 2 10H - 17H

1 1 3 18H - 1FH

CY AC F0 RS1 RS0 OV --- PCarry Flag

Auxiliary Carry Flag

Flag 0 (available for user)

Register Select 1

Register Select 0

Arithmetic Overflow

Flag

Accumulator Parity

Flag

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I/O PortsI/O PortsI/O Ports

• Four 8-bit I/O ports

• Most have alternate functions

• Quasi-bidirectional:– Soft pull-up when port latch contains a 1– Strong pull-up for 2 OSC cycles during 0 to 1

transitions

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CMOS Port ConfigurationCMOS Port ConfigurationCMOS Port Configuration

PortPin

Q

FromPort

Latch

2 OSC.Periods

P1 P2 P3

VCC

VCC

VCC

N

InputData

Read Port Pin

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Port 0Port 0Port 0

• As an I/O port:– No strong pull-up, outputs act as open drain

• As a multiplexed data bus:– Tri-state bus with strong pull-ups– 8-bit instruction bus, strobed by PSEN– Low byte of address bus, strobed by ALE– 8-bit data bus, strobed by WR and RD

• 3.2 mA outputs (about 8 LSTTL loads)

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Port 1Port 1Port 1

As an I/O port:

• Standard quasi-bidirectional

• Alternate functions only on some derivatives


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Port 2Port 2Port 2

As an I/O port:


• Alternate functions:

– High byte of address bus for external

– Program and data memory accesses


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Port 3Port 3Port 3

As an I/O port:


• Alternate functions:– Serial I/O TXD, RXD– Timer clocks T0, T1– Interrupts INT0, INT1– Data memory RD, WR


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Counter/TimersCounter/TimersCounter/Timers• Two 16-bit Counter/Timers

– Up counters can interrupt on overflow

• Counts:– CPU cycles (crystal / 12)– External input (max. half CPU rate)

• Four Operation Modes– Mode 0 8048 timer– Mode 1 16-bit counter / timer– Mode 2 8-bit C /T with auto-reload– Mode 3 Two 8-bit counter/timers

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Timer Mode 0Timer Mode 0Timer Mode 0

OSC 12

T1 Pin

Gate

INT1 Pin

TR1

Control

C/T = 0

C/T =1

TL1 (5 Bits)

TH1 (8 Bits) TF1 Interrupt

Operation– Times by counting CPU cycles– Counts external events on T0 or T1– Fmax is 500kHz (CPU @ 12MHz)– Gate inputs on / INT0 or /INT1

Emulates 8048 Counter/Timer– 8-bit up-counter (TH0, TH1)– 5-bit prescaler (TLO & TL1 )

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Timer Mode 1Timer Mode 1Timer Mode 116-bit up-counterOperation

– Times by counting CPU cycles– Counts external events on T0 or T1– Fmax is 500kHz (CPU @ 12MHz)– Gate inputs on / INT0 or /INT1

INT1 Pin

Interrupt

OSC 12

T1 Pin

Gate

TR1

Control

C/T = 0

C/T =1TL1

(8 Bits)TH1

(8 Bits) TF1

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Timer Mode 2Timer Mode 2Timer Mode 2

OSC 12

T1 Pin

Gate

INT0 Pin

TR1

Control

C/T = 0

C/T =1TL1

(8 Bits)

TH1 (8 Bits)

TF1 Interrupt

8-bit Auto-Reload– Uses counter TL0 or TL1– Reload value remains in TH0 or TH1– Provides a periodic flag or interrupt

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Timer Mode 3TimerTimer ModeMode 33

• Timer 0 Split into 2 8-bit C/Ts– TL0 becomes an 8-bit mode 0 type– TH0 counts CPU cycles while using

• TR1 (Timer 1's Run Bit) as enable• TF1 (Timer 1's overflow) as a flag• Timer 1's interrupt

• Timer 1– May be used for baud rate generation– Gate (INT1) & external input (T1) operate– Interrupt & flag sold to Timer 0

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Timer Mode 3 (Cont'd)Timer Mode 3 Timer Mode 3 (Cont'd)(Cont'd)

OSC 12

Gate

INTO Pin

TR0

To pin Control

C/T = 0

C/T =1TL1

(8 Bits) TF0 Interrupt

1/12 fOSC

1/12 fOSC

Control

TH0 (8 Bits) TF1 Interrupt1/12 fOSC

TR1

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TMOD: Counter Timer Mode RegisterTMOD: Counter Timer Mode RegisterTMOD: Counter Timer Mode Register

GATE Permits INTx pin to enable/disable counterC/T Set for counter operation, reset for timer operationM1, M0

00 Emulate 8048 counter/timer01 16-bit counter/timer10 8-bit auto-reload mode11 Timer 0 = two 8-bit timers

Timer 1 = stopped

TIMER 1 TIMER 0

GATE C/T M1 M0 GATE C/T M1 M0

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TCON : Counter/Timer Control RegisterTCON : Counter/Timer Control RegisterTCON : Counter/Timer Control Register

TF1, TF0 Overflow flags for Timer 1 and Timer 0

TR1, TR0 Run control bits for Timer 1 and Timer 0Set to run, reset to hold

IE1, IE0 Edge flag for external interrupts 1 and 0 *Set by interrupt edge, cleared when interruptprocessed

IT1, IT0 Type bit for external interrupts *Set for falling edge interrupts, reset for 0 levelinterrupts

* Not related to counter/timer operation

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

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80C51 Serial Interface80C51 Serial Interface80C51 Serial Interface• Full duplex UART• Four modes of operation:

– Synchronous serial I/O expansion– Asynchronous serial I/O with variable baud rate– Nine bit mode with variable baud rate– Nine bit mode with fixed baud rate

• 10 or 11 bit frames• Interrupt driven or polled operation

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Serial Interface RegistersSerial Interface RegistersSerial Interface Registers

SCON Serial port control register

SBUF Read received dataWrite data to be transmitted

PCON SMOD bit

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SCON : Serial Control RegisterSCON : Serial Control RegisterSCON : Serial Control Register

SM0, SM1 - Serial Mode00 = Mode 0 - Shift register I/O

expansion01 = Mode 1 - 8-bit UART with

variable baud rate10 = Mode 2 - 9-bit UART with

fixed baud rate11 = Mode 3 - 9-bit UART with

variable baud rate

SMO SM1 SM2 REN TB8 RB8 TI RI

SM2Mode 0 - Not usedMode 1 - 1 = Ignore bytes

with no stop bitMode 2, 3 - 0 = Set receive

interrupt (RI) onall bytes

- 1 = Set RI on byteswhere bit 9 = 1

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Serial Control Register (Cont’d)Serial Control Register Serial Control Register (Cont’d)(Cont’d)

SMO SM1 SM2 REN TB8 RB8 TI RI

REN - Enables receiver

TB8 - Ninth bit transmitted (in modes 2 and 3)

RB8 - Ninth bit received:Mode 0 Not usedMode 1 Stop bitMode 2, 3 Ninth data bit

TI - Transmit interrupt flag

RI - Receive interrupt flag

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80C51 UART Baud Rate Generation 80C51 UART Baud Rate Generation 80C51 UART Baud Rate Generation

Mode 2

Synchronous

Asynchronous

Mode Formula With 12 MHz XTAL

0

1.3

2

Baud Rate =

Baud Rate =

Baud Rate =

Oscillator Clock Rate 12

Oscillator Clock Rate(12) (2) (16) (256-TH1)

Oscillator Clock Rate (2) (2) (16)

1 MB

31250 (256-TH1)

B

187.5 KB

OSC 12TMOD Bit 6

Timer 1Modes 1, 3

2

2

16

Bit 87H.7

Mode Bitsof SCON

Clock forSerial I/O Mode 0

T1

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Interrupt SystemInterrupt SystemInterrupt System• 5 Interrupt Sources:

– Serial Port– Timer 0– Timer 1– External Interrupt 0– External Interrupt 1

• Each interrupt type has a separate vector address• Each interrupt type can be programmed to one of

two priority levels (allows nesting)• External interrupts can be programmed for edge or

level sensitivity

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IE - Interrupt Enable RegisterIE - Interrupt Enable RegisterIE - Interrupt Enable Register

EA Global interrupt enableES Serial interfaceET1 Timer 1EX1 External interrupt 1ET0 Timer 0EX0 External interrupt 0 0 = Disabled, 1 = Enabled

EA ----- ----- ES ET1 EX1 ET0 EX0

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Interrupt Vector AddressesInterrupt Vector AddressesInterrupt Vector Addresses

Source Address

IE0 03H

TF0 0BH

IE1 13H

TF1 1BH

RI&TI 23H

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IP - Interrupt Priority RegisterIP - Interrupt Priority RegisterIP - Interrupt Priority Register

PS Serial interfacePT1 Timer 1PX1 External interrupt 1PT0 Timer 0PX0 External interrupt 0

0=Low priority 1=High priority

----- ----- ----- PS PT1 PX1 PT0 PX0

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PCON: Power Control RegisterPCON: Power Control RegisterPCON: Power Control Register

• IDLE Mode Operation– Setting IDL gates clocks off, leaves oscillator running– All register and RAM contents are saved– All interrupt sources remain active– Exit with any enabled interrupt or Reset

• Power-Down Operation– Setting the PD bit stops the oscillator– RAM contents are saved– Vcc can be reduced to 2V– Exit via Reset

• GF0, GF1 - General purpose software flags; not on the 8051• SMOD - Serial interface control; doubles baud rate in modes 1-3

SMOD ––– ––– ––– GF1 GF0 PD IDL

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Part 2

80C51 Instruction Set

Part 2

80C51 Instruction Set

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Instruction Set: ArithmeticInstruction Set: ArithmeticInstruction Set: ArithmeticMnemonic Operands Bytes/Cycles

ADD A, Rn 1/1

ADDC A, direct 2/1

SUBB A, @Ri 1/1

A, #data 2/1

INC A 1/1

DEC Rn 1/1

direct 2/1

@Ri 1/1

INC DPTR 1/2

MUL AB 1/4

DIV AB 1/4

DA A 1/1

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Instruction Set: LogicInstruction Set: LogicInstruction Set: LogicMnemonic Operands Bytes/Cycles

ANL A, Rn 1/1

ORL A, direct 2/1

XRL A, @Ri 1/1

A, #data 2/1

direct, A 2/1

direct, #data 3/2

C, bit 2/2

C, /bit 2/2

CLR A 1/1

CPL C 1/1

bit 2/1

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Instruction Set: LogicInstruction Set: LogicInstruction Set: Logic

Mnemonic Operands Bytes/Cycles

RL A 1/1RLC A 1/1RR A 1/1RRC A 1/1SWAP A 1/1SETB C 1/1

bit 2/1

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Instruction Set: Data TransferInstruction Set: Data TransferInstruction Set: Data Transfer

Operands Bytes/Cycles

A, Rn 1/1

A, direct 2/1

A, @Ri 1/1

A, #data 2/1

Rn, A 1/1

Rn, direct 2/2

Rn, #data 2/1

direct, A 2/1

direct, Rn 2/2

Operands Bytes/Cycles

direct, direct 3/2

direct, @Ri 2/2

direct, #data 3/2

@Ri, A 1/1

@Ri, direct 2/2

@Ri, #data 2/1

DPTR, #data 16 3/2

C, bit 2/1

bit, C 2/2

Mnemonic: MOV

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Instruction Set: Data Transfer (Cont'd)Instruction Set: Data Transfer Instruction Set: Data Transfer (Cont'd)(Cont'd)


MOVC A, @A+DPTR 1/2

A, @A+PC 1/2

MOVX A, @Ri 1/2

A, @DPTR 1/2

@Ri, A 1/2

@DPTR, A 1/2

PUSH direct 2/2

POP direct 2/2

XCH A,Rn 1/1

A, direct 2/1

A, @Ri 1/1

XCHD A, @Ri 1/1

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Instruction Set: BranchingInstruction Set: BranchingInstruction Set: Branching


ACALL addr11 2/2

LCALL addr16 3/2

RET 1/2

RETI 1/2

AJMP addr11 2/2

LJMP addr16 3/2

SJMP rel 2/2

JMP @A+DPTR 1/2

JZ rel 2/2

JNZ rel 2/2

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Instruction Set: Branching (Cont'd)Instruction Set: Branching Instruction Set: Branching (Cont'd)(Cont'd)


CJNE A, direct, rel 3/2

A, #data, rel 3/2

Rn, #data, rel 3/2

@Ri, #data, rel 3/2

DJNZ Rn, rel 2/2

direct, rel 3/2

NOP 1/1

JC rel 2/2

JNC rel 2/2

JB bit, rel 3/2

JNB bit, rel 3/2

JBC bit, rel 3/2

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SummarySummarySummary• 8 Bit data path and ALU

• Easy interfacing

• 16 thru 40 MHzversions

• Full instruction setincluding multiply,divide, bit set, reset,and test

• Variety of addressingmodes

• 4K X 8 ROM - Programmemory

• 128 x 8 RAM - Datamemory

• Special FunctionRegisters

• Serial I/O port• 32 I/O lines• Two 16-bit

counter/timers

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