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Graphene-based transistors for digital and analog applications:
a simulation study
Roberto Grassi
Advanced Research Center on Electronic Systems (ARCES) University of Bologna
Outline
● Introduction to graphene and graphene nanoribbons
● Simulations studies of:
– Graphene Nanoribbons FETs
– Graphene FETs
– Graphene Base Transistors
3
CMOS scaling
● … approaching its limits due to a number of issues, e.g. short channel effects (SCEs)
● MOSFET scaling in digital electronics:
– ↑ complexity
– ↑ performance
– ↓ cost per transistor
↓ performance, ↑ power consumption
Source: Intel
4
Beyond CMOS
New device structures New channel materials
Fin FET (Tri-Gate)
Nanowire FET
Carbon nanotube
Graphene
MoS2
5
Graphene
● Monolayer of carbon atoms in a honeycomb lattice: first 2D crystal
● Isolated in 2004 by Manchester group (Nobel prize in Physics 2010)
unit cell
6
Graphene preparation
● Scotch-tape method
Source: Youtube
● Wafer scale production by CVD on metals
single-layer
Nature Nanotech. 5, 574 (2010)
7
Graphene properties
● Interesting properties for nanoelectronics:
● atomic thickness → ideal electrostatic control
● high mobility at room temperature (> 10,000 cm2/Vs)
→ ballistic transport
● large current density → interconnects
8
Unusual electronic propertiesDirac point = intrinsic level
E (k)=±ℏ vF∣k∣
● Zero bandgap
● p or n conductor depending on EF
● Electrons behave as “Dirac fermions”: linear E(k) + pseudo-spin
Band structure determines electron available states and velocity
9
Band-gap problem
Conventional semiconductor
ON state (high VG)
10
Band-gap problem
Conventional semiconductor
OFF state (low VG)
11
Band-gap problem
Graphene
● “Klein” tunneling → current ON/OFF ratio ≈ 10
EG = 0
OFF state (low VG)
12
Graphene Nanoribbons (GNRs)Physica E 40, 228 (2007)
Band-gap engineering by
transverse quantum confinement
PRL 98, 206805 (2007)
PRL 100, 206803 (2008)
13
Graphene Nanoribbons (GNRs)
Possibility of fully graphene-based electronics (both active components and interconnects)
High sensitivity to GNR orientation and width
Experimental GNRs: irregular edges and orientation
All metallicSemiconducting or metallic
ACS Nano 7, 198 (2013)
UCSB Nanoelectronics Research Lab
14
Why device modeling and simulation?
● They allow to:
– predict the device behavior
– understand the physical mechanisms underlying the device operation
– test the impact of device design parameters on the device performance (device optimization)
Results serve to guide and speed-up device fabrication
15
Transport models
Klimeck, ECE606 lectures (2012); available at nanohub.org
16
Device simulation
Error check
Electrostatics (Poisson eq.)
φ
φ
Transport (e.g. NEGF)
n, p
φ0
Current calculation
VGS, VDS
Device simulator
IDS
(+ other quantities)
VGS
IDS
Simulation flowchart:
Biasing scheme:
VDS
17
GNR FET
● Double gate structure for enhanced electrostatic control
● Uniform doping of S/D regions (and intrinsic channel)
W
18
I-V characteristicsTransfer char. Output char.
Good current saturation and high ION (= 8mA/μm) but contact resistance is neglected
W = 1.5 nm
19
I-V characteristicsTransfer char. Current spectrum & band profile
Problem of DIBL in the subthreshold region at VDS ≈ EG/q
(= 0.8 V) due to BTBT
20
Effect of larger widthTransfer char.
W < 3.5 nm to achieve ION/IOFF > 104
reduced ION/IOFF ratio
Smaller EG
VDD must be scaled to avoid BTBT
W = 4.8 nm
21
Tunneling GNR FET● Growing interest in tunneling FETs as low power devices
● ON-current due to BTBT at the source-channel junction: SS < 60 mV/dec
● TFETs realized with opposite doping of S/D regions
Ambipolar branch
p doping n doping
Possibility of operation at reduced VDD
22
Optimized devices
p doping
● Large ION/IOFF even with low VDD
● Lower ION compared to n-i-n devices
W = 4.8 nmW = 1.5 nm
23
Effect of scattering: edge roughness
p doping
Detrimental effect of ER on IOFF due to localized states inside the gap
Transfer char. Local density of states
24
Effect of scattering: acoustic phonons
VDS = 0.1 V
VG = 0.6 V
● Scattering with phonons is not negligible even for short GNR-FETs
● Ballisticity ratio about 0.6 at VG = 0.8 V, VDS = 0.1 V
W = 1.5 nm, LG = 10 nm
25
Low field mobility
● Calculated as:
Ballistic regime: IDS = const
Diffusive regime: IDS ∝ 1/LG
26
Low field mobility
● Mobility reduction with VG and increase with NA (width)
Vs/cm384 2≈extractedERµ
Vs/cm2300 2≈extractedAPµ
Vs/cm174 2exp ≈ERµ
W = 2.5 nm
● However, ER is more detrimental than AP:
Experiments
27
Wide GNR FETs for analog applications
W = 10 nm● Problem for analog
applications: no current saturation, hence low voltage gain Av = gm / gd
● Reason: small band-gap (EG = 140 meV) and BTBT at the drain end of the channel
28
Optimized devices
W = 10 nm
W = 15 nm
fT performance largely exceeding the THz barrier
No possibility of trading-off Av and fT as in standard MOSFETs
fT = gm / (2πCgs)
29
Graphene FET (GFET)
ACS Nano 6, 2610 (2012)
● Experimental observation of negative output differential resistance (gd < 0)
● NDR could be exploited to achieve high intrinsic voltage gain gm/gd
(WGNR →∞)
30
Simulation of NDR
● NDR is enhanced by larger ΔEcon (degeneracy of source/drain)
● Our simulations confirm NDR
● Related to peculiar DOS of graphene and the presence of an n-p-n double junction
31
Electrostatic doping
● Quasi-saturation or NDR regime depending on polarities of VGS and VDS
● Back gate allows easy control of ΔEcon
smaller gm
32
Small-signal analysis
● Circuit stability can be achieved by calibration of GL and RA
Circuit model including parasitic inductances LL, LA
33
Analog & RF metrics
Saturation
Voltage gain larger than 10 if GL matches -gout
Reduced gain-bandwidth product and fmax
In NDR regime:
NDR
34
Voltage transfer characteristics
Saturation
Narrower input voltage range → limitation to small-swing signals
In NDR regime:
NDR
35
Graphene Base Transistor (GBT)
● Hot Electron Transistor (HET) with graphene base
● Attractive features:
– Low off currents– Drain current
saturation– Low base transit time– Power amplification
Emitter Base Collector
VCE
VBE
EBL
BCL
Graphene
x
yz
transport direction
Emitter Base Collector
ΦEBL
ΦBCL
FN current
EBL BCL
tEBL
tBCL
36
Experimental works DC functionality Very low currents (< 1 μA/cm2) Poor common-base gain α (< 0.1)
C. Zeng et al., Nano Letters, vol. 13 no. 6, pp. 2370-2375, 2013.
S. Vaziri et al., Nano Letters, vol. 13 no. 4, pp. 1435-1439, 2013.
Due to the use of oxides as EBL and BCL
37
Simulation: DC operation
● ФEBL = ФBCL = 0.2 eV
● tEBL/BCL = 3/20 nm● Graphene treated as
transparent layer
Turn-on characteristics
38
Simulation: DC operationTurn-on characteristics
Band diagram (EC)
● ФEBL = ФBCL = 0.2 eV
● tEBL/BCL = 3/20 nm● Graphene treated as
transparent layer
39
Simulation: DC operation
VBE = 1.2 V
A B
Low VCE: unsaturated
High VCE: saturated
Output characteristics
Local density of states
40
Simulation: DC operationOutput characteristics
Red: tBCL = 10 nm
Blue: tBCL = 20 nm
Shorter BCL:Wider saturation region / Worse output conductance
41
Simulation: RF perfomance
Red: tBCL = 10 nm
Black: tBCL = 20 nm
Trade-off between fT and Av0
fT = gm / (2π dQgr/dVBE)
42
Opportunities for theses
● Graphene research activity currently carried out by:
– Prof. Antonio Gnudi
– Ph.D. Valerio Di Lecce
– myself
● … within the EU project GRADE (Graphene-based Devices and Circuits for RF Applications):
– GBT: modeling, choice of materials and dimensions, performance analysis,...
– GFET: optimization of the current saturation,...
http://www.grade-project.eu/