Greetings from IEEE EMC Society & Georgia Techewh.ieee.org/r1/njcoast/slides/swaminathan_dl_emc_nj.pdf · IEEE EMC Society & Georgia Tech ... Thermal Management Joule Heating Thermal

Greetings from

Multi-scale and Multi-physics Modeling

Their Role in 3D Integration

Multi-scale and Multi-physics Modeling

Their Role in 3D Integration

IEEE EMC Society & Georgia TechIEEE EMC Society & Georgia Tech

Madhavan Swaminathan

Distinguished Lecturer, IEEE EMC Society

Joseph M. Pettit Professor in Electronics

School of Electrical and Computer Engg.

Director, Interconnect and Packaging Center

Georgia Institute of Technology Feb 2012

� 3D Integration – What, Why and When ?

� Case for Multi-scale and Multi-physics Modeling

� Through Silicon Via Basics

� Electromagnetic Modeling (Multi-scale)� EFIE – Managing Spatial Resolution for Cylindrical Structures

� FDTD – Managing time resolution

� Electrical - Thermal Modeling (Multi-physics)� Joule Heating & IR Drop� Temperature Dependent High Frequency Effects

� Some thoughts on Electrical - Mechanical Modeling (Multi-physics)

� Concluding thoughts …..

OutlineOutline


Moore’s LawMoore’s Law

1965

Components/IC will double every year

1975

Components/IC will

double every two years

When asked, “What would you like your legacy to the world to be ?”Dr. Moore replied: “Anything” but Moore’s Law”

� Has been the

driver for the

semiconductor

industry for more than

4 decades

� More well known

than Murphy’s lawSource: Spectrum and Anderson

School UCLA


System Convergence and Miniaturization TrendSystem Convergence and Miniaturization Trend

1970 1980 1990 2000

100

1000

10000

100000

Vo

lum

e(cm

3)

W/S

SMART

“Watch” &

Bio-sensor

SINGLE FUNCTION

MULTIFUNCTION

MEGAFUNCTION

Notebook

PC

Laptop

Cellular

Fu

nct

ion

al

Den

sity

or

Co

mp

on

ent

Den

sity

/ c

m3)

Courtesy: Packaging Research Center, Georgia Tech


70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00 02 04 06 08 10 12 14 16 18 20 22 24 1

101

102

103

104

105

106

109

108

107

106

105

104

103

102

Mor

e th

an M

oore

SIP

/SO

PO

rgan

ic

Even M

o(o)re

Eve

n M

o(o)

re

Silic

on

World’s smallest

Organic RF Module

PRC/JMD

Moore’

s Law

Computing

Con

sum

er

Com

putin

g

, Con

sum

er,

Bio

, Ene

rgy

Performance

Degrades

With scaling

Quad

core

Dual

Core

3D

INTEGRATION

Ceramic/PWBVol=XYZ

Vol=10-3XYZ

Vol=10-6XYZ

Tra

nsis

tor

Density/c

m2

Syste

m C

om

p. D

ensity/c

m2

107

Source: IPC, PRC and Spectrum

Year

Is Moore’s Law Sufficient for System Miniaturization ?

Is Moore’s Law Sufficient for System Miniaturization ?


Stacking using Wirebond (past)

Stacking using TSV (future)

POP Stacking (present)

Ref: R. Tummala and M. Swaminathan, “Introduction to System on Package”, McGraw Hill, 2008

3D Z-directioninterconnections

3D Integration Technologies3D Integration Technologies


CPU and Memory Integration TrendCPU and Memory Integration Trend

Inte

gra

tion

Den

sity

Time

Multichip Package

DDR3

Stacked POPLPDDR

Stacked PIPLPDDR+Analog

Stacked TSV

Wide I/O

4.8nJ/word

512pJ/word

512pJ/word

2-7pJ/word

� Power Budgeting 10X increase in 10 Years� 30-50% increase in I/O Power (Mobile)� 3D w/ TSV reduces power by 4-10X� Interconnect/Packaging Based Solution

Courtesy: Part Greg Taylor, Intel and Paul Franzon, NC State


� First Killer Product in 2013

� Wide I/O Memory� Mobile product application

� 512 I/Os transmitting at 12.8Gbps (3.2Gbps

in LPDDR2 memory)

� 8X improvement in Bandwidth� 35% decrease in package size

� 50% decrease in power consumption

Courtesy: Samsung [1]

[1] Dr. Oh Hyun Kwon [ISSCC, 2010] – Samsung Electronics Courtesy: Xilinx

3D w/ Chip Stacking

2.5D

3D enabled w/ Interposer

Integration ApproachesIntegration Approaches


Empire State Building Micro-system

Going VerticalGoing Vertical

www.ipc.gatech.edu

Strong Foundationto protect against earthquake & entry/exitto outside world

MechanicalIntegrity toProtect againstHurricane

CommunicationBetween FloorsWith minimum interference

Good cooling System to remove heat


Power Delivery/DC/ACEMI

Signal Integrity

Place & Route

Electrical (EMC)

Joule HeatingThermal ManagementT

he

rma

l

Mechanical Stresses

Me

ch

an

ical

Tier 1Thickness ~ 50 µmAc tive Face Down

Tier 1Thickness ~ 5 0 µm

Active Face D own

BackSide MetalPitc h ~ 5-25 µm

BackSide MetalPitch ~ 5-2 5 µ m

Package SubstrateThickness ~ 180 µm

Package SubstrateThickness ~ 1 80 µ m

UnderfillG ap ~ 80 µ m

UnderfillGap ~ 80 µm

Flip Chip BumpSize ~ <100 umPitch ~ 100-200 um


TSVSize ~ 5-10 µmPitc h ~ 10-50 µm

TSVSize ~ 5-10 µm

Pitch ~ 10-50 µm

BGA BumpPitch ~ 0.65 mm

H eight ~ 300 um

BGA BumpPitch ~ 0.6 5 mmHeight ~ 300 um

µ-BumpPitc h ~ 25-50 µm

µ-BumpPitch ~ 25-50 µm

UnderfillGap ~ 20 µ m


Tier 2Thickness ~ 260 µm

Ac tive F ace D own

Tier 2Thickness ~ 2 60 µ mActive Face Down

Mu

lti-

sca

le G

eom

etr

y

Multi-physicsenvironment

Modeling for 3D IntegrationModeling for 3D Integration

Multi-scale

&


Cu Oxide

Si

D=100µm, R=15µm, L=100µm, dox=0.1µm, εSiO2=3.9 and εSi = 11.9

Sharp increase in IL

Gradual increase in IL

Structure and Electrical Response of Through Silicon Via Pair

Structure and Electrical Response of Through Silicon Via Pair


Signal ViaPort 1

Signal ViaPort 2

Ground Via

Ground Via

R1

C1

R2

C2

R1

C1

R

L/2

R

L/2

Conductance

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11

Frequency (Hz)

Conducta

nce (m

S)

Conductance

Capacitance

1.E-02

1.E-01

1.E+00

1.E+01

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11

Frequency (Hz)C

apacitance (pF)

Capacitance

Loss Tangent

0.E+00

5.E+00

1.E+01

2.E+01

2.E+01

3.E+01

3.E+01

4.E+01

1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11

Frequency (Hz)

tan

d

Loss Tangent

Slow Wave Quasi-TEMTransition

� Strong interfacial polarization and dielectric

relaxation exists that provide unique characteristics

to TSVs through the Maxwell-Wagner Effect (Defines Slow Wave and Quasi-TEM mode)

Maxwell-Wagner EffectMaxwell-Wagner Effect


Conductor (10um dia) Thin oxide layer (<1um)

Lossy silicon substrate

100um

10-30um

Due to the length scale (1:1000), it is difficult to apply EM Modeling directly to

TSV Arrays

Electromagnetic Modeling of TSVsThe Multi-scale Problem

Electromagnetic Modeling of TSVsThe Multi-scale Problem


� Uses Cylindrical

Basis Functions – CMBF, AMBF,PMBF

� Solves Electric Field Integral Equation

� Uses Acceleration Methods

� Computes frequency dependent RLGC parameters

� Computes accurate coupling and loss occurring due toproximity effect

� TSV position can be arbitrary (Eliminates Meshing)

Mutual Inductance

Integral Equation Based Solver using Specialized Basis FunctionsIntegral Equation Based Solver using Specialized Basis Functions


×1

×5.0

×5.0

SE mode

PE-d mode

PE-q mode

Resultant current

density distribution

×1

×5.0

×5.0

SE mode

PE-d mode

PE-q mode

Resultant current

density distribution

-1.5 -1 -0.5 0 0.5 1 1.5

-1.5

-1

-0.5

0

0.5

1

1.5

-1.5 -1 -0.5 0 0.5 1 1.5

-1.5

-1

-0.5

0

0.5

1

1.5

-1.5 -1 -0.5 0 0.5 1 1.5

-1.5

-1

-0.5

0

0.5

1

1.5

-1.5 -1 -0.5 0 0.5 1 1.5

-1.5

-1

-0.5

0

0.5

1

1.5

-1.5 -1 -0.5 0 0.5 1 1.5

-1.5

-1

-0.5

0

0.5

1

1.5

Skin and Proximity Effect Modes

Polarization Effect Modes

Fundamental

1st Mode 2nd Mode

Ref: K. J. Han and M. Swaminathan, “Inductance and Resistance

Calculations in Three-Dimensional Packaging using

Cylindrical Conduction Mode Basis Functions”, IEEE Trans. on

Computer Aided Design of Integrated Circuits & Systems, ‘09

Modal Basis FunctionsModal Basis Functions


-6 -4 -2 0 2 4 6-6

-4

-2

0

2

4

6x 10

-5

�378 basis functions (Fast Henry)

�3 – 5 Specialized Basis Functions (This Method)

Modeling of Current in ConductorModeling of Current in Conductor

Fast Henry


conductor series

resistance Conductor self

and mutual

inductances

Problem due to

increased conductance

(leakage)

Conductance

CapacitanceTSV StructureL=100umD=30umP=60umGrounded Substrate

K. J. Han, M. Swaminathan and T. Bandhyopadyay, “Electromagnetic Modeling of Through-Silicon Via (TSV) Interconnections using Cylindrical Modal Basis Functions”, IEEE Trans. on Advanced Packaging, 2010

RLGC Parameter ExtractionRLGC Parameter Extraction


Frequency 1GHz

-70

-60

-50

-40

-30

-20

-10

0

0 50 100 150 200 250

Pitch (um)

Co

up

lin

g (

dB

)

TSV

TOV

Frequency 10GHz

-70

-60

-50

-40

-30

-20

-10

0

0 50 100 150 200 250

Pitch (um)

Co

up

lin

g (

dB

)

TSV

TOV

R=10µm, L=100µm and dox=100nm

er(SiO2)=3.9, er(Si)=11.9

R=10µm and L=100µmEr = 3.9

D: Pitch

D: Pitch

25dB

7dB

Crosstalk – A Major Concern for Silicon InterposerCrosstalk – A Major Concern for Silicon Interposer


Q

G G G

G

G G

S

G

G

S S S S

S S S S S

S

S

S

S

S

S

D=100µm, R=10µm, L=200µm, dox=0.1µm, εSiO2=3.9 and εSi = 11.9

50 Ohm2V

50 Ohm

0 0.2 0.4 0.6 0.8 1

x 10-8

-0.02

0

0.02

0.04

0.06

0.08

0.1

0.12

TS

V-1

3 (

V)

TIME

Coupled Noise into Q TSV

All Signals Excited

Noise Measured on TSV Q Near End

Shielding

doesn’t work

well

Importance of ShieldingImportance of Shielding


Top viewCross-sectional view

SiO2

Si300 um

10 um

1000 um

1000 um

500 um500 um

20 um 150 um

100 um

1 mm 20 mm 1 mm

1 um

PEC boundary

20 mm

45 um

500 um

500 um100 mm

PEC boundary40 mm

• TSV oxide thickness: 1um

• TSV copper diameter: 100um

• Silicon conductivity: 10 S/m

• Scale difference=1um(oxide thickness):20mm(length of TL)=1:20000

• Discretized into 94 × 263 × 31 = 766,382 (Laguerre-FDTD Method)

� 4.6M unknowns

V. Sridharan, M. Swaminathan, and T. Bandyopadhyay, “Enhancing Signal and Power Integrity Using Double Sided Silicon Interposer,” IEEE

Microwave and Wireless Components Letters, To be Published in Dec. 2011

Microstrip Transition with Power and Ground Planes

Microstrip Transition with Power and Ground Planes


Start with FDTD

222

111

1

zyxc

t

∆+

∆+

∆

<∆

� Yee Grid Limited by the CFL stability condition Can lead to long simulation time for multi-scale dimensions� However, FDTD is memory efficient

Expand the fields

Ez Hy

Marching on Time

� Unconditional Stability

� Reduces simulation time for multi-scale dimensions – time step not limited by CFL condition� Domain decomposition techniques can be applied to reduce memory and increase capacity

Marching on Degree

qEEE ,....,, 10

0 5 10 15 20 25 30-0.5

0

0.5

1

p=0

p=1

p=2

p=3

p=4

Laguerre basis functions

Laguerre Finite Difference Time Domain (FDTD) MethodLaguerre Finite Difference Time Domain (FDTD) Method


22

Laguerre-FDTD

SLeEC

Improvement

Laguerre-domainTime-domain

Maxwell’s equations

in time-domain

Maxwell’s equations

in Laguerre-domain

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Time (ns)

J (A

/m2)

0 20 40 60 80 100 120 140 160 180 200-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

Coefficient #

Am

plit

ude

0 20 40 60 80 100 120 140 160 180 200-3000

-2000

-1000

0

1000

2000

3000

4000

Coefficient #

Am

plit

ude

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-800

-600

-400

-200

0

200

400

600

800

1000

1200

Time (ns)

J (A

/m2)

SourceSource

Solution

[5] Y.-S. Chung, T. K. Sarkar, B. H. Jung and M. Salazar-Palma, "An unconditionally stable scheme for the finite-difference time-domain method," IEEE Trans. Microw. Theory Tech., vol. 51, no. 3, pp. 697-704, Mar 2003. [6] K. Srinivasan, Multiscale EM and Circuit Simulation Using the Laguerre-FDTD Scheme for Package-Aware Integrated-Circuit Design. PhD Thesis, Georgia Institute of Technology, 2008

[1] K. S. Yee, "Numerical solution of initial boundary value problems involving Maxwell’s equations in isotropic media," IEEE Trans. Antennas Propag., vol. 14, no. 3, pp. 302-307, Mar 1966. [2] Shumin Wang, “Numerical Examinations of the Stability of FDTD Subgridding Schemes,” ACES Journal, Vol. 22, No. 2, July 2007[3] T. Namiki and K. Ito, "A new FDTD algorithm free from the CFL condition restraint for a 2D-TE wave," in IEEE AP-S Symp. Dig., Orlando, FL, 1999. [4] F. Zheng and Z. Chen, "Numerical Dispersion Analysis of the Unconditionally Stable 3-D ADI–FDTD Method," IEEE Trans. Microwave Theory and Tech., vol. 49, no. 5, pp. 1006-1009, May 2001.

Prior Time Domain Methods

Laguerre-FDTD Methods

SLeEC (Simulation using Laguerre-Equivalent Circuit) [6]

� Equivalent circuit model� Infinite time simulation capability� Optimal # basis functions

� Node numbering scheme for memory efficiency� Dispersion� Skin effect

Laguerre - FDTD MethodLaguerre - FDTD Method


Laguerre-FDTD

CPU time 319 mins

Memory

consumption44 GB

SiO2

Si300 um

10 um

1000 um

1000 um

500 um500 um

20 um 150 um

100 um

1 mm 20 mm 1 mm

1 um

PEC boundary

20 mm

45 um

500 um

500 um100 mm

PEC boundary40 mm

L-FDTD

CST

CPU Time << FDTD

Memory > FDTD

(Can be reduced using

Domain Decomposition)

Simulation ResultsSimulation Results


� Steady-state Electrical Problem

� Steady-state thermal problem

),,,( Tzyxρ : Electrical Resistivity

),,( zyxφ : Electrical Potential

Current

Ohmic Loss �� Joule Heat:

Conductor

IRV =∆

),,(),,( zyxEJzyxPJoule

vvv⋅=

0),,(),,,(

1=

∇⋅∇ zyx

Tzyxφ

ρ

),,,( Tzyxk : Thermal conductivity

),,( zyxT : Temperature

Heat sources

Power from Transistors

),,( zyxP

(((( )))) ),,(),,(),,( zyxPzyxTzyxk −−−−====∇∇∇∇⋅⋅⋅⋅∇∇∇∇

),,,( Tzyxρ Joule heating

Current

Multi-core CPU

Stacked Cache Memory

Multi-physics – Interaction between Electrical and ThermalMulti-physics – Interaction between Electrical and Thermal


• Conductor electrical resistivity

20 40 60 80 100 120 140 160 180 2001.5x10

-8

2.0x10-8

2.5x10-8

3.0x10-8

3.5x10-8

4.0x10-8

4.5x10-8

5.0x10-8

Resis

tivit

y (

Oh

m*m

)

Temperature (Degree)

Silver

Copper

Aluminum

30% increase

• Silicon thermal conductivity[*]

[*] http://www.efunda.com/

Electrical and Thermal Properties of Metal and Silicon Vs Temperature

Electrical and Thermal Properties of Metal and Silicon Vs Temperature

Creates HotspotsIncreases Ohmic Loss


Combined IR Drop & Thermal AnalysisCombined IR Drop & Thermal Analysis

Convergent?No

Yes

Input

Static Electrical Solver*(formulation, mesh, solve)

Heat Sources Calculation

Static Thermal Solver*(formulation, mesh, solve)

Update Material Properties

Output

DC

IR DropThermal

Gradient

Joule Heating

T-Dependent

Resistance

J. Xie, D. Chung, M. Swaminathan, et al, “Electrical-thermal co-analysis for power delivery networks in 3D system integration,” IEEE International Conference on 3D System Integration (3DIC), pp. 1-4, Sept. 2009.

J.Xie, D. Chung, M. Swaminathan, M. Mcallister, et al, “Effect of system components on electrical and thermal characteristics for power delivery networks in 3D system integration,” 18th conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 113-116, Oct. 2009.


Max temperature v.s. flow velocity

J. Xie, M. Swaminathan, “Electrical-thermal co-simulation with micro-channel water cooling in 3D integration,” accepted

with revision by IEEE Trans. Advanced Packaging, 2010.

Correlation with measurement

3D System with micro-channels

40 50 60 70 80 90 100 11020

25

30

35

Ou

tlet

Tem

pera

ture

(D

eg

ree)

Flow Rate (m l/m in)

Simulation

Measurement

Heat Conduction, Air Convection and Micro-fluidic CoolingHeat Conduction, Air Convection and Micro-fluidic Cooling

20 40 60 80 100 120

30

40

50

60

70

80

90

100

Tem

pera

ture

(D

eg

ree)

Flow Rate (ml/min)

Max chip temp: Chip1Max chip temp: Chip2

Channel output temp: Chip1Channel output temp: Chip2


Temperature (Flow rate: 104 ml/min)

Temperature and IR drop with Micro-fluidic CoolingTemperature and IR drop with Micro-fluidic Cooling

Temperature

Decrease

Using Micro-channels

IR Drop

DecreasesUsing

Micro-channels

Steady State Steady State


29

Die Temperatures

X (mm)y (mm)

Die: 1.2 cm x 1.2 cm

Interposer: 3 cm x 3 cm

PCB: 10 cm x 10 cm

Convection coefficient: 20 W/(m2K)

Interposer thickness: 110 micron

Die thickness: 200 micron

TIM conductivity: 2 W/(m-k)

Ideal heat sink: 25 Celsius

Air convection for interposer and PCB

Interposer Temperature

PCB Temperature

Power Map

17 W

17 W

8 W

8 W

17 W

17 W8 W

8 W

Die1

(50 W)

Die2

(50 W)

Stacked Dies

X (mm)y (mm)

TSV Location

Top Die

Jianyong Xie, M. Swaminathan, "Electrical-thermal co-simulation of 3D integrated systems with micro-fluidic cooling and

Joule heating effects," IEEE Trans. on CPMT, vol. 1, no. 2, pp. 234-246, Jan. 2011.

Bottom Die

Temperature Gradients in a SystemTemperature Gradients in a System


Temperature Dependent TSV model

Temperature-dependent Copper conductivity[*]

Temperature-dependent Silicon Conductivity[*]

*W.-S. Zhao, X.-P. Wang, and W.-Y. Yin, "Electro-thermal effects in high density through silicon via (TSV) arrays," Progress In

Electromagnetics Research, Vol. 115, 2011.

Temperature Variation of Conductivity for Copper and Silicon

Temperature Variation of Conductivity for Copper and Silicon


0 0.5 1 1.5 2

x 10-9

-0.05

0

0.05

Co

up

led

No

ise

TIME

T= 25 C

T= 60 C

T= 95 C

T=110 C44.16 mv

34 mv

Coupling increases as

temperature increase

Coupling decreases as

temperature increase

Silicon substrate

Signal TSV-1 Signal TSV-2

Ground TSV-1 Ground TSV-2

umI RDLref 95_ =

umP TSVTSV 250=−

umhsub 100=

umd TSVTSV 130=−

Microprobe

Port 1

Microprobe

Port 2

30υm

Capacitive

Portion

Resistive

Portion

Xtalk decreases

with temperature

Temperature Dependent High Frequency EffectsTemperature Dependent High Frequency Effects


TSV and surrounding stressed region. Arrows indicate direction of differential thermal expansion

Courtesy: G. Subbarayan, Purdue Univ.

Thermal field

Keep outregion Distance

Mechanical StressMechanical StressThermal Induced Stress

Thermal Induced Stress

S. M. Sri-Jayantha, et al, "Thermomechanical modeling of 3D electronic packages," IBM J. RES. & DEV., Vol. 52, No. 6, Nov. 2008.

� TSV induced stress is very large at the TSV-silicon interface � Relatively small as the distance from the TSV increases� Keep Out Zones (KOZ) around the TSV to maximize

reliability and performance� KOZ ensures that there is no wiring, TSVs or other transistordevices in this region

CTE (Cu) ~ 17ppm/CCTE (Tung) ~ 4.5ppm/C

CTE (Si) ~ 3ppm/C

Linear coefficient @ 20C

Keep Out Zones (KOZ) – Need for Mechanical ModelingKeep Out Zones (KOZ) – Need for Mechanical Modeling


Insertion Loss

NEXT between 1 and others FEXT between 1 and others

1

50µm

100µm

1V Excitation

Keep Out Zones (KOZ) and TSV Electrical ResponseKeep Out Zones (KOZ) and TSV Electrical Response

Spread in IL

Spread in Coupling

Change in

Current Dist.


Concluding Thoughts …..Concluding Thoughts …..

Mechanical Stresses

Joule Heating/Electro-migration

Thermal Management

Signal Integrity

Place & Route

Multi-physics andMulti-scaleEnvironment neededFor the DesignOf 3D Heterogeneous SystemsTier 1

Thickness ~ 50 µmAc tive Face Down

Tier 1Thickness ~ 5 0 µm

Active Face Down

BackSide MetalPitc h ~ 5-25 µm

BackSide MetalPitch ~ 5-2 5 µ m

Package SubstrateThickness ~ 180 µm

Package SubstrateThickness ~ 1 80 µ m





TSVSize ~ 5-10 µmPitc h ~ 10-50 µm

TSVSize ~ 5-10 µm

Pitch ~ 10-50 µm

BGA BumpPitch ~ 0.65 mm

Height ~ 300 um

BGA BumpPitch ~ 0.6 5 mmHeight ~ 300 um

µ-BumpPitc h ~ 25-50 µm

µ-BumpPitch ~ 25-50 µm



Tier 2Thickness ~ 260 µm

Ac tive Face Down

Tier 2Thickness ~ 2 60 µ mActive Face Down

Multi-scale

Need for the modelingof the interaction betweenmultiple domains will only

increase for 3D!Time for the IEEE Community to Innovate!


epsilonlab.ece.gatech.edu; www.ipc.gatech.edu

Thank youThank you

Documents

Greetings from IEEE EMC Society & Georgia Techewh.ieee.org/r1/njcoast/slides/swaminathan_dl_emc_nj.pdf · IEEE EMC Society & Georgia Tech ... Thermal Management Joule Heating Thermal