EE-584 INTRODUCTION TO VLSI DESIGN AND

TESTING

A REPORT ON

3 BIT BARREL SHIFTER

GROUP - 8

IMTIAZ MOHAMMAD ABDUL

MANISH REDDY KOTHAPALLY PRASHANTH BUSA

VINAY KUMAR REDDY MUPPIDI

TABLE OF CONTENTS

1. INTRODUCTION......................................................................................................... 3

1.1 Block Diagram.......................................................................................................... 4 1.2 Barrel Shifter............................................................................................................. 5

2. TRANSMISSION GATE ............................................................................................. 6 2.1 Symbol ...................................................................................................................... 6 2.2 Schematic.................................................................................................................. 6 2.3 Layout ....................................................................................................................... 8 2.4 Simulation ................................................................................................................. 9

3. D FLIP FLOP.............................................................................................................. 10 3.1 Symbol .................................................................................................................... 10 3.2 Schematic................................................................................................................ 10 3.3 Layout ..................................................................................................................... 12 3.4 Simulation ............................................................................................................... 13

4. SHIFTER..................................................................................................................... 14 4.1 Symbol .................................................................................................................... 14 4.2 Schematic................................................................................................................ 14 4.3 Layout ..................................................................................................................... 16 4.4 Simulation ............................................................................................................... 17

5. BUFFER....................................................................................................................... 18 5.1 Symbol .................................................................................................................... 19 5.2 Schematic................................................................................................................ 19 5.3 Layout ..................................................................................................................... 21 5.4 Simulation ............................................................................................................... 22

6. Overall Circuit ............................................................................................................ 23 6.1 Schematic................................................................................................................ 23 6.2 Simulation ............................................................................................................... 24

7. Simulation with buffers at corners............................................................................ 25 7.1 Typical conditions................................................................................................... 30 7.2 Fast conditions ........................................................................................................ 28 7.3 Slow conditions....................................................................................................... 31

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TABLE OF FIGURES Figure 1: Block diagram of a 3 bit barrel shifter ................................................................ 4 Figure 2: Barrel shifter using transmission gates................................................................ 5 Figure 3: Symbol of transmission gate ............................................................................... 6 Figure 4: Schematic of transmission gate ........................................................................... 7 Figure 5: Layout of transmission gate ................................................................................ 8 Figure 6: Simulation output of transmission gate ............................................................... 9 Figure 7:Symbol of D-flipflop .......................................................................................... 10 Figure 8: Schematic of D-flipflop..................................................................................... 11 Figure 9: Layout of D-flipflop ......................................................................................... 12 Figure 10: Simulation output of D-flipflop....................................................................... 13 Figure 11: Symbol of barrel shifter................................................................................... 14 Figure 12: Schematic of barrel shifterFigure 12 ............................................................... 15 Figure 13: Layout of barrel shifter.................................................................................... 16 Figure 14: Simulation output of barrel shifter ................................................................. 17 Figure 15: Symbol of output buffer .................................................................................. 19 Figure 16: Schematic of output buffer .............................................................................. 20 Figure 17: Layout of output buffer ................................................................................... 21 Figure 18: Simulation output of output buffer.................................................................. 22 Figure 19: Overall circuit schematic................................................................................. 23 Figure 20: Simulation of the Overall circuit (DC Input) ................................................. 24 Figure 21: Simulation of overall circuit (Pulse Input) ...................................................... 25 Figure 22: Surface plot under typical conditions.............................................................. 27 Figure 23: Surface plot under fast conditions ................................................................... 30 Figure 24: Surface plot under slow conditions ................................................................. 33 Figure 25: Simulation of the circuit under typical conditions .......................................... 26 Figure 26:Simulation of the circuit under fast conditions ................................................ 29 Figure 27: Simulation of the circuit under slow conditions .............................................. 32

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1. INTRODUCTION

Barrel shifter is a basic circuit that shifts the given data input .In this report we discuss a 3 bit barrel shifter circuit in which the data is shifted by n bits where n is the user input. The circuit is designed such that the shift operation is performed in a single clock cycle depending on the select input (i.e. n).

1.1 Block Diagram The basic block diagram of a barrel shifter is as shown in the figure.

Figure 1: Block diagram of a 3 bit barrel shifter The above block has the following

• Inputs: Input data (3 bits), Shift Bits (S0, S1 and S2), Clock Signal. • Power inputs: VDD, GND. • Outputs: Output data (3 bits). A 3 bit input data is given to the circuit. The number of bits by which the data is to be shifted is specified by the shift inputs. (i.e. if the data is to be shifted by 0 bit, shift input S0 will be enabled, by 1 bit then S2 will be enabled and so on). The 3 bit Shifted data is obtained at the output. The 9 I/O pads have ESD protection and also have buffers to drive the load.

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1.2 Barrel Shifter The Barrel shifter is used mainly in arithmetic and logic units where shifting or rotating of data is required. The current project is dedicated in designing a barrel shifter for a test pad containing of 12 pins. The circuit consists of nine transmission gates connected as shown in the figure.

Figure 2: Barrel shifter using transmission gates There will be a propagation delay associated with each transmission gate, since each transmission gate has PMOS device, NMOS device and inverter. Let us proceed with the analysis of each block in the block diagram.

• D Flip Flop (Combination of transmission gates and inverters) • Shifter (Transmission gates) • Buffer ( Series of inverters)

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2. TRANSMISSION GATE A Transmission gate is a combination of a PMOS pass gate and a NMOS pass gate in parallel. Since NMOS passes logic lows well and PMOS passes logic highs well, combining both produces a transmission gate that passes both logic levels efficiently. The Propagation delay-times of this CMOS transmission gate is estimated as

tPHL = tPLH = 0.7 . (Rn // Rp) . CLoad

The capacitance on the S input of the transmission gate is the input capacitance of the NMOS device (Cinn). The capacitance on the S’ input is the input capacitance of the PMOS device (Cinp).

2.1 Symbol

Figure 3: Symbol of transmission gate

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2.2 Schematic The Schematic of a transmission gate is as shown in the figure.

Figure 4: Schematic of transmission gate

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2.3 Layout The layout of a transmission gate is shown in the figure. The layout is laid in such a manner to avoid any crossing of routing in similar layers. VDD and GND connections are given using Metal 1.The clock signal is given using poly.

Figure 5: Layout of transmission gate

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2.4 Simulation The above schematic is simulated using a test input and the resulting wave forms are as shown in the figure. From the figure it is seen that when the transmission gate is enabled ( C in the figure) the output follows the input. i.e. The transmission gate passes both logic levels efficiently.

Figure 6: Simulation output of transmission gate

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3. D FLIP FLOP

To implement an edge triggered FF we use two level sensitive latches in cascade. When the clock is low, the first stage tracks the D input and the second stage holds the previous output. When the clock goes high, the first stage captures the input and transfers it to the second stage. The first stage is often called the “master” latch, while the second stage is the “slave” latch. When clock is low ,T1 and T4 are on.T2 and T3 are off.

The D input flows through to point A and its complement to point B. When

clock goes high,T1 and T4 shut off while T2 and T3 turn on. This causes the value of the D input, when clock transitioned high, to be captured and passed to the Q output. When clock is low, T1 and T4 turn on. The value of D on the Q output can change states again when clock goes back high.

3.1 Symbol

Figure 7:Symbol of D-flipflop

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3.2 Schematic

The schematic of a D-FF is as shown in the figure.

Figure 8: Schematic of D-flipflop

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3.3 Layout

The layout of D flip flop is shown in the figure. The VDD and GND connections are given using Metal 2. Metal 1 is used in connecting the transmission gates and the inverters.

Figure 9: Layout of D-flipflop

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3.4 Simulation

The circuit of D flip flop shown above is tested for a given input and outputs are simulated. We can observe that when the clock signal is high and the input transforms from a logic low to a logic high the output starts to fall to a logic low.

Figure 10: Simulation output of D-flipflop

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4. SHIFTER

4.1 Symbol

Figure 11: Symbol of barrel shifter The Input data is given at A2A1A0. The shift data is given at S2S1S0. The Power pins are VDD and GND. The Output is obtained at B2BB1B0 B

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4.2 Schematic

The schematic of barrel shifter is shown in the figure.

Figure 12: Schematic of barrel shifterFigure 12

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4.3 Layout

The layout of the shifter circuit is as shown in the figure.

Figure 13: Layout of barrel shifter

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In the layout VDD and GND connections are given using Metal 2. The inputs A2A1A0 are connected using Metal 1. The outputs BB2B1B BB0 are also connected using metal 2.The Select inputs S2S1S0are connected using poly.

4.4 Simulation The shifter circuit is simulated for test inputs and the output obtained is as shown in the figure.

Figure 14: Simulation output of barrel shifter

The barrel shifter circuit is simulated with a test input. The data input is

A2A1A0 (101) and it is shifted by 2 bits (S2 is enabled).The output is BB2B1B BB0 (011).This is shown in the above simulation.

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5. BUFFER

Buffer is a circuit designed to drive large loads with minimum delay time. It can also be used to improve the signal strength. The buffer circuit is usually added between the on-chip logic and the I/O pads. In the design of the buffer, each inverter stage is made ‘A’ times the previous inverter stages’ width. The channel length is left unchanged, as any change will cause a variation in the process parameters. The calculation of the number of stages used, ‘N’, is also very important. The value of N determines the width and the length of the buffer. Making the inverters wider causes the resistance to decrease and the input capacitance to increase at the same time by a factor of ‘A’. Since both the resistance and the capacitance change in the opposite direction, the RC time delay remains constant. Hence the delay across the each stage remains essentially the same. By definition of delay time, tPLH = 0.7* Rp*Cload tPHL = 0.7* Rn*Cload using Cload= 20pF, Rp and Rn can be calculated . The propagation delay time is determined which is dependent on the internal capacitances. Therefore using tPLH, tPHL, Rp and Rn values, Cout Cin= (3/2)Cout Using Cin, N is determined as N= ln (Cload/Cin) A is determined as A= (Cload/Cin)^ (1/N)

Making N smaller makes the stages to have large W values, this makes the

input capacitance increase, which increases the propagation delay-time of the gate driving the particular stage of the inverter. If the value of ‘N’ is made large, the calculated W value is not as high as in the former case which decreases the input capacitance and hence causes a decrease in the time delay.

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5.1 Symbol

Figure 15: Symbol of output buffer

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5.2 Schematic

The schematic of a four stage buffer is as shown in the figure.

Figure 16: Schematic of output buffer The extremely high widths of the inverters are not implemented per se. A technique called “Folding” is employed wherein the large width transistors are implemented using transistors of smaller widths, connected in parallel.

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This technique helps in the reduction of white spaces and aids in the effective utilization of the available layout area. The layout of the output buffer employing folding technique is as in figure

5.3 Layout The layout of the buffer circuit using folded layout technique is as shown in the figure.

Figure 17: Layout of output buffer

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5.4 Simulation The buffer circuit is simulated for a simple test input and the output is observed if there is any distortion in the input. The output is the same as the input. The circuit is just employed to match the capacitance of the circuit and the load capacitance. The simulation output is as shown in the figure

Figure 18: Simulation output of output buffer

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6. Overall circuit:

6.1 Schematic The overall circuit schematic is shown in the figure. All the blocks described above are merged into a single block.

Figure 19: Overall circuit schematic

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6.2 Simulation The overall circuit of the 3 bit barrel shifter is simulated for test inputs. The simulation output is as shown in the figure.

Figure 20: Simulation of the Overall circuit (DC Input)

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Figure 21: Simulation of overall circuit (Pulse Input)

7. Simulation with buffers at corners: Corners here mean extreme conditions. The voltage from the power supply does not always remain at the same value. There may be some fluctuations and the circuit should be able to produce the desired output even though these fluctuations occur. Another important parameter to be considered is the temperature. The circuit that is being fabricated should be able to produce the same results when it is operated over a wide temperature range. Therefore the corner simulations are done to check if the circuit function as it is supposed to in all possible cases such as varying temperature and power supply.

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7.1 Typical conditions The schematic is simulated for typical condition and the output is as shown in the figure. The input to the circuit is A2A1A0 and output is BB2B1B BB0

Figure 22: Simulation of the circuit under typical conditions

To check the working of the circuit under different operating conditions the voltage is varied from +10% to – 10% of the actual value and the temperature is varied from -100C to 150C. The circuit is simulated for various combinations of these in the typical, fast and slow conditions to see the behavior. The results are imported to Excel and the graph of change in delay versus temperature and power supply is drawn. It can be seen that when the temperature is low due to the less number of charge carriers the delay of the Barrel shifter is high. The delay also increases with increase in the power supply.

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The advantage of 3D plot is that it is not necessary to calculate the delay for each and every combination of VDD and temperature. It is possible to interpolate the delay for all points in the table if we know the delay for the corners or extreme values. The following plot shows the variation in delay with change in temperature and VDD for typical conditions.

The schematic is first simulated for typical conditions by setting the model libraries at typical corner.

100

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-25

-100

1.62

1.8 1.98

0

50

100

150

DELAY(ns)

TEMP(c)VDD(v)

TYPICAL SURFACE PLOT

100-15050-1000-50

Figure 23: Surface plot under typical conditions (VDD v/s Temp v/s delay)

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The variation of frequency under typical conditions also affects the output as shown in the following table Time period Frequency Delay at output 1000ns 1 Mhz 20ns 200ns 5 Mhz 19.4ns 100ns 10 Mhz 19ns 50ns 20 Mhz 18.5ns 25ns 40 Mhz 18ns 10ns 100 Mhz 17ns 1ns 1 Ghz 9.1ns 500ps 2 Ghz 9ns 200ps 5 Ghz 14ns 100ps 10 Ghz X 50ps 20 Ghz X Table1: Frequency variations under typical conditions.

7.2 Fast conditions The schematic is simulated for fast conditions and the output is as shown in the figure.

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Figure 24:Simulation of the circuit under fast conditions

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The following plot show the variation in delay with change in temperature and VDD for typical conditions

-100 -50 -25 0 27 50 1001.62

1.9020406080

100120140160

DELAY(ns)

TEMP(c)

VDD(v)

FAST SURFACE PLOT

140-160120-140100-12080-10060-8040-6020-400-20

Figure 25: Surface plot under fast conditions

The variation of frequency under Fast conditions also affects the output as shown in the following table

Time period Frequency Delay at output 1000ns 1 Mhz X 200ns 5 Mhz 107ns 100ns 10 Mhz 79ns 50ns 20 Mhz 58ns 25ns 40 Mhz 44ns 10ns 100 Mhz 20ns 1ns 1 Ghz 14ns 500ps 2 Ghz 12ns 200ps 5 Ghz 5ns 100ps 10 Ghz X 50ps 20 Ghz X Table2: Frequency variations under fast conditions

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A Schmoo plot is also drawn for simulations under fast conditions and is as

follows VDD\TEMP -100 -50 -25 0 27 50 100 150

1.62v X X X 1 16ns 1 13ns

1 10n

1 8n X

1.70v X X X 1 53ns 1 20ns

1 19ns

1 11ns

1 7ns

1.80v 1 21ns

1 18ns

1 10ns

1 9ns

1 8ns

1 7.5ns

1 7ns

1 6n

1.90v X X 1 96ns 1 87ns

1 52ns

1 30ns

1 11ns

1 8ns

1.98v X X X X 1 46ns 1 20ns

1 19ns

1 18ns

VDD\TEMP -100 -50 -25 0 27 50 100 150

7.3 Slow conditions

The schematic is simulated for slow conditions and the output is as shown in the figure.

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Figure 26: Simulation of the circuit under slow conditions

The following plot show the variation in delay with change in temperature and VDD for typical conditions

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-50 -25 0 27 50 100 1501.62

1.9050

100150200250300350400450

DELAY(ns)

TEMP(c)

VDD(v)

SLOW SURFACE PLOT

400-450350-400300-350250-300200-250150-200100-15050-1000-50

Figure 27: Surface plot under slow conditions Time period Frequency Delay at output 1000ns 1 Mhz X 200ns 5 Mhz 320ns 100ns 10 Mhz 200ns 50ns 20 Mhz 100ns 25ns 40 Mhz 60ns 10ns 100 Mhz 35ns 1ns 1 Ghz 28ns 500ps 2 Ghz 100ns 200ps 5 Ghz X 100ps 10 Ghz X 50ps 20 Ghz X Table3: frequency variations under slow conditions.

A Schmoo plot is also drawn for simulations under slow conditions and is as follows

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VDD\TEMP -100 -50 -25 0 27 50 100 150 1.62v X X X X 1 225ns

1 205ns

1 190ns

1 180ns

1.70v X X 1 235ns 1 207ns

1 192ns

1 190ns

1 180ns

1 170ns

1.80v X

1 200ns

1 193ns

1 180ns

1 175ns

1 173ns

1 172ns X

1.90v 1 203ns

1 177ns

1 172ns

1 170ns

1 170ns

1 170ns

1 165ns X

1.98v 1 180ns

1 165ns

1 162ns

1 155ns

1 150ns

1 148ns X X

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REFERENCE:

1. CMOS circuit design, layout and simulation, 2nd edition by R. Jacob Baker. 2. Basic VLSI design by Douglas A Pucknell, Kamran Eshraghan

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1. INTRODUCTION1.1 Block Diagram1.2 Barrel Shifter

2. TRANSMISSION GATE2.1 Symbol2.2 Schematic2.3 Layout2.4 Simulation

3. D FLIP FLOP3.1 Symbol3.2 Schematic3.3 Layout3.4 Simulation

4. SHIFTER 4.1 Symbol 4.2 Schematic4.3 Layout4.4 Simulation

5. BUFFER 5.1 Symbol 5.2 Schematic5.3 Layout5.4 Simulation

6. Overall circuit:6.1 Schematic6.2 Simulation

7. Simulation with buffers at corners:7.1 Typical conditions7.2 Fast conditions 7.3 Slow conditions