GSM Based Patient Mono to Ring

8/3/2019 GSM Based Patient Mono to Ring

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GSM Based Patient Monitoring System

Chapter 1

Introduction

Mobile Telemedicine System are becoming more important all the time, specially

in care of patients that are isolated or travelling ,far from a reference hospitals.

Incorporating technologies such as GSM to this system allow wireless transmission to

health or control centers.

This project provides an excellent equipment using Wireless technology

especially for monitoring the patient and sending data over GSM to the Doctor. This

system also provides an excellent requirment option when ever patient needed using

touch screen. The equipment has a better fesability to send the data continuosly from time

to time.

This paper describes a low cost, portable system with wireless transmission

capabilities for the processing and visualization in real time of the electrical activity of

the heart to a mobile phone , a PDA.

1.1 System Discription

The system consists of three modules: the patients acquisition and processing for

monitoring parameter of patient,the medical control unit board(Micro controller), and the

medical cotrol unit for receiving data as Mobile .The system block diagram is as shown

in fig.1.


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Fig.1:System diagram

The Micro-controller module is a tool with a user interface that simulates an

heart beat monitor and offers the functionalities as to send the data over a wireless GSM

to the mobile and LCD module. The aquisition module consists of a amplifier, a

microcontroller and a GSM for wireless transmission, touch screen with a voice

activation module according to the option specified for the patient .

The purpose of choosing GSM as a transmission module is that, it provide a data

transfer over a global area. It is a wide range technology that allows security and robust

communications. For data transfer using GSM the protocol used is AT commands .

1.2 Background of the Project

The software application and the hardware implementation help the

microcontroller to read the data from the Sensors(Heartbeat and Temperature) through

the reader and send the data using GSM and requirement of the patient is indiacated by

the Voice module. The measure of efficiency is based on the range of the GSM

communication to the mobile is used in this project and how fast the microcontroller can

read the data from the Sensor and perform the specified task. The system is totally

designed using GSM and embedded systems technology. The performance of the design

is maintained by controlling unit.

The GSM with micro controller will be wired to the machine(Micro-controller) and to

that to sensors. Whenever any sensors crosses the level of heart beat or temperature , the


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depending on the logic designed in the controller, it will send the required data over a

GSM device using AT commands and it will send SMS to the owner .

Touch Screen is also used to fullfill the patient needs when he/she is

unable to speak. And it is done by Voice activated module which can generate a voice to

a perticular operation .The voice activated IC used is APR9600.

1.3 Organization of the Thesis

In view of the proposed thesis work explanation of theoretical aspects and

algorithms used in this work are presented as per the sequence described below.

Chapter1: Describes a brief review of the objectives and goals of the work.

Chapter2: Discusses the existing technologies and the study of various

technologies in detail.

Chapter3: Describes the Block diagram of the project and its description. The

construction and description of various modules used for the application are described in

detail.

Chapter4: Explains the Software tools required for the project, the Code

developed for the design.

Chapter5:Presents the results, overall conclusions of the study and proposes

possible improvements and directions of future research work.


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Chapter 2

Overview of the technologies used

Embedded Systems:

An embedded system can be defined as a computing device that does a specific focused job. Appliances such as the air-conditioner, VCD player, DVD player, printer, fax

machine, mobile phone etc. are examples of embedded systems. Each of these appliances

will have a processor and special hardware to meet the specific requirement of the

application along with the embedded software that is executed by the processor for

meeting that specific requirement.

The embedded software is also called firm ware. The desktop/laptop computer is a

general purpose computer. You can use it for a variety of applications such as playing

games, wordprocessing, accounting, software development and so on.

In contrast, the software in the embedded systems is always fixed listed below:

Embedded systems do a very specific task, they cannot be programmed to do different

things. Embedded systems have very limited resources, particularly the memory.

Generally, they do not have secondary storage devices such as the CDROM or the floppy

disk. Embedded systems have to work against some deadlines. A specific job has to be

completed within a specific time. In some embedded systems, called real-time systems,

the deadlines are stringent. Missing a deadline may cause a catastrophe-loss of life or

damage to property. Embedded systems are constrained for power. As many embedded

systems operate through a battery, the power consumption has to be very low.

Some embedded systems have to operate in extreme environmental conditions such as

very high temperatures and humidity.

Following are the advantages of Embedded Systems:

1. They are designed to do a specific task and have real time performance

constraints which must be met.

2. They allow the system hardware to be simplified so costs are reduced.


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3. They are usually in the form of small computerized parts in larger devices which

serve a general purpose.

4. The program instructions for embedded systems run with limited computer

hardware resources, little memory and small or even non-existent keyboard or

screen.

Introduction to GSM Technology

The GSM/GPRS modem comes with a serial interface through which the modem

can be controlled using AT command interface. An antenna and a power adapter are

provided. The figure of GSM is shown in Fig2.

The basic segregation of working of the modem is as under:

Voice

SMS

GSM Data Calls

GPRS

GSM converter will be add-on device to be attached between a

terminal which wants data transfer and the GSM modem. This GSM coverter will

take care of call establishment where the embedded device cannot make a call.

The converter will remain trasnparent through-out the call once call is established.

The BSM converter will be a very small piece of hardware possibly embedded

inside the cable itself. GSM System has a frequency bandwidth of 200kHz and a

data transmission rate of approximately 270kpbs.

One of the key features of GSM is the Subscriber identity

module,commonly called known as SIM card. The SIM is a detachable smart card

containing the users subscription information and phone book. This allows the

user to retain his or her information after switching handsets.


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Fig: GSM/GPRS Modem.

Definition of GSM(TDMA) technology 1991

GSM, which stands for Global System for Mobile communications,

reigns as the worlds most widely used cell phone technology. Cell phones use a cell

phone service carriers(TDMA) GSM network by searching for cell phone towers in the

nearby area.

GSM uses digital technology and is a second-generation (2G) cell

phone system. GSM, which predates CDMA, is especially strong in Europe. EDGE is

faster than GSM and was built upon GSM. The GSM platform is a hugely successful

wireless technology and an unprecedented story of global achievement and cooperation.

Todays GSM platform is living, growing and evolving and already offers an expanded

and feature-rich family of voice and multimedia services. New developments that will

push up data transfer rates for GSM users are HSCSD (high speed circuit switched data)

and GPRS (general packet radio service) are now available.

.


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Chapter 3

Hardware Implementation of the Project

This chapter briefly explains about the Hardware Implementation of the project. It

discusses the design and working of the design with the help of block diagram and circuitdiagram and explanation of circuit diagram in detail. It explains the features of LPC2148

microcontroller. It also explains the various modules used in this project.

3.1 Project Design

The implementation of the project design can be divided in two parts.

Hardware implementation

Firmware implementation

Hardware implementation deals in drawing the schematic on the plane paper according to

the application, testing the schematic design over the breadboard using the various ICs to

find if the design meets the objective, carrying out the PCB layout of the schematic tested

on breadboard, finally preparing the board and testing the designed hardware.

The firmware part deals in programming the microcontroller so that it can control the

operation of the ICs used in the implementation. In the present work, we have used the

Orcad design software for PCB circuit design, the Keil v4 software development tool to

write and compile the source code, which has been written in the C language. The

Flashmagic programmer has been used to write this compile code into the

microcontroller. The firmware implementation is explained in the next chapter.

The project design and principle are explained in this chapter using the block diagram

and circuit diagram. The block diagram discusses about the required components of thedesign and working condition is explained using circuit diagram and system wiring

diagram.


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3.1.1 Block Diagram of the Project and its Description

The block diagram of the design is as shown in Fig 3.1. It consists of power

supply unit, microcontroller LPC2148, GSM module, Heart-beat sensor and Temperature

sensor, LCD display, Touch screen, voice IC APR9600, LM386 operational amplifier

and loudspeaker. The brief description of each unit is explained as follows.

3.2 Power Supply:

The input to the circuit is applied from the regulated power supply. The a.c. input i.e.,

230V from the mains supply is step down by the transformer to 12V and is fed to a

rectifier. The output obtained from the rectifier is a pulsating d.c voltage. So in order to

get a pure d.c voltage, the output voltage from the rectifier is fed to a filter to remove any

a.c components present even after rectification. Now, this voltage is given to a voltage

regulator to obtain a pure constant dc voltage.


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Transformer:

Usually, DC voltages are required to operate various electronic equipment and

these voltages are 5V, 9V or 12V. But these voltages cannot be obtained directly. Thus

the a.c input available at the mains supply i.e., 230V is to be brought down to the

required voltage level. This is done by a transformer. Thus, a step down transformer is

employed to decrease the voltage to a required level.

Rectifier:

The output from the transformer is fed to the rectifier. It converts A.C. into

pulsating D.C. The rectifier may be a half wave or a full wave rectifier. In this project, a

bridge rectifier is used because of its merits like good stability and full wave rectification.

Filter:

Capacitive filter is used in this project. It removes the ripples from the output of

rectifier and smoothens the D.C. Output received from this filter is constant until themains voltage and load is maintained constant. However, if either of the two is varied,

D.C. voltage received at this point changes. Therefore a regulator is applied at the output

stage.


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Voltage regulator:

As the name itself implies, it regulates the input applied to it. A voltage regulator

is an electrical regulator designed to automatically maintain a constant voltage level. In

this project, power supply of 5V and 12V are required. In order to obtain these voltage

levels, 7805 and 7812 voltage regulators are to be used. The first number 78 represents

positive supply and the numbers 05, 12 represent the required output voltage levels.

3.3 LPC2141/42/44/46/48

General description

The LPC2141/42/44/46/48 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S

CPU with real-time emulation and embedded trace support, that combine microcontroller

with embedded high speed flash memory ranging from 32 kB to 512 kB. A 128-bit wide

memory interface and a unique accelerator architecture enable 32-bit code execution at

the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb

mode reduces code by more than 30 % with minimal performance penalty. Due to their

tiny size and low power consumption, LPC2141/42/44/46/48 are ideal for applications

where miniaturization is a key requirement, such as access control and point-of-sale.

Serial communications interfaces ranging from a USB 2.0 Full-speed device, multiple

UARTs, SPI, SSP to I2C-bus and on-chip SRAM of 8 kB up to 40 kB, make these

devices very well suited for communication gateways and protocol converters, soft

modems, voice recognition and low end imaging, providing both large buffer size and

high processing power. Various 32-bit timers, single or dual 10-bit ADC(s), 10-bit DAC,

PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive external

interrupt pins make these microcontrollers suitable for industrial control and medical

systems.

Features

1. 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

2. 8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash

memory. 128-bit wide interface/accelerator enables high-speed 60 MHz

operation.


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3. In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot

loader software. Single flash sector or full chip erase in 400 ms and programming

of 256 bytes in 1 ms.

4. EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with

the on-chip RealMonitor software and high-speed tracing of instruction execution.

5. USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM. In

addition, the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by

DMA.

6. One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a total of

6/14 analog inputs, with conversion times as low as 2.44 s per channel.

7. Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only).

8. Two 32-bit timers/external event counters (with four capture and four compare

channels each), PWM unit (six outputs) and watchdog.

9. Low power Real-Time Clock (RTC) with independent power and 32 kHz clock

input.

Single-chip 16-bit/32-bit microcontrollers

Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400

kbit/s), SPI and SSP with buffering and variable data length capabilities.

Vectored Interrupt Controller (VIC) with configurable priorities and vectoraddresses.

Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.

Up to 21 external interrupt pins available.

60 MHz maximum CPU clock available from programmable on-chip PLL with

settling time of 100 s.

On-chip integrated oscillator operates with an external crystal from 1 MHz to 25

MHz.

Power saving modes include Idle and Power-down.

Individual enable/disable of peripheral functions as well as peripheral clock

scaling for additional power optimization.

Processor wake-up from Power-down mode via external interrupt or BOD.

Block diagram


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Pinning information


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Pin description


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[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10

ns slew rate control.

[2] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10

ns slew rate control. If configured for an input function, this pad utilizes built-in glitch

filter that blocks pulses shorter than 3 ns.

[3] Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It

requires external pull-up to provide an output functionality.

[4] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew

rate control) and analog input function. If configured for an input function, this pad


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utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an

ADC input, digital section of the pad is disabled.

[5] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew

rate control) and analog output function. When configured as the DAC output, digital

section of the pad is disabled.

[6] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with

TTL levels and hysteresis and 10 ns slew rate control. The pull-up resistors value

typically ranges from 60 k to 300 k.

[7] Pad is designed in accordance with the Universal Serial Bus (USB) specification,

revision 2.0 (Full-speed and Low-speed mode only).

[8] 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function

only.

[9] Pad provides special analog functionality.

1. Functional description

Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed Complex

Instruction Set Computers (CISC). This simplicity results in a high instruction throughput

and impressive real-time interrupt response from a small and cost-effective processor

core. Pipeline techniques are employed so that all parts of the processing and memory

systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory. The

ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb,

which makes it ideally suited to high-volume applications with memory restrictions, or

applications where code density is an issue. The key idea behind Thumb is that of a

super-reduced instruction set. Essentially, the


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ARM7TDMI-S processor has two instruction sets:

The standard 32-bit ARM set.

A 16-bit Thumb set.

The Thumb sets 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARMs performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system. The

particular flash implementation in the LPC2141/42/44/46/48 allows for full speed

execution also in ARM mode. It is recommended to program performance critical and

short code sections (such as interrupt service routines and DSP algorithms) in ARM

mode. The impact on the overall code size will be minimal but the speed can be increased

by 30% over Thumb mode.

2. On-chip flash program memory

The LPC2148 incorporates a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB flash

memory system respectively. This memory may be used for both code and data storage.

Programming of the flash memory may be accomplished in several ways. It may be

programmed In System via the serial port. The application program may also erase and/or

program the flash while the application is running, allowing a great degree of flexibility

for data storage field firmware upgrades, etc. Due to the architectural solution chosen for

an on-chip boot loader, flash memory available for users code on LPC2141/42/44/46/48

is 32 kB, 64 kB, 128 kB, 256 kB and 500 kB respectively.

The LPC2141/42/44/46/48 flash memory provides a minimum of 100,000 erase/write

cycles and 20 years of data-retention.

3. On-chip static RAM

On-chip static RAM may be used for code and/or data storage. The SRAM may

be accessed as 8-bit, 16-bit, and 32-bit. The LPC2141, LPC2142/44 and LPC2146/48


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provide 8 kB, 16 kB and 32 kB of static RAM respectively. In case of LPC2146/48 only,

an 8 kB SRAM block intended to be utilized mainly by the USB can also be used as a

general purpose RAM for data storage and code storage and execution.

4. Memory map

The LPC2141/42/44/46/48 memory map incorporates several distinct regions, as shown

in Figure 5. In addition, the CPU interrupt vectors may be remapped to allow them to

reside in either flash memory (the default) or on-chip static RAM. This is described in

System control.


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5. Interrupt controller

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs andcategorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and

non-vectored IRQ as defined by programmable settings. The programmable assignment

scheme means that priorities of interrupts from the various peripherals can be

dynamically assigned and adjusted. Fast interrupt request (FIQ) has the highest priority.

If more than one request is assigned to FIQ, the VIC combines the requests to produce


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the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when

only one request is classified as FIQ, because then the FIQ service routine does not need

to branch into the interrupt service routine but can run from the interrupt vector location.

If more than one request is assigned to the FIQ class, the FIQ service routine will read a

word from the VIC that identifies which

FIQ source(s) is (are) requesting an interrupt. Vectored IRQs have the middle priority.

Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt

requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the

highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority. The VIC combines the requests from all the

vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The

IRQ service routine can start by reading a register from the VIC and jumping there. If any

of the vectored IRQs are pending, the VIC

provides the address of the highest-priority requesting IRQs service routine, otherwise it

provides the address of a default routine that is shared by all the non-vectored IRQs. The

default routine can read another VIC register to see what IRQs are active.

Interrupt sources

Each peripheral device has one interrupt line connected to the Vectored Interrupt

Controller, but may have several internal interrupt flags. Individual interrupt flags may

also represent more than one interrupt source.

6. Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between

the pin and the on chip peripherals. Peripherals should be connected to the appropriate

pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity

of any enabled peripheral function that is not mapped to a related pin should be

considered undefined. The Pin Control Module with its pin select registers defines the

functionality of the microcontroller in a given hardware environment. After reset all pins


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of Port 0 and 1 are configured as input with the following exceptions: If debug is enabled,

the JTAG pins will assume their JTAG functionality; if trace is enabled, the Trace pins

will assume their trace functionality. The pins associated with the I2C0 and I2C1

interface are open drain.

7. Fast general purpose parallel I/O (GPIO)

Device pins that are not connected to a specific peripheral function are controlled by

the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

LPC214148 introduces accelerated GPIO functions over prior LPC2000 devices:

GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing.

Mask registers allow treating sets of port bits as a group, leaving other bits unchanged.

All GPIO registers are byte addressable.

Entire port value can be written in one instruction.

Features

Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

Direction control of individual bits.

Separate control of output set and clear.

All I/O default to inputs after reset.

8. 10-bit ADC

The LPC2141/42 contain one and the LPC2144/46/48 contain two analog to digital

converters. These converters are single 10-bit successive approximation analog to digital

converters. While ADC0 has six channels, ADC1 has eight channels. Therefore, total

number of available ADC inputs for LPC2141/42 is 6 and for LPC2144/46/48 is 14.


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Features

10 bit successive approximation analog to digital converter.

Measurement range of 0 V to VREF (2.0 V VREF VDDA).

Each converter capable of performing more than 400,000 10-bit samples per second.

Every analog input has a dedicated result register to reduce interrupt overhead.

Burst conversion mode for single or multiple inputs.

Optional conversion on transition on input pin or timer match signal.

Global Start command for both converters (LPC2142/44/46/48 only).

9. 10-bit DAC

The DAC enables the LPC2141/42/44/46/48 to generate a variable analog output. The

maximum DAC output voltage is the VREF voltage.

9.1 Features

10-bit DAC.

Buffered output.

Power-down mode available.

Selectable speed versus power.

10. USB 2.0 device controller

The USB is a 4-wire serial bus that supports communication between a host and a

number (127 max) of peripherals. The host controller allocates the USB bandwidth to

attached devices through a token based protocol. The bus supports hot plugging,

unplugging, and dynamic configuration of the devices. All transactions are initiated by

the host controller. The LPC2141/42/44/46/48 is equipped with a USB device controller

that enables 12 Mbit/s data exchange with a USB host controller. It consists of a register

interface, serial interface engine, endpoint buffer memory and DMA controller. The serial

interface engine decodes the USB data stream and writes data to the appropriate end point

buffer memory. The status of a completed USB transfer or error condition is indicated via

status registers. An interrupt is also generated if enabled. A DMA controller (available in

LPC2146/48 only) can transfer data between an endpoint buffer and the USB RAM.


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10.1 Features

Fully compliant with USB 2.0 Full-speed specification.

Supports 32 physical (16 logical) endpoints.

Supports control, bulk, interrupt and isochronous endpoints.

Scalable realization of endpoints at run time.

Endpoint maximum packet size selection (up to USB maximum specification) by

software at run time.

RAM message buffer size based on endpoint realization and maximum packet size.

Supports SoftConnect and GoodLink LED indicator. These two functions are sharing

one pin.

Supports bus-powered capability with low suspend current.

Supports DMA transfer on all non-control endpoints (LPC2146/48 only).

One duplex DMA channel serves all endpoints (LPC2146/48 only).

Allows dynamic switching between CPU controlled and DMA modes (only in

LPC2146/48).

Double buffer implementation for bulk and isochronous endpoints.


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11. UARTs

The LPC2141/42/44/46/48 each contains two UARTs. In addition to standard

transmit and receive data lines, the LPC2144/46/48 UART1 also provide a full modem

control handshake interface. Compared to previous LPC2000 microcontrollers, UARTs

in LPC2141/42/44/46/48 introduce a fractional baud rate generator for both UARTs,

enabling these microcontrollers to achieve standard baudrates such as 115200 with any

crystal frequency above 2 MHz. In addition, auto-CTS/RTS flow-control functions are

fully implemented in hardware (UART1 in LPC2144/46/48 only).

11.1 Features

16 byte Receive and Transmit FIFOs.

Register locations conform to 550 industry standard.

Receiver FIFO trigger points at 1, 4, 8, and 14 bytes

Built-in fractional baud rate generator covering wide range of baud rates without a need

for external crystals of particular values.

Transmission FIFO control enables implementation of software (XON/XOFF) flow

control on both UARTs.

LPC2144/46/48 UART1 equipped with standard modem interface signals. This module

also provides full support for hardware flow control (auto-CTS/RTS).

12. I2C-bus serial I/O controller


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The LPC2141/42/44/46/48 each contain two I2C-bus controllers. The I2C-bus is

bidirectional, for inter-IC control using only two wires: a serial clock line (SCL), and a

serial data line (SDA). Each device is recognized by a unique address and can operate as

either a receiver-only device (e.g., an LCD driver or a transmitter with the capability to

both receive and send information (such as memory)). Transmitters and/or receivers can

operate in either master or slave mode, depending on whether the chip has to initiate a

data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be controlled

by more than one bus master connected to it. The I2C-bus implemented in

LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s (Fast I2C-bus).

12.1 Features

Compliant with standard I2C-bus interface.

Easy to configure as master, slave, or master/slave.

Programmable clocks allow versatile rate control.

Bidirectional data transfer between masters and slaves.

Multi-master bus (no central master).

Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

The I2C-bus can be used for test and diagnostic purposes.

13. SPI serial I/O controller

The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full

duplex serial interface, designed to handle multiple masters and slaves connected to a

given bus. Only a single master and a single slave can communicate on the interface

during a given data transfer. During a data transfer the master always sends a byte of data

to the slave, and the slave always sends a byte of data to the master.


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13.1 Features

Compliant with Serial Peripheral Interface (SPI) specification.

Synchronous, Serial, Full Duplex, Communication.

Combined SPI master and slave.

Maximum data bit rate of one eighth of the input clock rate.

14. SSP serial I/O controller

The LPC2148 contains one SSP. The SSP controller is capable of operation on a

SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the

bus. However, only a single master and a single slave can communicate on the bus during

a given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to

16 bits of data flowing from the master to the slave and from the slave to the master.

Often only one of these data flows carries meaningful data.

14.1 Features

Compatible with Motorolas SPI, TIs 4-wire SSI and National Semiconductors

Microwire buses.

Synchronous serial communication.

Master or slave operation.

8-frame FIFOs for both transmit and receive.

Four bits to 16 bits per frame.

15. General purpose timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock and optionally generate interrupts or perform other actions at

specified timer values, based on four match registers. It also includes four capture inputs

to trap the timer value when an input signal transition, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with or and and, as well as broadcast functions among them. The

LPC2141/42/44/46/48 can count external events on one of the capture inputs if the


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minimum external pulse is equal or longer than a period of the PCLK. In this

configuration, unused capture lines can be selected as regular timer capture inputs, or

used as external interrupts.

15.1 Features

A 32-bit timer/counter with a programmable 32-bit prescaler.

External event counter or timer operation.

Four 32-bit capture channels per timer/counter that can take a snapshot of the timer

value when an input signal transitions. A capture event may also optionally generate an

interrupt.

Four 32-bit match registers that allow:

Continuous operation with optional interrupt generation on match.

Stop timer on match with optional interrupt generation.

Reset timer on match with optional interrupt generation.

Four external outputs per timer/counter corresponding to match registers, with the

following capabilities:

Set LOW on match.

Set HIGH on match.

Toggle on match.

Do nothing on match.

16. Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount

of time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to feed (or reload) the watchdog within a predetermined

amount of time.

16.1 Features

Internally resets chip if not periodically reloaded.


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Debug mode.

Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

Flag to indicate watchdog reset.

Programmable 32-bit timer with internal pre-scaler.

Selectable time period from (TPCLK 256 4) to (TPCLK 232 4) in multiples of

TPCLK 4.

17. Real-time clock

The RTC is designed to provide a set of counters to measure time when normal or idle

operating mode is selected. The RTC has been designed to use little power, making it

suitable for battery powered systems where the CPU is not running continuously (Idle

mode).

17.1 Features

Measures the passage of time to maintain a calendar and clock.

Ultra-low power design to support battery powered systems.

Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day

of Year.

Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the

external crystal/oscillator input at XTAL1. Programmable reference clock divider allows

fine adjustment of the RTC.

Dedicated power supply pin can be connected to a battery or the main 3.3 V.

18. Pulse width modulator

The PWM is based on the standard timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC2141/42/44/46/48. The timer is designed

to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or

perform other actions when specified timer values occur, based on seven match registers.


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The PWM function is also based on match register events. The ability to separately

control rising and falling edge locations allows the PWM to be used for more

applications. For instance, multi-phase motor control typically requires three non-

overlapping PWM outputs with individual control of all three pulse widths and positions.

Two match registers can be used to provide a single edge controlled PWM output.

One match register (MR0) controls the PWM cycle rate, by resetting the count upon

match. The other match register controls the PWM edge position. Additional single edge

controlled PWM outputs require only one match register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM outputs will all

have a rising edge at the beginning of each PWM cycle, when an MR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled.

Again, the MR0 match register controls the PWM cycle rate. The other match registers

control the two PWM edge positions. Additional double edge controlled PWM outputs

require only two match registers each, since the repetition rate is the same for all PWM

outputs. With double edge controlled PWM outputs, specific match registers control the

rising and falling edge of the output. This allows both positive going PWM pulses (when

the rising edge occurs prior to the falling edge), and negative going PWM pulses (when

the falling edge occurs prior to the rising edge).

18.1 Features

Seven match registers allow up to six single edge controlled or three double edge

controlled PWM outputs, or a mix of both types.

The match registers also allow:

Continuous operation with optional interrupt generation on match.

Stop timer on match with optional interrupt generation.

Reset timer on match with optional interrupt generation.

Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the

output is a constant LOW. Double edge controlled PWM outputs can have either edge


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occur at any position within a cycle. This allows for both positive going and negative

going pulses.

Pulse period and width can be any number of timer counts. This allows complete

flexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

Double edge controlled PWM outputs can be programmed to be either positive going or

negative going pulses.

Match register updates are synchronized with pulse outputs to prevent generation of

erroneous pulses. Software must release new match values before they can become

effective.

May be used as a standard timer if the PWM mode is not enabled.

A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

19. System control

19.1 Crystal oscillator

On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz.

The oscillator output frequency is called fosc and the ARM processor clock frequency is

referred to as CCLK for purposes of rate equations, etc. fosc and CCLK are the same

value unless the PLL is running and connected. Refer to Section 6.19.2 PLL for

additional information.

19.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current

Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in

practice, the multiplier value cannot be higher than 6 on this family of microcontrollers

due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz

to 320 MHz, so there is an additional divider in the loop to keep the CCO within its

frequency range while the PLL is providing the desired output frequency. The output

divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the

minimum output divider value is 2,


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it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and

bypassed following a chip reset and may be enabled by software. The program must

configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a

clock source. The PLL settling time is 100 s.

19.3 Reset and wake-up timer

Reset has two sources on the LPC2141/42/44/46/48: the RESET pin and watchdog reset.

The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of

chip reset by any source starts the Wake-up Timer (see Wake-up Timer description

below), causing the internal chip reset to remain asserted until the external reset is de-

asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip

flash controller has completed its initialization. When the internal reset is removed, the

processor begins executing at address 0, which is the reset vector. At that point, all of the

processor and peripheral registers have been initialized to predetermined values.

The Wake-up Timer ensures that the oscillator and other analog functions required for

chip operation are fully functional before the processor is allowed to execute instructions.

This is important at power on, all types of reset, and whenever any of the aforementioned

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mode, any wake-up of the processor from Power-down mode

makes use of the Wake-up Timer.

The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufficient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of VDD ramp (in the case of power on), the type of

crystal and its electrical characteristics (if a quartz crystal is used), as well as any other

external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the

existing ambient conditions.


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19.4 Brownout detector

The LPC2141/42/44/46/48 includes 2-stage monitoring of the voltage on the VDD pins.

If this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the VIC. This

signal can be enabled for interrupt; if not, software can monitor the signal by reading

dedicated register. The second stage of low voltage detection asserts reset to inactivate

the LPC2141/42/44/46/48 when the voltage on the VDD pins falls below 2.6 V. This

reset prevents alteration of the flash as operation of the various elements of the chip

would otherwise become unreliable due to low voltage. The BOD circuit maintains this

reset down below 1 V, at which point the POR circuitry maintains the overall reset. Both

the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this

hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event

loop to sense the condition.

19.5 Code security

This feature of the LPC2148 allows an application to control whether it can be debugged

or protected from observation. If after reset on-chip boot loader detects a valid checksum

in flash and reads 0x8765 4321 from address 0x1FC in flash, debugging will be disabled

and thus the code in flash will be protected from observation. Once debugging is

disabled, it can be enabled only by performing a full chip erase using the ISP.

19.6 External interrupt inputs

The LPC2141/42/44/46/48 include up to nine edge or level sensitive External Interrupt

Inputs as selectable pin functions. When the pins are combined, external events can be

processed as four independent interrupt signals. The External Interrupt Inputs can

optionally be used to wake-up the processor from Power-down mode. Additionally

capture input pins can also be used as external interrupts without the option to wake the

device up from Power-down mode.

19.7 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip


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flash memory, or to the on-chip static RAM. This allows code running in different

memory spaces to have control of the interrupts.

19.8 Power control

The LPC2141/42/44/46/48 supports two reduced power modes: Idle mode and Power-

down mode. In Idle mode, execution of instructions is suspended until either a reset or

interrupt occurs. Peripheral functions continue operation during Idle mode and may

generate interrupts to cause the processor to resume execution. Idle mode eliminates

power used by the processor itself, memory systems and related controllers, and internal

buses. In Power-down mode, the oscillator is shut down and the chip receives no internal

clocks. The processor state and registers, peripheral registers, and internal SRAM values

are preserved throughout Power-down mode and the logic levels of chip output pins

remain static.

The Power-down mode can be terminated and normal operation resumed by either a reset

or certain specific interrupts that are able to function without clocks. Since all dynamic

operation of the chip is suspended, Power-down mode reduces chip power consumption

to nearly zero. Selecting an external 32 kHz clock instead of the PCLK as a clock-source

for the on-chip RTC will enable the microcontroller to have the RTC active during

Power-down mode. Power-down current is increased with RTC active. However, it is

significantly lower than in Idle mode. A Power Control for Peripherals feature allows

individual peripherals to be turned off if they are not needed in the application, resulting

in additional power savings during active and idle mode.

19.9 VPB bus

The VPB divider determines the relationship between the processor clock (CCLK) and

the clock used by peripheral devices (PCLK). The VPB divider serves two purposes. The

first is to provide peripherals with the desired PCLK via VPB bus so that they can operate

at the speed chosen for the ARM processor. In order to achieve this, the VPB bus may be

slowed down to 12 to 14 of the processor clock rate. Because the VPB bus must work


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properly at power-up (and its timing cannot be altered if it does not work since the VPB

divider control registers reside on the VPB bus), the default condition at reset is for the

VPB bus to run at 14 of the processor clock rate. The second purpose of the VPB divider

is to allow power savings when an application does not require any peripherals to run at

the full processor rate. Because the VPB divider is connected to the PLL output, the PLL

remains active (if it was running) during Idle mode.

20. Emulation and debugging

The LPC2141/42/44/46/48 support emulation and debugging via a JTAG serial port. A

trace port allows tracing program execution. Debugging and trace functions are

multiplexed only with GPIOs on Port 1. This means that all communication, timer and

interface peripherals residing on Port 0 are available during the development and

debugging phase as they are when the application is run in the embedded system itself.

20.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The

debugging of the target system requires a host computer running the debugger software

and an EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the

remote debug protocol commands to the JTAG data needed to access the ARM core. The

ARM core has a Debug Communication Channel (DCC) function built-in. The DCC

allows a program running on the target to communicate with the host debugger or another

separate host without stopping the program flow or even entering the debug state. The

DCC is accessed as a co-processor 14 by the program running on the ARM7TDMI-S

core. The DCC allows the JTAG port to be used for sending and receiving data without

affecting the normal program flow. The DCC data and control registers are mapped in to

addresses in the EmbeddedICE logic.

20.2 Embedded trace

Since the LPC2141/42/44/46/48 have significant amounts of on-chip memory, it is

not possible to determine how the processor core is operating simply by observing the


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external pins. The Embedded Trace Macrocell (ETM) provides real-time trace capability

for deeply embedded processor cores. It outputs information about processor execution to

the trace port. The ETM is connected directly to the ARM core and not to the main

AMBA system bus. It compresses the trace information and exports it through a narrow

trace port. An external trace port analyzer must capture the trace information under

software debugger control. Instruction trace (or PC trace) shows the flow of execution of

the processor and provides a list of all the instructions that were executed. Instruction

trace is significantly compressed by only broadcasting branch addresses as well as a set

of status signals that indicate the pipeline status on a cycle by cycle basis. Trace

information generation can be controlled by selecting the trigger resource. Trigger

resources include address comparators, counters and sequencers. Since trace information

is compressed the software debugger requires a static image of the code being executed.

Self-modifying code can not be traced because of this restriction.

20.3 RealMonitor

RealMonitor is a configurable software module, developed by ARM Inc., which enables

real-time debug. It is a lightweight debug monitor that runs in the background while users

debug their foreground application. It communicates with the host using the DCC, which

is present in the EmbeddedICE logic. The LPC2141/42/44/46/48 contain a specific

configuration of RealMonitor software programmed into the on-chip flash memory.

3.4 Serial Communication:

The main requirements for serial communication are:

1. Microcontroller

2. PC

3. RS 232 cable

4. MAX 232 IC

5. HyperTerminal

When the pins P3.0 and P3.1 of microcontroller are set, UART which is inbuilt in the

microcontroller will be enabled to start the serial communication.


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Timers:

The 8051 has two timers: Timer 0 and Timer 1. They can be used either as timers to

generate a time delay or as counters to count events happening outside the

microcontroller. Both Timer 0 and Timer 1 are 16-bit wide. Since the 8051 has an 8-bit

architecture, each 16-bit timer is accessed as two separate registers of low byte and high

byte.

Lower byte register of Timer 0 is TL0 and higher byte is TH0. Similarly lower byte

register of Timer1 is TL1 and higher byte register is TH1.

TMOD (timer mode) register:

Both timers 0 and 1 use the same register TMOD to set the various operation modes.

TMOD is an 8-bit register in which the lower 4 bits are set aside for Timer 0 and the

upper 4 bits for Timer 1. In each case, the lower 2 bits are used to set the timer mode and

the upper 2 bits to specify the operation.

GATE

Every timer has a means of starting and stopping. Some timers do this by software, some

by hardware and some have both software and hardware controls. The timers in the 8051

have both. The start and stop of the timer are controlled by the way of software by the TR(timer start) bits TR0 and TR1. These instructions start and stop the timers as long as

GATE=0 in the TMOD register. The hardware way of starting and stopping the timer by

an external source is achieved by making GATE=1 in the TMOD register.

C/T


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Timer or counter selected. Cleared for timer operation and set for counter operation.

M1

Mode bit 1

M0

Mode bit 0

Mode Selection

M1 M0 Mode Operating Mode

0 0 0 13-bit timer mode

8-bit timer/counter THx with TLx as 5-bit prescaler

0 1 1 16-bit timer mode

16-bit timer/counters THx and TLx are cascaded

1 0 2 8-bit auto reload timer/counter

THx holds a value that is to be reloaded into TLx each time

it overflows

1 1 3 Split timer mode

The mode used here to generate a time delay is MODE 2. This mode 2 is an 8-bit timer

and therefore it allows only values of 00H to FFH to be loaded into the timers register

TH. After TH is loaded with the 8-bit value, the 8051 give a copy of it to TL. When the

timer starts, it starts to count up by incrementing the TL register. It counts up until it

reaches its limit of FFH. When it rolls over from FFH to 00H, it sets high the TF (timer

flag). If Timer 0 is used, TF0 goes high and if Timer 1 is used, TF1 goes high. When the

TL register rolls from FFH to 0 and TF is set to 1, TL is reloaded automatically with the

original value kept by the TH register.

Asynchronous and Synchronous Serial Communication

Computers transfer data in two ways: parallel and serial. In parallel data transfers, often 8

or more lines are used to transfer data to a device that is only a few feet away. Although a


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lot of data can be transferred in a short amount of time by using many wires in parallel,

the distance cannot be great. To transfer to a device located many meters away, the serial

method is best suitable.

In serial communication, the data is sent one bit at a time. The 8051 has serial

communication capability built into it, thereby making possible fast data transfer using

only a few wires.

The fact that serial communication uses a single data line instead of the 8-bit data line

instead of the 8-bit data line of parallel communication not only makes it cheaper but also

enables two computers located in two different cities to communicate over the telephone.

Serial data communication uses two methods, asynchronous and synchronous. The

synchronous method transfers a block of data at a time, while the asynchronous method

transfers a single byte at a time. With synchronous communications, the two devices

initially synchronize themselves to each other, and then continually send characters to

stay in sync. Even when data is not really being sent, a constant flow of bits allows each

device to know where the other is at any given time. That is, each character that is sent is

either actual data or an idle character. Synchronous communications allows faster data

transfer rates than asynchronous methods, because additional bits to mark the beginning

and end of each data byte are not required. The serial ports on IBM-style PCs are

asynchronous devices and therefore only support asynchronous serial communications.

Asynchronous means "no synchronization", and thus does not require sending and

receiving idle characters. However, the beginning and end of each byte of data must be

identified by start and stop bits. The start bit indicates when the data byte is about to

begin and the stop bit signals when it ends. The requirement to send these additional two

bits causes asynchronous communication to be slightly slower than synchronous however

it has the advantage that the processor does not have to deal with the additional idle

characters.


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There are special IC chips made by many manufacturers for serial data communications.

These chips are commonly referred to as UART(universal asynchronous receiver-

transmitter) and USART(universal synchronous-asynchronous receiver-transmitter). The

8051 has a built-in UART.

In the asynchronous method, the data such as ASCII characters are packed between a

start and a stop bit. The start bit is always one bit, but the stop bit can be one or two bits.

The start bit is always a 0 (low) and stop bit (s) is 1 (high). This is called framing.

The rate of data transfer in serial data communication is stated as bps (bits per second).

Another widely used terminology for bps is baud rate. The data transfer rate of a given

computer system depends on communication ports incorporated into that system. And in

asynchronous serial data communication, this baud rate is generally limited to

100,000bps. The baud rate is fixed to 9600bps in order to interface with the

microcontroller using a crystal of 11.0592 MHz.

RS232 CABLE:

To allow compatibility among data communication equipment, an interfacing standard

called RS232 is used. Since the standard was set long before the advent of the TTL logic

family, its input and output voltage levels are not TTL compatible. For this reason, to

connect any RS232 to a microcontroller system, voltage converters such as MAX232 are

used to convert the TTL logic levels to the RS232 voltage levels and vice versa.

MAX 232:

Max232 IC is a specialized circuit which makes standard voltages as required by RS232

standards. This IC provides best noise rejection and very reliable against discharges and

short circuits. MAX232 IC chips are commonly referred to as line drivers.

To ensure data transfer between PC and microcontroller, the baud rate and voltage levels

of Microcontroller and PC should be the same. The voltage levels of microcontroller are

logic1 and logic 0 i.e., logic 1 is +5V and logic 0 is 0V. But for PC, RS232 voltage levels


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are considered and they are: logic 1 is taken as -3V to -25V and logic 0 as +3V to +25V.

So, in order to equal these voltage levels, MAX232 IC is used. Thus this IC converts

RS232 voltage levels to microcontroller voltage levels and vice versa.

SCON (serial control) register:

The SCON register is an 8-bit register used to program the start bit, stop bit and data bits

of data framing.

SM0 SCON.7 Serial port mode specifier

SM1 SCON.6 Serial port mode specifier

SM2 SCON.5 Used for multiprocessor communication

REN SCON.4 Set/cleared by software to enable/disable reception

TB8 SCON.3 Not widely used

RB8 SCON.2 Not widely used

TI SCON.1 Transmit interrupt flag. Set by hardware at the

beginning of the stop bit in mode 1. Must be

cleared by software.

RI SCON.0 Receive interrupt flag. Set by hardware at the

beginning of the stop bit in mode 1. Must be


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cleared by software.

SM0 SM1

0 0 Serial Mode 0

0 1 Serial Mode 1, 8-bit data, 1 stop bit, 1 start bit

1 0 Serial Mode 2

1 1 Serial Mode 3

Of the four serial modes, only mode 1 is widely used. In the SCON register, when serial

mode 1 is chosen, the data framing is 8 bits, 1 stop bit and 1 start bit, which makes it

compatible with the COM port of IBM/ compatible PCs. And the most important is

serial mode 1 allows the baud rate to be variable and is set by Timer 1 of the 8051. In

serial mode 1, for each character a total of 10 bits are transferred, where the first bit is the

start bit, followed by 8 bits of data and finally 1 stop bit.


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8051 interface with any External Devices using Serial Communication:

3.5 GSM System Technology:

GSM stands for Global System for Mobile Communications. Just like

computers, mobile phones have evolved over time. There were first generation mobile

phones in the 70's, there are 2nd generation mobile phones in the 80's and 90's, and now

there are 3rd gen phones which are about to enter the Indian market. GSM is called a 2nd

generation, or 2G communications technology.

Now, GSM makes use of two principles. The first called Time division Multiplexing isvery simple.On the same lines, in GSM, the radio frequency say 890 Mhz is shared by

different users in time. This means if user A, B, C and D all talk at the same time. You

assign the 890 Mhz frequency to A for some time and allow him to talk, then you assign

890 band to B for sometime to speak, then to C , and finally to D, before coming back to

A. So the process continues in a round robin fashion, as long as A, B, C, and D want to


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talk. This way many users talk at same time on the same frequency. This has to be done,

because as we now frequency or Bandwidth is a scarce resource and is not available in

plentiful, so it must be shared.

Now the second principle that GSM uses is Frequency Division Multiplex. In Frequency

Division Multiplex, users A, B, C and D, all use different frequency say 890, 900, 910 ,

920 for their respective communications. A very good example of this is Radio

broadcasting.

Now, GSM uses a combination of TDMA and FDMA. This means that users A and B are

not only sharing the channel in time but also frequency. This means that user A is on the

channel 890Mhz for 2 seconds, then jumps to 900Mhz channel for the next to seconds,

then jumps to 910Mhz for the next 2 seconds and so on... Thus, each user is uses a

different frequency at different time slots. This is called Frequency Hopping.

GSM Architecture

Global system for mobile communication (GSM) is a globally accepted standard for

digital cellular communication. GSM is the name of a standardization group established

in 1982 to create a common European mobile telephone standard that would formulate

specifications for a pan-European mobile cellular radio system operating at 900 MHz. It

is estimated that many countries outside of Europe will join the GSM partnership.

Cellular is one of the fastest growing and most demanding telecommunications

applications. Throughout the evolution of cellular telecommunications, various systems

have been developed without the benefit of standardized specifications. This presented

many problems directly related to compatibility, especially with the development of

digital radio technology. The GSM standard is intended to address these problems.

From 1982 to 1985 discussions were held to decide between building an analog or digital

system. After multiple field tests, a digital system was adopted for GSM. The next task

was to decide between a narrow or broadband solution. In May 1987, the narrowband

time division multiple access (TDMA) solution was chosen.


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GSM provides recommendations, not requirements. The GSM specifications define the

functions and interface requirements in detail but do not address the hardware. The GSM

network is divided into three major systems: the switching system (SS), the base station

system (BSS), and the operation and support system (OSS).

GSM Architecture:


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The Switching System:

The switching system (SS) is responsible for performing call processing and subscriber-

related functions. The switching system includes the following functional units.

Home location register (HLR) The HLR is a database used for storage and

management of subscriptions. The HLR is considered the most important database, as it

stores permanent data about subscribers, including a subscriber's service profile,

location information, and activity status. When an individual buys a subscription from

one of the PCS operators, he or she is registered in the HLR of that operator.

Mobile services switching center (MSC) The MSC performs the telephony

switching functions of the system. It controls calls to and from other telephone and data

systems. It also performs such functions as toll ticketing, network interfacing, common

channel signaling, and others.

Visitor location register (VLR) The VLR is a database that contains temporary

information about subscribers that is needed by the MSC in order to service visiting

subscribers. The VLR is always integrated with the MSC. When a mobile station roams

into a new MSC area, the VLR connected to that MSC will request data about the

mobile station from the HLR. Later, if the mobile station makes a call, the VLR will

have the information needed for call setup without having to interrogate the HLR each

time.

Authentication center (AUC) A unit called the AUC provides authentication

and encryption parameters that verify the user's identity and ensure the confidentiality of

each call. The AUC protects network operators from different types of fraud found in

today's cellular world.

Equipment identity register (EIR) The EIR is a database that contains

information about the identity of mobile equipment that prevents calls from stolen,

unauthorized, or defective mobile stations. The AUC and EIR are implemented as stand-

alone nodes or as a combined AUC/EIR node.


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The Base Station System (BSS):

All radio-related functions are performed in the BSS, which consists of base station

controllers (BSCs) and the base transceiver stations (BTSs).

BSC The BSC provides all the control functions and physical links between the

MSC and BTS. It is a high-capacity switch that provides functions such as handover,

cell configuration data, and control of radio frequency (RF) power levels in base

transceiver stations. A number of BSCs are served by an MSC.

BTS The BTS handles the radio interface to the mobile station. The BTS is the

radio equipment (transceivers and antennas) needed to service each cell in the network.

A group of BTSs are controlled by a BSC.

The Operation and Support System:

The operations and maintenance center (OMC) is connected to all equipment in the

switching system and to the BSC. The implementation of OMC is called the operation

and support system (OSS). The OSS is the functional entity from which the network

operator monitors and controls the system. The purpose of OSS is to offer the customer

cost-effective support for centralized, regional, and local operational and maintenance

activities that are required for a GSM network. An important function of OSS is to

provide a network overview and support the maintenance activities of different operation

and maintenance organizations.

Additional Functional Elements:

Other functional elements shown in Figure 2 are as follows:

Message center (MXE) The MXE is a node that provides integrated voice, fax,

and data messaging. Specifically, the MXE handles short message service, cell

broadcast, voice mail, fax mail, e-mail, and notification.


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Mobile service node (MSN) The MSN is the node that handles the mobile

intelligent network (IN) services.

Gateway mobile services switching center (GMSC) A gateway is a node used

to interconnect two networks. The gateway is often implemented in an MSC. The MSC

is then referred to as the GMSC.

GSM interworking unit (GIWU) The GIWU consists of both hardware and

software that provides an interface to various networks for data communications.

Through the GIWU, users can alternate between speech and data during the same call.

The GIWU hardware equipment is physically located at the MSC/VLR.

GSM network areas:

In a GSM network, the following areas are defined:

Cell: Cell is the basic service area: one BTS covers one cell. Each cell is given a

Cell Global Identity (CGI), a number that uniquely identifies the cell.

Location Area: A group of cells form a Location Area. This is the area that is

paged when a subscriber gets an incoming call. Each Location Area is assigned a

Location Area Identity (LAI). Each Location Area is served by one or more

BSCs.

MSC/VLR Service Area: The area covered by one MSC is called the MSC/VLR

service area.

PLMN: The area covered by one network operator is called PLMN. A PLMN can

contain one or more MSCs.

GSM Device Control

GSM modem (900/1800 MHz) Semens GSM/GPRS Smart Modem is a multi-

functional, ready to use, rugged unit that can be embedded or plugged into any

application. The Smart Modem can be controlled and customized to various levels

by using the standard AT commands. The modem is fully type-approved, it can


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speed up the operational time with full range of Voice, Data, Fax and Short

Messages (Point to Point and Cell Broadcast), the modem also supports GPRS

(Class 2*) for spontaneous data transfer. Description of the interfaces The modem

comprises several interfaces: - LED Function including operating Status -

External antenna ( via SMA) - Serial and control link - Power Supply ( Via 2 pin

Phoenix tm contact ) - SIM card holder

LED Status Indicator The LED will indicate different status of the modem: - OFF

Modem Switched off - ON Modem is connecting to the network - Flashing

Slowly Modem is in idle mode Flashing rapidly Modem is in

transmission/communication (GSM only)

SIM300 AT Command Set

In application, controlling device controls the GSM engine by sending AT

Command via its serial interface. The controlling device at the other end of the

serial line is referred to as following term: 1) TE (Terminal Equipment); 2) DTE

(Data Terminal Equipment)

AT Command syntax The "AT" or "at" prefix must be set at the beginning of each

command line. To terminate a command line enter . Commands are usually

followed by a response that includes.

The AT command set implemented by SIM300 is a combination of GSM07.05,

GSM07.07 and ITU-T recommendation V.25ter and the AT commands developed

by SIMCOM. Note: Only enter AT command through serial port after SIM300 is

power on and Unsolicited Result Code RDY is received from serial port. And if

unsolicited result codeSCKS: 0 returned it indicates SIM card isnt present. If

autobauding is enabled, the Unsolicited Result Codes RDY and so on are not

indicated when you start up

Types of AT commands and responses

Test command AT+=? The mobile equipment returns the list of parameters

and value ranges set with the corresponding Write command or by internal


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processes. Read command AT+? This command returns the currently set

value of the parameter or parameters. Write command AT+= This

command sets the user-definable parameter values. Execution command AT+

The execution command reads non-variable parameters affected by internal

processes in the GSM engine.

Heart Beat Sensor interfacing

As shown the heart beat sensor is a combination of IR TX(Transmitter) and IR

RX(receiver). When ever the patient uses the sensor sense the flow of blood by injectingIR (transmitter)signal ,and the varition in the pulse is sensed by the IR receiver. As it is a

electronic device the output of the sensor is a voltage and it is weak signal. Then signal is

amplified by the Op Amp series LM358 a low power comparator in built. The amplified

signal is used by the controller to perform task.

Temperature Sensor (LM 35) interfacing

As shown the temperature sensor used is a LM35Precision Centigrade Temperature

Sensors. Its output voltage is linearly proportional to the celsius temperature, and its

range is 55 to +150C. It it draws only 60 A from its supply, it has very low self-

heating. The LM35 series is available packaged in hermetic TO-46 transistor packages,

while the LM35C, LM35CA, and LM35D are also available in the plastic TO-92

transistor package. The linear scale factor is +10.0mV/C with a suitable for remote


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applicaton at low cost due to wafer-level trimming. The device operatea at 4 to 30 volts

and a low impedance output, 0.1 W for 1 mA load.

3.6 Single-Chip Voice Recording & Playback Device 60-Second

Duration

Features

Single-chip, high-quality voice recording & playback solution

- No external ICs required

- Minimum external components

Non-volatile Flash memory technology

- No battery backup required

User-Selectable messaging options

- Random access of multiple fixed-duration messages

- Sequential access of multiple variable duration messages

User-friendly, easy-to-use operation

- Programming & development systems not required

- Level-activated recording & edge-activated playback switches

Low power consumption

- Operating current: 25 mA typical- Standby current: 1 uA typical

- Automatic power-down

Chip Enable pin for simple message expansion


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General Description

The APR9600 device offers true single-chip voice recording, non-volatile storage, and

playback capability for 40 to 60 seconds. The device supports both random and

sequential access of multiple messages. Sample rates are user-selectable, allowing

designers to customize their design for unique quality and storage time needs. Integrated

output amplifier, microphone amplifier, and AGC circuits greatly simplify system design.

The device is ideal for use in portable voice recorders, toys, and many other consumer

and industrial applications.

APLUS integrated achieves these high levels of storage capability by using its proprietary

analog/multilevel storage technology implemented in an advanced Flash non-volatile

memory process, where each memory cell can store 256 voltage levels. This technology

enables the APR9600 device to reproduce voice signals in their natural form. It

eliminates the need for encoding and compression, which often introduce distortion.

Functional Description

The APR9600 block diagram is included in order to give understanding of the APR9600

internal architecture. At the left hand side of the diagram are the analog inputs. A

differential microphone amplifier, including integrated AGC, is included on-chip for

applications requiring its use. The amplified microphone signal is fed into the device by


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connecting the Ana_Out pin to the Ana_In pin through an external DC blocking

capacitor. Recording can be fed directly into the Ana_In pin through a DC blocking

capacitor, however, the connection between Ana_In and Ana_Out is still required for

playback. The next block encountered by the input signal is the internal anti-aliasing

filter. The filter automatically adjusts its response according to the sampling frequency

selected so Shannons Sampling Theorem is satisfied.

After anti-aliasing filtering is accomplished the signal is ready to be clocked into the

memory array. This storage is accomplished through a combination of the Sample and

Hold circuit and the Analog Write/Read circuit. These circuits are clocked by either the

Internal Oscillator or an external clock source. When playbackis desired the previously

stored recording is retrieved from memory, low pass filtered, and amplified as shown on

the right hand side of the diagram. The signal can be heard by connecting a speaker to the

SP+ and SP- pins. Message management is controlled through the message control block

represented in the lower center of the block diagram.

Message Management

Message Management General Description


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Playback and record operations are managed by on chip circuitry. There are several

available messaging modes depending upon desired operation. These message modes

determine message management style, message length, and external parts count.

Therefore, the designer must select the appropriate operating mode before beginning the

design. Operating modes do not affect voice quality; for information on factors affecting

quality refer to the Sampling Rate & Voice Quality section.

The device supports three message management modes (defined by the MSEL1, MSEL2

and /M8_Option pins

Random access mode with 2, 4, or 8 fixed-duration messages

Tape mode, with multiple variable-duration messages, provides two options:

- Auto rewind

- Normal

Modes cannot be mixed. Switching of modes after the device has recorded an initial

message is not recommended. If modes are switched after an initial recording has been

made some unpredictable message fragments from the previous mode may remain

present, and be audible on playback, in the new mode. These fragments will disappear

after a record operation in the newly selected mode.

An important feature of the APR9600 message management capabilities is the ability to

audibly prompt the user to changes in the devices status through the use of beeps

superimposed on the devices output. This feature is enabled by asserting a logic high

level on the BE pin.


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Random Access Mode

Random access mode supports 2, 4, or 8 messages segments of fixed duration. As

suggested, recording or playback can be made randomly in any of the selected messages.

The length of each message segment is the total recording length available (as defined by

the selected sampling rate) divided by the total number of segments enabled. Random

access mode provides easy indexing to message segments.

Functional Description of Recording in Random Access Mode

On power up, the device is ready to record or play back, in any of the enabled message

segments. To record, /CE must be set low to enable the device and /RE must be set low to

enable recording. You initiate recording by applying a low level on the message trigger

pin that represents the message segment you intend to use. The message trigger pins are

labeled /M1_Message - /M8_Option on pins 1-9 (excluding pin 7) for message segments

1-8 respectively. When actual recording begins the device responds with a single beep (if

the BE pin is high to enable the beep tone) at the speaker outputs to indicate that it has

started recording.

Recording continues as long as the message pin stays low. The rising edge of the same

message trigger pin during record stops the recording operation (indicated with a single

beep). If the message trigger pin is held low beyond the end of the maximum allocated

duration, recording stops automatically (indicated with two beeps) regardless of the state

of the message trigger pin. The chip then enters low-power mode until the message

trigger pin returns high. After the message trigger pin returns to high, the chip enters

standby mode.

Any subsequent high to low transition on the same message trigger pin will initiate

recording from the beginning of the same message segment. The entire previous message

is then overwritten by the new message, regardless of the duration of the new message.

Transitions on any other message trigger pin or the /RE pin during the record operation

are ignored until after the device enters standby mode.


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Functional Description of Playback in Random Access Mode

On power up, the device is ready to record or playback, in any of the enabled message

segments. To playback, /CE must be set low to enable the device and /RE must be set

high to disable recording & enable playback. You initiate playback by applying a high to

low edge on the message trigger pin that representing the message segment you intend to

playback. Playback will continue until the end of the message is reached. If a high to low

edge occurs on the same message trigger pin during playback, playback of the current

message stops immediately.

If a different message trigger pin pulses during playback, playback of the current message

stops immediately (indicated by one beep) and playback of the new message segment

begins. A delay equal to 8,400 cycles of the sample clock will be encountered before the

device starts playing the new message. If a message trigger pin is held low, the selected

message is played back repeatedly as long as the trigger pin stays low. A period of

silence, of duration equal to 8,400 cycles of the sampling clock, will be inserted during

looping as an indicator to the user of the transition between the end and the beginning of

the message.

Tape Mode

Tape mode manages messages sequentially much like traditional cassette tape recorders.

Within tape mode two options exist, auto rewind and normal. Auto rewind mode

configures the device to automatically rewind to the beginning of the message

immediately following recording or playback of the message. In tape mode, using either

option, messages must be recorded or played back sequentially, much like a traditional

cassette tape recorder.

Function Description Recording in Tape Mode using the Normal option

On power up, the device is ready to record or play back, starting at the first address in the

memory array. To record, /CE must be set low to enable the device and /RE must be set

low to enable recording. A falling edge of the /M1_Message pin initiates voice recording


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(indicated by one beep). A subsequent rising edge of the /M1_Message pin during

recording stops the recording (also indicated by one beep). If the /M1_Message pin is

held low beyond the end of the available memory, recording will stop automatically

(indicated by two beeps). The device will then assert a logic low on the /M7_END pin for

a duration equal to 1600 cycles of the sample clock, regardless of the state of the

/M1_Message pin.

The device returns to standby mode when the /M1_Message pin goes high again. After

recording is finished the device will automatically rewind to the beginning of the most

recently recorded message and wait for the next user input. The auto rewind function is

convenient because it allows the user to immediately playback and review the message

without the need to rewind. However, caution must be practiced because a subsequent

record operation will overwrite the last recorded message unless the user remembers to

pulse the /M2_Next pin in order to increment the device past the current message. A

subsequent falling edge on the /M1_Message pin starts a new record operation,

overwriting the previously existing message. You can preserve the previously recorded

message by using the /M2_Next input to initiate recording in the next available message

segment. To perform this function, the /M2_Next pin must be pulled low for at least 400

cycles of the sample clock.

The auto rewind mode allows the

Documents

GSM Based Patient Mono to Ring