H8S/2633 Hardware Manual - Farnell element14The H8S/2633 Series is a series of high-performance microcontrollers with a 32-bit H8S/2600 CPU core, and a set of on-chip supporting functions

H8S/2633 SeriesH8S/2633HD6432633

H8S/2632HD6432632

H8S/2631HD6432631

H8S/2633 F-ZTAT™HD64F2633

Hardware Manual

ADE-602-165BRev. 3.03/20/01Hitachi, Ltd.

Cautions

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Preface

The H8S/2633 Series is a series of high-performance microcontrollers with a 32-bit H8S/2600CPU core, and a set of on-chip supporting functions required for system configuration.

The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bitgeneral registers with a 32-bit internal configuration, and a concise and optimized instruction set.The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs basedon the high-level language C can also be run efficiently.

The address space is divided into eight areas. The data bus width and access states can be selectedfor each of these areas, and various kinds of memory can be connected fast and easily.

Single-power-supply flash memory (F-ZTAT™*1), PROM (ZTAT™*2), and mask ROM versionsare available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications.

On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulsegenerator (PPG), 8-bit timer, 14-bit PWM timer (PWM), watchdog timer (WDT), serialcommunication interface (SCI, IrDA), A/D converter, D/A converter, and I/O ports. It is alsopossible to incorporate an on-chip PC bus interface (IIC) as an option.

In addition, DMA controller (DMAC) and data transfer controller (DTC) are provided, enablinghigh-speed data transfer without CPU intervention.

Use of the H8S/2633 Series enables easy implementation of compact, high-performance systemscapable of processing large volumes of data.

This manual describes the hardware of the H8S/2633 Series. Refer to the H8S/2600 Series andH8S/2000 Series Programming Manual for a detailed description of the instruction set.

Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Hitachi, Ltd.

Main Revisions and Additions in this Edition

Page ItemRevisions(See Manual for Details)

7 1.3.1 Pin Arrangement Note on FWE pin added

13 1.3.2 Pin Functions in Each Operating Mode Note 2 added

75 3.4 Pin Functions in Each Operating Mode Table 3-3 Pin Functions in EachMode

Port G added

570 15.2.2 Timer Control/Status Register (TCSR) WDT0 input clock selection

Overflow cycle value amended

571 WDT1 input clock selection

Overflow cycle value amended

703 18.2.4 I2C Bus Mode Register (ICMR) Bits 5 to 3—Transfer clock select

Note added

731 18.3.9 Sample Flowcharts Figure 18-14 Flowchart for MasterTransmit Mode (Example)

Completely revised

732 Figure 18-15 Flowchart for MasterReceive Mode (Example)

Completely revised

22.1 Overview Added

22.2 Register Descriptions Added

22.3 Operation Added

22.4 Flash Memory Overview Added

811 22.7.1 Program Mode Description added

Maximum number of writes

WDT overflow cycle

811 22.7.2 Program-Verify Mode Maximum number of writesamended

814 Figure 22-12 Program/Program-Verify Flowchart amended

815 22.7.3 Erase Mode WDT overflow cycle amended

839 22.13 Flash Memory Programming and ErasingPrecautions

“Do not perform overwriting. Erasethe memory before reprogramming”amended

Page ItemRevisions(See Manual for Details)

858, 859 24.1 Overview Table 24-1 LSI Internal States inEach Mode

Note added

884, 886 25.2 DC Characteristics Table 25-2 DC Characteristics (1)

Note 5 added

887, 889 Table 25-2 DC Characteristics (2)

Note 6 added

918 25.4 A/D Conversion Characteristics Position of Conversion Timeamended

920 25.6 Flash Memory Characteristics Table 25-14 Flash MemoryCharacteristics

Erase time typ. value amended

953, 955,960

A.2 Instruction Codes CLRMAC, LDMAC, MAC, STMACinstructions modified

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Contents

Section 1 Overview............................................................................................................ 11.1 Overview............................................................................................................................ 11.2 Internal Block Diagram......................................................................................................61.3 Pin Description................................................................................................................... 7

1.3.1 Pin Arrangement ................................................................................................... 71.3.2 Pin Functions in Each Operating Mode................................................................ 91.3.3 Pin Functions ........................................................................................................ 14

Section 2 CPU..................................................................................................................... 212.1 Overview............................................................................................................................ 21

2.1.1 Features................................................................................................................. 212.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU................................... 222.1.3 Differences from H8/300 CPU ............................................................................. 232.1.4 Differences from H8/300H CPU .......................................................................... 23

2.2 CPU Operating Modes ....................................................................................................... 242.3 Address Space.................................................................................................................... 292.4 Register Configuration....................................................................................................... 30

2.4.1 Overview............................................................................................................... 302.4.2 General Registers.................................................................................................. 312.4.3 Control Registers .................................................................................................. 322.4.4 Initial Register Values .......................................................................................... 34

2.5 Data Formats...................................................................................................................... 352.5.1 General Register Data Formats............................................................................. 352.5.2 Memory Data Formats.......................................................................................... 37

2.6 Instruction Set .................................................................................................................... 382.6.1 Overview............................................................................................................... 382.6.2 Instructions and Addressing Modes...................................................................... 392.6.3 Table of Instructions Classified by Function....................................................... 412.6.4 Basic Instruction Formats ..................................................................................... 48

2.7 Addressing Modes and Effective Address Calculation...................................................... 502.7.1 Addressing Mode.................................................................................................. 502.7.2 Effective Address Calculation .............................................................................. 53

2.8 Processing States................................................................................................................ 572.8.1 Overview............................................................................................................... 572.8.2 Reset State ............................................................................................................ 582.8.3 Exception-Handling State ..................................................................................... 592.8.4 Program Execution State ...................................................................................... 622.8.5 Bus-Released State................................................................................................ 622.8.6 Power-Down State ................................................................................................ 62

2.9 Basic Timing...................................................................................................................... 63

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2.9.1 Overview............................................................................................................... 632.9.2 On-Chip Memory (ROM, RAM).......................................................................... 632.9.3 On-Chip Supporting Module Access Timing ....................................................... 652.9.4 External Address Space Access Timing ............................................................... 66

2.10 Usage Note......................................................................................................................... 662.10.1 TAS Instruction .................................................................................................... 66

Section 3 MCU Operating Modes................................................................................. 673.1 Overview............................................................................................................................ 67

3.1.1 Operating Mode Selection .................................................................................... 673.1.2 Register Configuration.......................................................................................... 68

3.2 Register Descriptions ......................................................................................................... 683.2.1 Mode Control Register (MDCR).......................................................................... 683.2.2 System Control Register (SYSCR)....................................................................... 693.2.3 Pin Function Control Register (PFCR)................................................................. 71

3.3 Operating Mode Descriptions............................................................................................ 743.3.1 Mode 4 .................................................................................................................. 743.3.2 Mode 5 ................................................................................................................. 743.3.3 Mode 6 .................................................................................................................. 743.3.4 Mode 7 .................................................................................................................. 74

3.4 Pin Functions in Each Operating Mode ............................................................................. 753.5 Address Map in Each Operating Mode.............................................................................. 75

Section 4 Exception Handling........................................................................................ 794.1 Overview............................................................................................................................ 79

4.1.1 Exception Handling Types and Priority................................................................ 794.1.2 Exception Handling Operation ............................................................................. 804.1.3 Exception Vector Table ........................................................................................ 80

4.2 Reset................................................................................................................................... 824.2.1 Overview............................................................................................................... 824.2.2 Types of Reset ...................................................................................................... 824.2.3 Reset Sequence ..................................................................................................... 834.2.4 Interrupts after Reset............................................................................................. 854.2.5 State of On-Chip Supporting Modules after Reset Release.................................. 85

4.3 Traces ................................................................................................................................. 864.4 Interrupts ............................................................................................................................ 874.5 Trap Instruction.................................................................................................................. 884.6 Stack Status after Exception Handling .............................................................................. 894.7 Notes on Use of the Stack.................................................................................................. 90

Section 5 Interrupt Controller......................................................................................... 915.1 Overview............................................................................................................................ 91

5.1.1 Features................................................................................................................. 915.1.2 Block Diagram...................................................................................................... 92

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5.1.3 Pin Configuration.................................................................................................. 935.1.4 Register Configuration.......................................................................................... 93

5.2 Register Descriptions ......................................................................................................... 945.2.1 System Control Register (SYSCR)....................................................................... 945.2.2 Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO) ............................. 955.2.3 IRQ Enable Register (IER) ................................................................................... 965.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ..................................... 975.2.5 IRQ Status Register (ISR) .................................................................................... 98

5.3 Interrupt Sources................................................................................................................ 995.3.1 External Interrupts ................................................................................................ 995.3.2 Internal Interrupts.................................................................................................. 1005.3.3 Interrupt Exception Handling Vector Table ......................................................... 100

5.4 Interrupt Operation............................................................................................................. 1055.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 1055.4.2 Interrupt Control Mode 0...................................................................................... 1085.4.3 Interrupt Control Mode 2...................................................................................... 1105.4.4 Interrupt Exception Handling Sequence ............................................................... 1125.4.5 Interrupt Response Times ..................................................................................... 113

5.5 Usage Notes ....................................................................................................................... 1145.5.1 Contention between Interrupt Generation and Disabling ..................................... 1145.5.2 Instructions that Disable Interrupts....................................................................... 1155.5.3 Times when Interrupts are Disabled .................................................................... 1155.5.4 Interrupts during Execution of EEPMOV Instruction .......................................... 116

5.6 DTC and DMAC Activation by Interrupt.......................................................................... 1165.6.1 Overview............................................................................................................... 1165.6.2 Block Diagram...................................................................................................... 1165.6.3 Operation .............................................................................................................. 117

Section 6 PC Break Controller (PBC).......................................................................... 1196.1 Overview............................................................................................................................ 119

6.1.1 Features................................................................................................................. 1196.1.2 Block Diagram...................................................................................................... 1206.1.3 Register Configuration.......................................................................................... 121

6.2 Register Descriptions ......................................................................................................... 1216.2.1 Break Address Register A (BARA)...................................................................... 1216.2.2 Break Address Register B (BARB) ...................................................................... 1226.2.3 Break Control Register A (BCRA)....................................................................... 1226.2.4 Break Control Register B (BCRB) ....................................................................... 1246.2.5 Module Stop Control Register C (MSTPCRC) .................................................... 124

6.3 Operation............................................................................................................................ 1256.3.1 PC Break Interrupt Due to Instruction Fetch........................................................ 1256.3.2 PC Break Interrupt Due to Data Access ............................................................... 1256.3.3 Notes on PC Break Interrupt Handling................................................................. 126

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6.3.4 Operation in Transitions to Power-Down Modes ................................................. 1266.3.5 PC Break Operation in Continuous Data Transfer ............................................... 1276.3.6 When Instruction Execution is Delayed by One State.......................................... 1286.3.7 Additional Notes ................................................................................................... 129

Section 7 Bus Controller.................................................................................................. 1317.1 Overview............................................................................................................................ 131

7.1.1 Features................................................................................................................. 1317.1.2 Block Diagram...................................................................................................... 1337.1.3 Pin Configuration.................................................................................................. 1347.1.4 Register Configuration.......................................................................................... 135

7.2 Register Descriptions ......................................................................................................... 1367.2.1 Bus Width Control Register (ABWCR) ............................................................... 1367.2.2 Access State Control Register (ASTCR).............................................................. 1377.2.3 Wait Control Registers H and L (WCRH, WCRL) .............................................. 1387.2.4 Bus Control Register H (BCRH) .......................................................................... 1427.2.5 Bus Control Register L (BCRL) ........................................................................... 1447.2.6 Pin Function Control Register (PFCR)................................................................. 1467.2.7 Memory Control Register (MCR) ........................................................................ 1497.2.8 DRAM Control Register (DRAMCR).................................................................. 1517.2.9 Refresh Timer Counter (RTCNT) ........................................................................ 1537.2.10 Refresh Time Constant Register (RTCOR).......................................................... 153

7.3 Overview of Bus Control ................................................................................................... 1547.3.1 Area Partitioning................................................................................................... 1547.3.2 Bus Specifications ................................................................................................ 1557.3.3 Memory Interfaces................................................................................................ 1567.3.4 Interface Specifications for Each Area ................................................................. 1577.3.5 Chip Select Signals ............................................................................................... 158

7.4 Basic Bus Interface ............................................................................................................ 1597.4.1 Overview............................................................................................................... 1597.4.2 Data Size and Data Alignment.............................................................................. 1597.4.3 Valid Strobes ........................................................................................................ 1617.4.4 Basic Timing......................................................................................................... 1627.4.5 Wait Control.......................................................................................................... 170

7.5 DRAM Interface ................................................................................................................ 1727.5.1 Overview............................................................................................................... 1727.5.2 Setting up DRAM Space ...................................................................................... 1727.5.3 Address Multiplexing............................................................................................ 1737.5.4 Data Bus................................................................................................................ 1737.5.5 DRAM Interface Pins ........................................................................................... 1747.5.6 Basic Timing......................................................................................................... 1747.5.7 Precharge State Control ........................................................................................ 1767.5.8 Wait Control.......................................................................................................... 177

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7.5.9 Byte Access Control ............................................................................................. 1797.5.10 Burst Operation..................................................................................................... 1817.5.11 Refresh Control..................................................................................................... 185

7.6 DMAC Single Address Mode and DRAM Interface ......................................................... 1897.6.1 DDS=1 .................................................................................................................. 1897.6.2 DDS=0 .................................................................................................................. 190

7.7 Burst ROM Interface.......................................................................................................... 1917.7.1 Overview............................................................................................................... 1917.7.2 Basic Timing......................................................................................................... 1917.7.3 Wait Control.......................................................................................................... 193

7.8 Idle Cycle ........................................................................................................................... 1947.8.1 Operation .............................................................................................................. 1947.8.2 Pin States in Idle Cycle ......................................................................................... 198

7.9 Write Data Buffer Function ............................................................................................... 1997.10 Bus Release........................................................................................................................ 200

7.10.1 Overview............................................................................................................... 2007.10.2 Operation .............................................................................................................. 2007.10.3 Pin States in External Bus Released State ............................................................ 2017.10.4 Transition Timing ................................................................................................. 2027.10.5 Notes ..................................................................................................................... 203

7.11 Bus Arbitration................................................................................................................... 2047.11.1 Overview............................................................................................................... 2047.11.2 Operation .............................................................................................................. 2047.11.3 Bus Transfer Timing............................................................................................. 205

7.12 Resets and the Bus Controller............................................................................................ 205

Section 8 DMA Controller.............................................................................................. 2078.1 Overview............................................................................................................................ 207

8.1.1 Features................................................................................................................. 2078.1.2 Block Diagram...................................................................................................... 2088.1.3 Overview of Functions.......................................................................................... 2098.1.4 Pin Configuration.................................................................................................. 2118.1.5 Register Configuration.......................................................................................... 212

8.2 Register Descriptions (1) (Short Address Mode)............................................................... 2138.2.1 Memory Address Registers (MAR)...................................................................... 2148.2.2 I/O Address Register (IOAR) ............................................................................... 2158.2.3 Execute Transfer Count Register (ETCR)............................................................ 2158.2.4 DMA Control Register (DMACR) ....................................................................... 2168.2.5 DMA Band Control Register (DMABCR) ........................................................... 220

8.3 Register Descriptions (2) (Full Address Mode)................................................................. 2258.3.1 Memory Address Register (MAR)........................................................................ 2258.3.2 I/O Address Register (IOAR) ............................................................................... 2258.3.3 Execute Transfer Count Register (ETCR)............................................................ 226

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8.3.4 DMA Control Register (DMACR) ....................................................................... 2278.3.5 DMA Band Control Register (DMABCR) ........................................................... 231

8.4 Register Descriptions (3) ...................................................................................................2368.4.1 DMA Write Enable Register (DMAWER)........................................................... 2368.4.2 DMA Terminal Control Register (DMATCR) ..................................................... 2388.4.3 Module Stop Control Register (MSTPCR)........................................................... 239

8.5 Operation............................................................................................................................ 2408.5.1 Transfer Modes ..................................................................................................... 2408.5.2 Sequential Mode ................................................................................................... 2428.5.3 Idle Mode.............................................................................................................. 2458.5.4 Repeat Mode ......................................................................................................... 2488.5.5 Single Address Mode............................................................................................ 2528.5.6 Normal Mode........................................................................................................ 2558.5.7 Block Transfer Mode............................................................................................ 2588.5.8 DMAC Activation Sources................................................................................... 2648.5.9 Basic DMAC Bus Cycles...................................................................................... 2678.5.10 DMAC Bus Cycles (Dual Address Mode)............................................................ 2688.5.11 DMAC Bus Cycles (Single Address Mode) ......................................................... 2768.5.12 Write Data Buffer Function .................................................................................. 2828.5.13 DMAC Multi-Channel Operation......................................................................... 2838.5.14 Relation Between External Bus Requests, Refresh Cycles, the DTC,

and the DMAC...................................................................................................... 2858.5.15 NMI Interrupts and DMAC .................................................................................. 2868.5.16 Forced Termination of DMAC Operation ............................................................ 2878.5.17 Clearing Full Address Mode................................................................................. 288

8.6 Interrupts ............................................................................................................................ 2898.7 Usage Notes ....................................................................................................................... 290

Section 9 Data Transfer Controller (DTC)................................................................. 2959.1 Overview............................................................................................................................ 295

9.1.1 Features................................................................................................................. 2959.1.2 Block Diagram...................................................................................................... 2969.1.3 Register Configuration.......................................................................................... 297

9.2 Register Descriptions ......................................................................................................... 2989.2.1 DTC Mode Register A (MRA) ............................................................................. 2989.2.2 DTC Mode Register B (MRB).............................................................................. 3009.2.3 DTC Source Address Register (SAR) .................................................................. 3019.2.4 DTC Destination Address Register (DAR) .......................................................... 3019.2.5 DTC Transfer Count Register A (CRA) ............................................................... 3019.2.6 DTC Transfer Count Register B (CRB)................................................................ 3029.2.7 DTC Enable Registers (DTCER).......................................................................... 3029.2.8 DTC Vector Register (DTVECR)......................................................................... 3039.2.9 Module Stop Control Register A (MSTPCRA).................................................... 304

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9.3 Operation............................................................................................................................ 3059.3.1 Overview............................................................................................................... 3059.3.2 Activation Sources................................................................................................ 3079.3.3 DTC Vector Table ................................................................................................ 3089.3.4 Location of Register Information in Address Space............................................. 3129.3.5 Normal Mode........................................................................................................ 3139.3.6 Repeat Mode ......................................................................................................... 3149.3.7 Block Transfer Mode............................................................................................ 3159.3.8 Chain Transfer ...................................................................................................... 3179.3.9 Operation Timing.................................................................................................. 3189.3.10 Number of DTC Execution States ........................................................................ 3199.3.11 Procedures for Using DTC.................................................................................... 3219.3.12 Examples of Use of the DTC................................................................................ 322


Section 10 I/O Ports............................................................................................................. 32710.1 Overview............................................................................................................................ 32710.2 Port 1.................................................................................................................................. 332

10.2.1 Overview............................................................................................................... 33210.2.2 Register Configuration.......................................................................................... 33310.2.3 Pin Functions ........................................................................................................ 335

10.3 Port 3.................................................................................................................................. 34710.3.1 Overview............................................................................................................... 34710.3.2 Register Configuration.......................................................................................... 34710.3.3 Pin Functions ........................................................................................................ 350




10.7 Port A ................................................................................................................................. 36310.7.1 Overview............................................................................................................... 36310.7.2 Register Configuration.......................................................................................... 36410.7.3 Pin Functions ........................................................................................................ 36710.7.4 MOS Input Pull-Up Function................................................................................ 367

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10.8 Port B ................................................................................................................................. 36910.8.1 Overview............................................................................................................... 36910.8.2 Register Configuration.......................................................................................... 37010.8.3 Pin Functions ........................................................................................................ 37310.8.4 MOS Input Pull-Up Function................................................................................ 374

10.9 Port C ................................................................................................................................. 37510.9.1 Overview............................................................................................................... 37510.9.2 Register Configuration.......................................................................................... 37610.9.3 Pin Functions for Each Mode ............................................................................... 37910.9.4 MOS Input Pull-Up Function................................................................................ 381

10.10 Port D ................................................................................................................................. 38210.10.1 Overview............................................................................................................... 38210.10.2 Register Configuration.......................................................................................... 38310.10.3 Pin Functions ........................................................................................................ 38510.10.4 MOS Input Pull-Up Function................................................................................ 386

10.11 Port E.................................................................................................................................. 38710.11.1 Overview............................................................................................................... 38710.11.2 Register Configuration.......................................................................................... 38810.11.3 Pin Functions ........................................................................................................ 39010.11.4 MOS Input Pull-Up Function................................................................................ 391

10.12 Port F.................................................................................................................................. 39210.12.1 Overview............................................................................................................... 39210.12.2 Register Configuration.......................................................................................... 39310.12.3 Pin Functions ........................................................................................................ 395

10.13 Port G ................................................................................................................................. 39710.13.1 Overview............................................................................................................... 39710.13.2 Register Configuration.......................................................................................... 39810.13.3 Pin Functions ........................................................................................................ 400

Section 11 16-Bit Timer Pulse Unit (TPU).................................................................. 40311.1 Overview............................................................................................................................ 403

11.1.1 Features.................................................................................................................40311.1.2 Block Diagram...................................................................................................... 40711.1.3 Pin Configuration.................................................................................................. 40811.1.4 Register Configuration.......................................................................................... 410

11.2 Register Descriptions ......................................................................................................... 41211.2.1 Timer Control Register (TCR).............................................................................. 41211.2.2 Timer Mode Register (TMDR)............................................................................. 41711.2.3 Timer I/O Control Register (TIOR)...................................................................... 41911.2.4 Timer Interrupt Enable Register (TIER)............................................................... 43211.2.5 Timer Status Register (TSR) ................................................................................ 43511.2.6 Timer Counter (TCNT)......................................................................................... 43911.2.7 Timer General Register (TGR) ............................................................................. 440

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11.2.8 Timer Start Register (TSTR) ................................................................................ 44111.2.9 Timer Synchro Register (TSYR) .......................................................................... 44211.2.10 Module Stop Control Register A (MSTPCRA).................................................... 443

11.3 Interface to Bus Master...................................................................................................... 44411.3.1 16-Bit Registers .................................................................................................... 44411.3.2 8-Bit Registers ...................................................................................................... 444

11.4 Operation............................................................................................................................ 44611.4.1 Overview............................................................................................................... 44611.4.2 Basic Functions..................................................................................................... 44711.4.3 Synchronous Operation ........................................................................................ 45311.4.4 Buffer Operation ................................................................................................... 45511.4.5 Cascaded Operation .............................................................................................. 45911.4.6 PWM Modes ......................................................................................................... 46111.4.7 Phase Counting Mode........................................................................................... 466

11.5 Interrupts ............................................................................................................................ 47311.5.1 Interrupt Sources and Priorities ............................................................................ 47311.5.2 DTC/DMAC Activation........................................................................................ 47511.5.3 A/D Converter Activation..................................................................................... 475

11.6 Operation Timing............................................................................................................... 47611.6.1 Input/Output Timing ............................................................................................. 47611.6.2 Interrupt Signal Timing ........................................................................................ 480

11.7 Usage Notes ....................................................................................................................... 484

Section 12 Programmable Pulse Generator (PPG)..................................................... 49512.1 Overview............................................................................................................................ 495

12.1.1 Features.................................................................................................................49512.1.2 Block Diagram...................................................................................................... 49612.1.3 Pin Configuration.................................................................................................. 49712.1.4 Registers................................................................................................................498

12.2 Register Descriptions ......................................................................................................... 49912.2.1 Next Data Enable Registers H and L (NDERH, NDERL) ................................... 49912.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 50012.2.3 Next Data Registers H and L (NDRH, NDRL) .................................................... 50112.2.4 Notes on NDR Access .......................................................................................... 50112.2.5 PPG Output Control Register (PCR) .................................................................... 50312.2.6 PPG Output Mode Register (PMR) ...................................................................... 50512.2.7 Port 1 Data Direction Register (P1DDR).............................................................. 50812.2.8 Module Stop Control Register A (MSTPCRA).................................................... 508

12.3 Operation............................................................................................................................ 50912.3.1 Overview............................................................................................................... 50912.3.2 Output Timing ...................................................................................................... 51012.3.3 Normal Pulse Output ............................................................................................ 51112.3.4 Non-Overlapping Pulse Output ............................................................................ 513

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12.3.5 Inverted Pulse Output ........................................................................................... 51612.3.6 Pulse Output Triggered by Input Capture............................................................. 517

12.4 Usage Notes ...................................................................................................................... 518

Section 13 8-Bit Timers (TMR)....................................................................................... 52113.1 Overview............................................................................................................................ 521


13.2 Register Descriptions ......................................................................................................... 52513.2.1 Timer Counters 0 to 3 (TCNT0 to TCNT3).......................................................... 52513.2.2 Time Constant Registers A0 to A3 (TCORA0 to TCORA3) ............................... 52513.2.3 Time Constant Registers B0 to B3 (TCORB0 to TCORB3)................................ 52613.2.4 Timer Control Registers 0 to 3 (TCR0 to TCR3) ................................................. 52613.2.5 Timer Control/Status Registers 0 to 3 (TCSR0 to TCSR3).................................. 52913.2.6 Module Stop Control Register A (MSTPCRA).................................................... 532

13.3 Operation............................................................................................................................ 53313.3.1 TCNT Incrementation Timing.............................................................................. 53313.3.2 Compare Match Timing........................................................................................ 53413.3.3 Timing of External RESET on TCNT.................................................................. 53613.3.4 Timing of Overflow Flag (OVF) Setting.............................................................. 53613.3.5 Operation with Cascaded Connection .................................................................. 537

13.4 Interrupts ............................................................................................................................ 53813.4.1 Interrupt Sources and DTC Activation ................................................................. 53813.4.2 A/D Converter Activation..................................................................................... 538

13.5 Sample Application............................................................................................................ 53913.6 Usage Notes ....................................................................................................................... 540

13.6.1 Contention between TCNT Write and Clear ........................................................ 54013.6.2 Contention between TCNT Write and Increment................................................. 54113.6.3 Contention between TCOR Write and Compare Match....................................... 54213.6.4 Contention between Compare Matches A and B.................................................. 54313.6.5 Switching of Internal Clocks and TCNT Operation ............................................ 54313.6.6 Interrupts and Module Stop Mode........................................................................ 545

Section 14 14-Bit PWM D/A............................................................................................ 54714.1 Overview............................................................................................................................ 547


14.2 Register Descriptions ......................................................................................................... 55014.2.1 PWM D/A Counter (DACNT).............................................................................. 550

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14.2.2 PWM D/A Data Registers A and B (DADRA and DADRB) .............................. 55114.2.3 PWM D/A Control Register (DACR)................................................................... 55214.2.4 Module Stop Control Register B (MSTPCRB) .................................................... 554

14.3 Bus Master Interface.......................................................................................................... 55514.4 Operation............................................................................................................................ 558

Section 15 Watchdog Timer.............................................................................................. 56315.1 Overview............................................................................................................................ 563


15.2 Register Descriptions ......................................................................................................... 56715.2.1 Timer Counter (TCNT)......................................................................................... 56715.2.2 Timer Control/Status Register (TCSR) ................................................................ 56715.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 57215.2.4 Pin Function Control Register (PFCR)................................................................. 57315.2.5 Notes on Register Access ..................................................................................... 574

15.3 Operation............................................................................................................................ 57615.3.1 Watchdog Timer Operation .................................................................................. 57615.3.2 Interval Timer Operation ...................................................................................... 57815.3.3 Timing of Setting Overflow Flag (OVF).............................................................. 57815.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF).......................... 579


15.5.1 Contention between Timer Counter (TCNT) Write and Increment...................... 58015.5.2 Changing Value of CKS2 to CKS0 ...................................................................... 58115.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 58115.5.4 System Reset by WDTOVF Signal ...................................................................... 58115.5.5 Internal Reset in Watchdog Timer Mode ............................................................. 581

Section 16 Serial Communication Interface (SCI, IrDA)........................................ 58316.1 Overview............................................................................................................................ 583


16.2 Register Descriptions ......................................................................................................... 58916.2.1 Receive Shift Register (RSR) ............................................................................... 58916.2.2 Receive Data Register (RDR)............................................................................... 58916.2.3 Transmit Shift Register (TSR).............................................................................. 59016.2.4 Transmit Data Register (TDR).............................................................................. 59016.2.5 Serial Mode Register (SMR) ................................................................................ 591

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16.2.6 Serial Control Register (SCR) .............................................................................. 59416.2.7 Serial Status Register (SSR) ................................................................................. 59816.2.8 Bit Rate Register (BRR) ....................................................................................... 60216.2.9 Smart Card Mode Register (SCMR)..................................................................... 61116.2.10 IrDA Control Register (IrCR)............................................................................... 61216.2.11 Module Stop Control Registers B and C (MSTPCRB, MSTPCRC).................... 613

16.3 Operation............................................................................................................................ 61516.3.1 Overview............................................................................................................... 61516.3.2 Operation in Asynchronous Mode........................................................................ 61816.3.3 Multiprocessor Communication Function ............................................................ 62916.3.4 Operation in Clocked Synchronous Mode............................................................ 63716.3.5 IrDA Operation ..................................................................................................... 645

16.4 SCI Interrupts..................................................................................................................... 64816.5 Usage Notes ....................................................................................................................... 650

Section 17 Smart Card Interface...................................................................................... 65917.1 Overview............................................................................................................................ 659


17.2 Register Descriptions ......................................................................................................... 66417.2.1 Smart Card Mode Register (SCMR)..................................................................... 66417.2.2 Serial Status Register (SSR) ................................................................................. 66617.2.3 Serial Mode Register (SMR) ................................................................................ 66817.2.4 Serial Control Register (SCR) .............................................................................. 670

17.3 Operation............................................................................................................................ 67117.3.1 Overview............................................................................................................... 67117.3.2 Pin Connections.................................................................................................... 67117.3.3 Data Format .......................................................................................................... 67317.3.4 Register Settings ................................................................................................... 67517.3.5 Clock..................................................................................................................... 67717.3.6 Data Transfer Operations...................................................................................... 67917.3.7 Operation in GSM Mode ...................................................................................... 68617.3.8 Operation in Block Transfer Mode....................................................................... 687

17.4 Usage Notes ....................................................................................................................... 688

Section 18 I2C Bus Interface [Option]........................................................................... 69118.1 Overview............................................................................................................................ 691

18.1.1 Features.................................................................................................................69118.1.2 Block Diagram...................................................................................................... 69218.1.3 Input/Output Pins.................................................................................................. 69418.1.4 Register Configuration.......................................................................................... 695

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18.2 Register Descriptions ......................................................................................................... 69618.2.1 I2C Bus Data Register (ICDR).............................................................................. 69618.2.2 Slave Address Register (SAR).............................................................................. 69918.2.3 Second Slave Address Register (SARX).............................................................. 70018.2.4 I2C Bus Mode Register (ICMR)............................................................................ 70118.2.5 I2C Bus Control Register (ICCR).......................................................................... 70418.2.6 I2C Bus Status Register (ICSR) ............................................................................ 71118.2.7 Serial Control Register X (SCRX)........................................................................ 71618.2.8 DDC Switch Register (DDCSWR)....................................................................... 71718.2.9 Module Stop Control Register B (MSTPCRB) .................................................... 718

18.3 Operation............................................................................................................................ 71918.3.1 I2C Bus Data Format ............................................................................................. 71918.3.2 Master Transmit Operation................................................................................... 72018.3.3 Master Receive Operation .................................................................................... 72218.3.4 Slave Receive Operation....................................................................................... 72418.3.5 Slave Transmit Operation ..................................................................................... 72618.3.6 IRIC Setting Timing and SCL Control ................................................................. 72818.3.7 Operation Using the DTC ..................................................................................... 72918.3.8 Noise Canceler...................................................................................................... 73018.3.9 Sample Flowcharts................................................................................................ 73018.3.10 Initialization of Internal State ............................................................................... 734

18.4 Usage Notes ....................................................................................................................... 736

Section 19 A/D Converter.................................................................................................. 74519.1 Overview............................................................................................................................ 745


19.2 Register Descriptions ......................................................................................................... 74919.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 74919.2.2 A/D Control/Status Register (ADCSR)................................................................ 75019.2.3 A/D Control Register (ADCR) ............................................................................. 75319.2.4 Module Stop Control Register A (MSTPCRA).................................................... 754

19.3 Interface to Bus Master...................................................................................................... 75519.4 Operation............................................................................................................................ 756

19.4.1 Single Mode (SCAN = 0) ..................................................................................... 75619.4.2 Scan Mode (SCAN = 1)........................................................................................ 75819.4.3 Input Sampling and A/D Conversion Time.......................................................... 76019.4.4 External Trigger Input Timing.............................................................................. 761


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Section 20 D/A Converter.................................................................................................. 76920.1 Overview............................................................................................................................ 769

20.1.1 Features.................................................................................................................76920.1.2 Block Diagram...................................................................................................... 76920.1.3 Input and Output Pins ........................................................................................... 77120.1.4 Register Configuration.......................................................................................... 771

20.2 Register Descriptions ......................................................................................................... 77220.2.1 D/A Data Registers 0 to 3 (DADR0 to DADR3).................................................. 77220.2.2 D/A Control Register 01 and 23 (DACR01 and DACR23) ................................. 77220.2.3 Module Stop Control Register A and C (MSTPCRA and MSTPCRC) ............... 774

20.3 Operation............................................................................................................................ 776

Section 21 RAM.................................................................................................................... 77721.1 Overview............................................................................................................................ 777

21.1.1 Block Diagram...................................................................................................... 77721.1.2 Register Configuration.......................................................................................... 778

21.2 Register Descriptions ......................................................................................................... 77821.2.1 System Control Register (SYSCR)....................................................................... 778

21.3 Operation............................................................................................................................ 77921.4 Usage Notes ....................................................................................................................... 779

Section 22 ROM.................................................................................................................... 78122.1 Overview............................................................................................................................ 781


22.2 Register Descriptions ......................................................................................................... 78222.2.1 Mode Control Register (MDCR).......................................................................... 782

22.3 Operation............................................................................................................................ 78222.4 Flash Memory Overview ................................................................................................... 785

22.4.1 Features................................................................................................................. 78522.4.2 Overview............................................................................................................... 78622.4.3 Flash Memory Operating Modes.......................................................................... 78722.4.4 On-Board Programming Modes............................................................................ 78822.4.5 Flash Memory Emulation in RAM ....................................................................... 79022.4.6 Differences between Boot Mode and User Program Mode.................................. 79122.4.7 Block Configuration.............................................................................................. 79222.4.8 Pin Configuration.................................................................................................. 79222.4.9 Register Configuration.......................................................................................... 793

22.5 Register Descriptions ......................................................................................................... 79322.5.1 Flash Memory Control Register 1 (FLMCR1) ..................................................... 79322.5.2 Flash Memory Control Register 2 (FLMCR2) ..................................................... 79622.5.3 Erase Block Register 1 (EBR1) ............................................................................ 797

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22.5.4 Erase Block Register 2 (EBR2) ............................................................................ 79822.5.5 RAM Emulation Register (RAMER).................................................................... 79922.5.6 Flash Memory Power Control Register (FLPWCR) ............................................ 80122.5.7 Serial Control Register X (SCRX)........................................................................ 801

22.6 On-Board Programming Modes......................................................................................... 80222.6.1 Boot Mode ............................................................................................................ 80322.6.2 User Program Mode.............................................................................................. 807

22.7 Programming/Erasing Flash Memory................................................................................ 80922.7.1 Program Mode ...................................................................................................... 81022.7.2 Program-Verify Mode .......................................................................................... 81122.7.3 Erase Mode ........................................................................................................... 81522.7.4 Erase-Verify Mode................................................................................................ 815

22.8 Protection ........................................................................................................................... 81722.8.1 Hardware Protection ............................................................................................. 81722.8.2 Software Protection .............................................................................................. 81822.8.3 Error Protection .................................................................................................... 819

22.9 Flash Memory Emulation in RAM .................................................................................... 82122.10 Interrupt Handling when Programming/Erasing Flash Memory ....................................... 82322.11 Flash Memory Programmer Mode..................................................................................... 823

22.11.1 Socket Adapter Pin Correspondence Diagram ..................................................... 82422.11.2 Programmer Mode Operation ............................................................................... 82622.11.3 Memory Read Mode ............................................................................................. 82722.11.4 Auto-Program Mode ............................................................................................. 83022.11.5 Auto-Erase Mode.................................................................................................. 83222.11.6 Status Read Mode ................................................................................................. 83422.11.7 Status Polling........................................................................................................ 83522.11.8 Programmer Mode Transition Time ..................................................................... 83522.11.9 Notes on Memory Programming .......................................................................... 836

22.12 Flash Memory and Power-Down States ............................................................................ 83722.12.1 Note on Power-Down States................................................................................. 837

22.13 Flash Memory Programming and Erasing Precautions...................................................... 83822.14 Note on Switching from F-ZTAT Version to Mask ROM Version................................... 843

Section 23 Clock Pulse Generator................................................................................... 84523.1 Overview............................................................................................................................ 845


23.2 Register Descriptions ......................................................................................................... 84623.2.1 System Clock Control Register (SCKCR)............................................................ 84623.2.2 Low-Power Control Register (LPWRCR)............................................................ 847

23.3 Oscillator............................................................................................................................ 84823.3.1 Connecting a Crystal Resonator............................................................................ 84823.3.2 External Clock Input ............................................................................................. 851

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23.4 PLL Circuit ........................................................................................................................ 85323.5 Medium-Speed Clock Divider ........................................................................................... 85323.6 Bus Master Clock Selection Circuit................................................................................... 85323.7 Subclock Oscillator............................................................................................................ 85423.8 Subclock Waveform Shaping Circuit ................................................................................ 85523.9 Note on Crystal Resonator .................................................................................................855

Section 24 Power-Down Modes...................................................................................... 85724.1 Overview............................................................................................................................ 857

24.1.1 Register Configuration.......................................................................................... 86124.2 Register Descriptions ......................................................................................................... 862

24.2.1 Standby Control Register (SBYCR) ..................................................................... 86224.2.2 System Clock Control Register (SCKCR)............................................................ 86424.2.3 Low-Power Control Register (LPWRCR)............................................................ 86524.2.4 Timer Control/Status Register (TCSR) ................................................................ 86824.2.5 Module Stop Control Register (MSTPCR)........................................................... 869

24.3 Medium-Speed Mode.........................................................................................................87024.4 Sleep Mode ........................................................................................................................ 871

24.4.1 Sleep Mode ........................................................................................................... 87124.4.2 Exiting Sleep Mode .............................................................................................. 871

24.5 Module Stop Mode ............................................................................................................ 87224.5.1 Module Stop Mode ............................................................................................... 87224.5.2 Usage Notes .......................................................................................................... 874

24.6 Software Standby Mode.....................................................................................................87424.6.1 Software Standby Mode........................................................................................ 87424.6.2 Exiting Software Standby Mode........................................................................... 87424.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode... 87524.6.4 Software Standby Mode Application Example .................................................... 87624.6.5 Usage Notes .......................................................................................................... 877

24.7 Hardware Standby Mode ................................................................................................... 87724.7.1 Hardware Standby Mode ...................................................................................... 87724.7.2 Hardware Standby Mode Timing.......................................................................... 878

24.8 Watch Mode....................................................................................................................... 87824.8.1 Watch Mode.......................................................................................................... 87824.8.2 Exiting Watch Mode............................................................................................. 87924.8.3 Notes ..................................................................................................................... 879

24.9 Sub-Sleep Mode................................................................................................................. 88024.9.1 Sub-Sleep Mode.................................................................................................... 88024.9.2 Exiting Sub-Sleep Mode....................................................................................... 880

24.10 Sub-Active Mode ............................................................................................................... 88124.10.1 Sub-Active Mode.................................................................................................. 88124.10.2 Exiting Sub-Active Mode ..................................................................................... 881

24.11 Direct Transitions............................................................................................................... 882

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24.11.1 Overview of Direct Transitions ............................................................................ 88224.12 ø Clock Output Disabling Function ................................................................................... 882

Section 25 Electrical Characteristics.............................................................................. 88325.1 Absolute Maximum Ratings .............................................................................................. 88325.2 DC Characteristics ............................................................................................................. 88425.3 AC Characteristics ............................................................................................................. 892

25.3.1 Clock Timing.................

Documents

H8S/2633 Hardware Manual - Farnell element14The H8S/2633 Series is a series of high-performance microcontrollers with a 32-bit H8S/2600 CPU core, and a set of on-chip supporting functions