A CMOS Frequency Synthesizer with anInjection-Locked Frequency Divider for a 5 GHz

Wireless LAN Receiver

Hamid Rategh

Center for Integrated SystemsStanford University

OUTLINE

� Motivation

� Introduction to wireless LAN

� Synthesizer architecture

� Synthesizer building blocks

� Summary and conclusion

MOTIVATION

� Large demand for wideband wireless LAN systems

– 20+ Mb/s data rate

– Low cost

– Low power

� New released frequency band

– Unlicensed national information infrastructure (U–NII) band

GOAL

� Design a 5 GHz frequency synthesizer for a U–NII bandwireless–LAN receiver (HIPERLAN compatible).

� Implement in CMOS.

� Minimize power consumption.

FREQUENCY OF OPERATION

23.5 MHz

5.15 5.30 5.35 5.8255.725

HIPERLAN U-NII

5.15 GHz

GHz

5.35

HIPERLAN/1 STANDARD

Class A Class B Class C

Transmitter power +10 dBm +20 dBm +30 dBm

Receiver sensitivity -50 dBm -60 dBm -70 dBm

Maximum signal level -25 dBm

Modulation GMSK (BT=0.3)

Data rate 20 Mb/s

Topology multihop ad hoc

Carrier switching time � 1 ms

Channel bandwidth 23.5 MHz

HIPERLAN MULTIHOP ad hoc topology

Forwarder

RECEIVER ARCHITECTURE

rfLO1=f x

Σ

Σ

16

17 16

1LO2=LO1x

rff =5.15-5.35 GHz

Q

I+

-

+

+

LNA

SynthesizerFrequency

� Weaver architecture.

� Requires quadrature LO’s to reject the image signal.

TYPICAL PLL–BASED FREQUENCY SYNTHESIZER

VCO

M

PFD

Loop Filter

Channel Selection

foutref f =Mfref

� Reference is a crystal oscillator.

� fout = M� fref

� Multiple LO frequencies are generated by changing M.

� Frequency dividers are power hungry.

– Their power consumption increases with frequency.

PROPOSED PLL ARCHITECTURE

f

Charge PumpPFD

M

ModulusChannelSelect Control

Loop Filter VCO

f

PrescalerProgram &

CountersPulse Swallow

outref

Tracking ILFD

12

N/N+1

� fref=11 MHz

� fo=4.840–4.994 GHz

� 8 channels

� M=220–227

� N=8

INJECTION LOCKING

� By impressing an oscillator with an external (incident) signal,frequency locking can be achieved.

– First-harmonic injection locked oscillators ( fifo= 1).

– Subharmonic injection locked oscillators ( fifo= 1N

).

– Superharmonic injection locked oscillators ( fifo= N ).

Injection–locked frequency dividers (ILFDs).

ILFD SIMPLIFIED PICTURE

f(e) = e2

iω iω2

iωi2

ωi2

ω

i2

ωi Η(ω)e uω

2,

,

3@

� Intermodulation of the input and output is the base of frequencydivision in an ILFD.

� An ILFD is an oscillator with perturbed oscillation.

– Oscillation conditions should be satisfied in the presence ofthe incident signal.

SPECIAL CASE (DIVIDE–BY–TWO)

f(e) = a0 + a1e+ a2e2 + a3e3

� Condition 1:

j�!!rj < jH0a2Vi

2Q

j ;

H0Q

=LQ!r

Q

= L!r

� Condition 2:

H0(a1 +3

2a3V2

i + a2Vi cos(�)) < 1

TRACKING ILFD

Tracking ILFD

12

Vc

VVi o

VCO

� Locking range extension

DIFFERENTIAL TRACKING ILFD

Vx

Vin

Vout

Vc

M1M2

M3M4 R1R2

Ibias

Vdd

- - ++

� 0.24 �m CMOS

� Vdd=1.5 V

� Ibias=300 �A

� fo=2.45 GHz

� fi=4.9 GHz

INDUCTOR DESIGN (ILFD)

� Maximum locking range) maximize L

� Minimum power consumption) maximize LQ

INDUCTOR DESIGN

Cp1 Cp2

RsiCsiRsi Csi

Cs

L Rs

Sub

w

s

OD

� Design parameters:

– w: metal width

– s: metal spacing

– OD: outer dimension

– n: number of turns

INDUCTOR DESIGN (ILFD)

� In planar spiral inductors maximizing L does not maximize LQ

+

maximize L for a given LQ

ILFD FREE–RUNNING OSCILLATION

0.5 1 1.5 2 2.52380

2400

2420

2440

2460

2480

2500

Control voltage (V)

Out

put f

requ

ency

(M

Hz)

� 0.24 �m CMOS

� Vdd=1.5 V

� Ibias=300 �A

� �f=110 MHz (5%)

� �Vc=2 V

ILFD LOCKING RANGE/POWER CONSUMPTION

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60

500

1000

Inpu

t ref

erre

d lo

ckin

g ra

nge

(MH

z)

Vc=1.5VVc=2.0V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

0.5

1

Pow

er (

mW

)

Incident amplitude (V)

� 0.24 �m CMOS

� Vdd=1.5 V

� fo=2.45 GHz

� fi=4.9 GHz

� �f=1 GHz@ 1 V (� 20%)

� Power=0.75 mW@ 1 V

PHASE NOISE MEASUREMENT TEST SETUP

HP8563E50

On chip

Vi

50

50

Vdd

Ext. Amp.DILFD

ILFD PHASE NOISE

100

101

102

103

104

−130

−120

−110

−100

−90

−80

−70

Offset frequency (kHz)

Pha

se n

oise

(dB

c/H

z)

HP83732B Free running Middle freqeuncyEdge frequency � 0.24 �m CMOS

� Vdd=1.5 V

� fo=2.45 GHz

� fi=4.9 GHz

ILFD SUMMARY

Frequency of operation 5 GHz

Output frequency tuning 110 MHz� 5%

Input–referred locking range 600 MHz� 12% @ 0.55 mW

1000 MHz� 20% @ 0.8 mW

Technology 0.24 �m CMOS

Die area 0.225 mm2

Flipflop based divider (for comparison)

0.24 �m CMOS (simulation) 5 mW @ 5 GHz

0.1 �m CMOS [1] 2.6 mW @ 5 GHz

[1] Razavi et al., JSSC Vol. 30, No.2, pp 101–109, Feb. 1995

PROGRAMMABLE FREQUENCY DIVIDER

N/N+1fin

S

M

P

Program Counter

Reset

Swallow Counter

fout

ModulusControl

Channel Selection

Prescaler

� One output cycle =

(N+ 1)S+ (P� S)N = PN+ S input cycles.

� M = PN+ S

� N = 8;P = 26; S = 12:::19;M = 220:::227

PRESCALER (� 8/9)

FF2 FF1MC

Clk

O1

Q

Q 2ClkMC

QQClk 2Clk2/3In

MC

Out

ClkQ

D Q

ClkQ

D Q

NOR/FLIPFLOP IMPLEMENTATION

B

AB B

A

Ibias

Clk

Vdd

RR

Vdd

RR

Q Q

A

Clk

PROGRAM AND PULSE SWALLOW COUNTERS

S=1,2,...,24Swallow Counter (S=1,2,...,24)

MC

FF1

Reset

Reset

Program Counter (P=26)

FF2

OutT-FF

ClkQ

R QT-FF

R

ClkQR

D Q

Clk

D

Q

Q

Q

Ch3Ch2Ch1 Ch4 Ch5

QClk

T-FFR Q

QClk

T-FFR Q

QClk

T-FFR Q

QClk

clk

clk clk

PHASE/FREQUENCY DETECTOR

iU

FF1

FF2

Reset

Reset

V

R

Q

Q

D

Clk

QD

Q

D

Clk i

Output stage

U

U

D

D

CHARGE PUMP AND LOOP–FILTER

Wp

DownI

M6

M7

Vr

Wp

Wn 2Wn Wn

Loop filter

Charge pumpReplica bias Feedback network

WpI

M8

Up

M5

pO

C1C2

R3

C3

R1

Vddvco

Vc1On

UUM4M3

DDM1 M2

CHARGE PUMP CURRENT MATCHING

0 0.5 1 1.5 2−10

−8

−6

−4

−2

0

2

4

6

8

10

Vo (V)

(Id−

Iu)/

Id*1

00

� �II

<0.05%0.25 V� VO � 1.75 V

� �II

<2%0.1 V� VO � 1.8 V

LOOP FILTER

PLL order

2nd order 3rd order 4th order

# Poles 2 3 4

Independent designvariables:

1) Phase marginp p p

2) Loop bandwidthp p p

3) Spur attenuation

p

LOOP FILTER DESIGN (4th ORDER PLL)

104

105

106

107

108

109

−150

−100

−50

0

50

100

Mag

nitu

de (

dB)

open loop transfer function

104

105

106

107

108

109

−300

−250

−200

−150

−100

Frequency (Hz)

Pha

se (

degr

ee)

OutIn

C1

R1

C2 C3

R3

� R3C3 � R1(C2 + C3)

� b = C1

C2+C3

� PM � tan�1(p

1 + b)� tan�1( 1p1+b)

� Wc �p

1+b

R1C1

� ts = f2(PM)

Wc

� R3C3 sets the spur attenuation.

LOOP PARAMETERSParameter Value

Kvco 360 MHz/V (Average)

500 MHz/V (Max)

Ip 3 �A

C1 42 pF

C2 3.5 pF

C3 2.2 pF

R1 170 k

R3 64.5 k

PM 49Æ

Wc 60 kHz

jH(j2�f)j@ fref -45 dB

ts < 35 �s

OutIn

C1

R1

C2 C3

R3

LOOP–FILTER NOISE

100

102

104

106

108

−250

−200

−150

−100

−50

Offset frequency (Hz)

Pha

se n

oise

(dB

c/H

z)

noise of R1noise of R3total noise

� L=-149 dBc/Hz@ 22 MHz

VOLTAGE–CONTROLLED OSCILLATOR

I2m

I1mI1p

I2p

Vo1

M7 M8M4

M6M2M1

M3

M5

Vo2

Vo1

I1=I1p-I1mVo2

-Vo2 I2=I2p-I2m

biasI

biasI

+ +- -

Vdd

Vc+ +- -

Vdd

Vc� 0.24 �m CMOS

� Vdd=1.5 V

� Ibias=4.0 mA

� fo=4.9 GHz

INDUCTOR DESIGN (VCO)

� Maximum Q) minimum inductor noise

� If inductors are not the main source of noise, maximum LQ)

– Maximum oscillation amplitude for a given bias current.

– Minimum phase noise due to active devices.

VCO FREQUENCY TUNING

0 0.5 1 1.5 24.7

4.8

4.9

5

5.1

5.2

5.3

Control voltage (V)

Fre

quen

cy (

GH

z)

� 0.24 �m CMOS

� Vdd=1.5 V

� Ibias=4.0 mA

� �f =550 MHz (11%)

� ( dfdv)max=500 MHz/V

PLL PHASE NOISE

104

105

106

107

108

−150

−140

−130

−120

−110

−100

−90

−80

−70

−60

Offset frequency (Hz)

Pha

se n

oise

(dB

c/H

z)

� L=-134 dBc/Hz@ 22 MHz

SPECTRUM OF THE SYNTHESIZED OUTPUT

4.9 4.92 4.94 4.96 4.98 5−80

−70

−60

−50

−40

−30

−20

−10

0

Frequency (GHz)

Pow

er (

dBm

)

SYNTHESIZER CHIP MICROGRAPH

VCO

ILFDTracking

Prescaler

Counters

BiasLoop Filter

PFD

ChargePump

� 0.24 �m CMOS

� area=1.45 mm2

(1� 1.45 mm2)

SUMMARYSynthesized frequencies 4:840–4:994 GHz

Reference frequency 11 MHz

Spurs < �70 dBc

Phase noise �134 dBc=Hz @ 22MHz

Loop bandwidth 60 kHz

Settling time < 35 �s

Power dissipation

VCO 12 mW

ILFD 1 mW

Prescaler 6:6 mW

Digital+Bias Circuits 2 mWTotal 21:6 mWSupply voltage 1:5 V (analog)

2:0 V (digital)

Implementation

Die area 1:45 mm2

Technology 0:24 �m CMOS

COMPARISON

Ref. f (GHz) P (mW) L (�m) FM PN (dBc/Hz) PNn Spur

[1] 1.6 90 0.6 10.7 -114 @ 600kHz -135.4 -80 dBc

[2] 1.8 51 0.4 14.1 -134 @ 3MHz -142.4

[3] 1.6 36 0.5 22.2 -140 @ 35MHz -126 -45 dBc

[4] 5.0 47 0.4 42.5 -100 @ 5.2MHz -112.5 -50 dBc

This work 5.0 21.6 0.24 55.5 -134 @ 22MHz -134 -70 dBc

� FM = f�LP

� PNn = PN+ 20 log�

�ff

5GHz

22MHz�

[1] J. Parker et al. “A 1.6GHz CMOS PLL with On–chip loop filter” JSSC Vol 33 Mar 98.

[2] J. Craninckx et al. “A Fully Integrated CMOS DCS–1800 Synthesizer” JSSC Vol 33 Dec 98.

[3] A. Shahani et al. “Low Power Dividerless Frequency Synthesis ...” JSSC Vol 33, Dec 98.

[4] C. Lam et al. “A 2.6GHz/5.2GHz Frequency Synthesizer in a 0.4�m CMOS Technology”, VLSI 99.

CONCLUSION

� A 5GHz frequency synthesizer is fully integrated in 0.24�m CMOS.

� Power consumption is reduced significantly by:

– employing a tracking ILFD.

– optimizing spiral inductors for the VCO and ILFD.

– current sharing in the prescaler.

� Loop–filter noise is kept small by using reasonably small resistors.

� A spurious free output is achieved by:

– using a semi–differential charge pump with well matched currents.

– minimizing the skew of the PFD complementary outputs.

– designing a fourth–order loop.

CONTRIBUTIONS

� Developing a general theory for injection–locked oscillators.

� Developing design techniques for very low power ILFD’s with awide locking range.

� Introducing the tracking ILFD.

� Designing a very low power and fully integrated CMOSfrequency synthesizer at 5 GHz.

� Developing a very simple loop filter design recipe for third andfourth order PLL’s.

� Demonstrating the operation of analog CMOS circuits with asub 2 V supply.

ACKNOWLEDGMENTS

National Semiconductor

Stanford Graduate Fellowship Program

Tektronix

Conexant