Hardware Reference Manual PEX8603 TQFP-AIC Rapid ... · s lo t_ p e r s t# dbg mo e s mbus _ e n# p o r tc f g 0 up c f g _tim er n# i2 c _ addr 2 i2 c _ addr 1 i2 c _ addr 0 g p

PEX8603 TQFP-AIC RDK

© PLX Technology, www.plxtech.com Page 1 of 23 05Mar13, Version 1.0

PLX Technology

Hardware Reference Manual

PEX8603 TQFP-AIC Rapid Development Kit



Preface

Notice This document contains PLX Confidential and Proprietary information. The contents of this document may not be copied

nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.

PLX provides the information and data included in this document for your benefit, but it is not possible to entirely verify

and test all the information, in all circumstances, particularly information relating to non-PLX manufactured products.

PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this information. The

information in this document is subject to change without notice. Although every effort has been made to ensure the

accuracy of this manual, PLX shall not be liable for any errors, incidental, or consequential damages in connection with

the furnishing, performance, or use of this manual or examples herein. PLX assumes no responsibility for damage or

loss resulting from the use of this manual, for loss or claims by third parties, which may arise through the use of the

RDK, or for any damage or loss caused by deletion of data as a result of malfunction or repair.

About This Manual This document describes the PLX PEX8603 TQFP-AIC RDK, a Rapid Development Kit, from a hardware perspective. It

contains a description of all major functional circuit blocks on the board and also is a reference for the creation of

software for this product. This manual also includes complete schematics and bill of materials.

Revision History

Date Version Comments

March

2013 1.0 Initial Release



Table of Contents

1 GENERAL INFORMATION .......................................................................................................... 5

1.1 PEX8603 Features ................................................................................................................................................... 7

1.2 PEX8603 AIC RDK Features ................................................................................................................................. 8

1.3 Getting Started ......................................................................................................................................................... 9

2 PEX8603 RDK HARDWARE ARCHITECTURE ........................................................................ 10

2.1 Architecture Block Diagram ................................................................................................................................. 10

2.2 Board Components ................................................................................................................................................ 11

2.3 PEX8603 PCI Express Switch .............................................................................................................................. 13

2.4 PCI Express Upstream Port Connection ............................................................................................................. 13

2.5 PCI Express Downstream Port Connections ....................................................................................................... 13

2.6 Hardware Strap Pin Dipswitches ......................................................................................................................... 13

2.7 Dipswitch Setting Tables ....................................................................................................................................... 14

2.8 Power Circuitry ..................................................................................................................................................... 16

2.9 Serial EEPROM Interface .................................................................................................................................... 16

2.10 JTAG Interface .................................................................................................................................................. 16

2.11 I2C/SMBUS Interface ........................................................................................................................................ 17

2.12 FATAL_ERR#, and INTA# .............................................................................................................................. 18

2.13 Reference Clock Circuitry ................................................................................................................................. 18

2.14 Reset Circuitry ................................................................................................................................................... 18

2.15 Port Good Indicator LEDs ................................................................................................................................ 19

2.16 PCIe Protocol Debug ......................................................................................................................................... 20

2.17 WAKE# and Vaux Support............................................................................................................................... 20

3 RDK CONFIGURATIONS .......................................................................................................... 21



3.1 Default Strap Pin Settings Diagram ..................................................................................................................... 21

3.2 Hardware Strap Pins ............................................................................................................................................. 22

3.3 Configuration Modules ......................................................................................................................................... 22

3.4 Hardware Jumpers ................................................................................................................................................ 23

Figures Figure 1. PEX8603 RDK Front View ___________________________________________________________________________ 6 Figure 2. Getting Started ______________________________________________________________________________________ 9 Figure 3. RDK Architecture ____________________________________________________________________________________ 10 Figure 4. RDK Component Locations ____________________________________________________________________________ 12 Figure 5. Configuration Dipswitches ____________________________________________________________________________ 13 Figure 6. EEPROM in Socket ___________________________________________________________________________________ 16 Figure 7. Pin Assignment of JTAG Port Header, JP1 ________________________________________________________________ 17 Figure 8. I2C Plug Orientation _________________________________________________________________________________ 17 Figure 9. Pin Assignment of I2C Connector JP2 ___________________________________________________________________ 18 Figure 10. Fatal Error and INTA# LEDs ___________________________________________________________________________ 18 Figure 11. Manual PERST# button ______________________________________________________________________________ 19 Figure 12 Lane Good LEDs ____________________________________________________________________________________ 19 Figure 13: Midbus 2.0 Probe Footprint __________________________________________________________________________ 20 Figure 14. Default Dipswitch Settings ___________________________________________________________________________ 21

Tables Table 1. PEX8603 Port Configurations ____________________________________________________________________________ 5 Table 2 Component Table ____________________________________________________________________________________ 11 Table 3. SW1 Functions ______________________________________________________________________________________ 14 Table 4. SW2 Functions ______________________________________________________________________________________ 15 Table 5. SW3 Functions ______________________________________________________________________________________ 15 Table 6. SW4 Functions ______________________________________________________________________________________ 15 Table 7. Port Indicator Blink Pattern ____________________________________________________________________________ 19 Table 8. PEX8603 StrapPortCfg Settings _________________________________________________________________________ 22 Table 9. Configuration Module Description _______________________________________________________________________ 22 Table 10. PEX8603 Jumper Settings _____________________________________________________________________________ 23



1 General Information The PEX8603 TQFP RDK is a PLX Rapid Development Kit intended primarily for use by PLX customers for silicon evaluation and design reference. The form factor is based on the PCI Express Card Electromechanical specification. The board is designed to work by plugging internally into a PCI Express compliant motherboard. Figure 1 shows the board outline and component placement. The PEX8603 TQFP RDK has 1 x4 upstream port connector and 2 x16 PCIe connectors. The upstream edge connector has 1 or 2 PCIe Gen2 lanes electrically connected to it, and the downstream PCIe connectors have 1 PCIe Gen2 lane each electrically connected to it depending on the installed configuration module. The PEX8603 TQFP RDK supports the use of one configuration module slot to provide flexibility in the routing of PCIe lane 1 to either the x4 PCIe edge connector or to one of the PCIe slots. The Configuration Module enables the RDK to support the following port configurations:

Table 1. PEX8603 Port Configurations

PEX 8603 Port Configuration

0h x1, x1, x1

1h x2, x1

The PEX8603 TQFP RDK meets the ROHS guidelines for electronic components, and hardware.



G1

47

2

G2

48

JP11

G1

47

2

G2

48

JP8

JP

9

JP

7

19

18

24

6

7 12

13

U8

32

33

64

6596

97

12

8

U1

D8 43

2

D7

43

2

16

14

12

10

8

6

4

2

H

I J

20

18

P1

15

13

11

9

7

5

3

1

A B

C D E F G

19

17

20

19

2

JP1

10 9

B8

2B1

2

P4

B1

1

B1

PCB Edge

U5

6

7 12

13

18

1924

U75

42

B3

2

P2

B1

B1

7

L2

L1

2

4

3

S2

2

S1

4

3

1112

2

JP10

10 11

20U12

U1320

1110

L3

3U9

6

4

TP48

TP21TP32

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP

20

TP

19

TP18

TP31

TP30

TP

17

TP16

TP

15

TP37

TP36

TP35

TP34

TP33

TP3

TP

47

TP

46

TP1

TP2

TP4

C138

C2

4

C2

2

C1

32

C120

C18

C1

13

C126

C3

6C

43

C56

C57

C6

8

C69

C7

0

C71

C59

C58

8

5

RN2

4

RN1

8

4 5

RN3

8

4 5

8

54

RN

4

8

RN5

54

RN6

8

54

16ON

9

SW2

8

ON16

9

SW3

8

ON

12

SW4

6

7

P3

A70 A82

B70 B82

A60A50A40

B60B40 B50

A30A20A12

B12 B20 B30

B1

A10A2

B2 B10

P5

A70 A82

B82B70

A60A50A40

B60B40 B50

A30A20A12

B12 B20 B30

B1

A10A2

B2 B10

8

U2

54

5

8

4

SW1

1

5

43

U10

5

43

U11

C15

C9

C8

C7

C6

C5

C11

C10

D9

D10

D11

D1

D4

D5

D6

D2

D3

R37

R36

R35

R34

C3

5

C3

4

C3

2

C3

1

C3

0

C2

9

C128

C124

C127

2

10

JP4

9

2

10

JP2

9

JP6

3

2

JP5

2

JP3

R110

C60

C1

37

R109

R108

R1

07

R106

R1

05

R1

04

R3

1

R44

R43

C3

3

R4

0

R4

6

R41

R33

R3

2

R2

9

R2

7

R26

C2

6

C65

C1

12

C1

25

C52

C53

C6

4

C6

6C

67

C46

C47

R6

R7

7

R81

C55

C54

R3

R4

R5

R1

R2

R4

8

R4

9

C5

1

C4

9

R1

9

R2

0

R2

3

R22

R2

1

R1

8

R17

R1

6

R1

5

R14

R1

3

C1

6

C1

4C

13

C1

2

C44

C45

R5

8

R5

9R

63

R67 R68

R71

R8

5

R84

R8

3

R82

R80

R79R78

R76R75

R74

R5

3

SLOT_PERST#

DBGMODE

SMBUS_EN#

PORTCFG0

UPCFG_TIMER_EN#

I2C_ADDR2

I2C_ADDR1

I2C_ADDR0

GPIO1

GPIO2

TESTMODE3

TESTMODE2

TESTMODE1

PROBE_MODE#

SERDES_MODE_EN#

PLL_BYPASS#

FAST_BRINGUP#

DEBUG_SEL#

TESTMODE0

GPIO0

GPIO3

PLX Technology, Inc. C 2013

SLOT 1

3.3VAUX

3.3VCC

12VCC

PWRGD_12

PWRGD2_12

I2C

SLOT 2

SLOT 3

LANEGOOD3#

LANEGOOD2#

LANEGOOD1#

LANEGOOD0#

FERR#

INTA#

PWRON_RST#

PERST#

DB

G_P

R2

DB

G_P

R3

DBG_SELBUS

DB

G_P

R0

DB

G_P

R1

JTAG

Figure 1. PEX8603 TQFP RDK Front View



1.1 PEX8603 Features The PEX 8603 supports the following features:

• 3-Port PCI Express switch

– 3 Lanes with integrated on-chip SerDes

– Low-power SerDes (under 90 mW per Lane)

– Fully Non-Blocking Switch architecture

– Port configuration

3 independent Ports

Choice of Link width (quantity of Lanes) per unique Link/Port (x1, x2)

Configurable with serial EEPROM or I2C

• High Performance

– Full line rate on all Ports

– Cut-Thru packet latency of less than 250 ns between symmetric (x1 to x1)

– Maximum Payload Size – 256 bytes

• Quality of Service (QoS) support

– All Ports support one, full-featured Virtual Channel (VC0)

– All Ports support eight Traffic Class (TC[7:0]) mapping, independently of the other Ports

– Weighted Round-Robin (WRR) Port arbitration

• Reliability, Availability, Serviceability (RAS) features

– Electromechanical Interlock supported with Power Enable output

– Baseline and Advanced Error Reporting capability

– JTAG AC/DC boundary scan

INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) (Conventional PCI SERR# equivalent) pin support

3 General-Purpose Input/Output (GPIO) pins, which can be used for Link Status LEDs, GPIOs, and/or Interrupt

inputs

• Other PCI Express Capabilities

– Transaction Layer Packet (TLP) Digest support for Poison bit

– Lane reversal (Port 0 only, when Port 0 is configured with a x2 Link width)

– Polarity reversal

– Conventional PCI-compatible Link Power Management states

L0, L0s, L1, L2, and L2/L3 Ready

L3 (with Vaux supported)

– Conventional PCI-compatible Device Power Management states

D0, D1, D2, and D3hot

D3cold (with Vaux supported)

– Active State Power Management (ASPM)

– Dynamic speed (2.5 or 5.0 GT/s) negotiation

– Dynamic Link-width negotiation

• Out-of-Band Initialization options



– Serial EEPROM

– I2C and SMBus (7-bit Slave address with 100 Kbps)

• Testability – JTAG support for DC

• 14x14mm2 128-lead TQFP package

• Typical power – 0.8W

1.2 PEX8603 AIC RDK Features • PEX8603-AB PCI Express 3-port Gen 2 PCIE Switch

• X4 Upstream goldfinger

• Two downstream PCI Express x16 Slot Connectors

• DIP Switches for hardware configuration of PEX8603

• Socketable Serial EEPROM

• Manual push-button PERST# capability

• I2C /SMBus header for Out-of-Band register access

• JTAG header for testability



1.3 Getting Started

1

2

3

4

Figure 2. Getting Started

Follow the following steps to use the RDK.

1) Plug board into x16 PCI Express slot on motherboard.

2) Check and set dipswitches for desired port configuration.

3) Check that the correct configuration module is plugged into the socket.

4) Plug in PCI Express endpoints into downstream slots.

After all these steps are completed, system can be powered on.



2 PEX8603 RDK Hardware Architecture

2.1 Architecture Block Diagram

x1

PEX 8603 TQFP

(U1)

Lane0

Lane2

X4 Card Edge(P2)

x1

X16 Connector(P3)

x1

RefClk

Buffer (U8)

EEPROM

(U2)

JTAG

(JP1)

I2C

(JP2)

DIPSW

PERST#

Status LED

X16 Connector(P5)

CM

Lane1

x1

Figure 3. RDK Architecture



2.2 Board Components (Refer to Figure 4. RDK Component Locations)

Table 2 Component Table

Component Location Component Location

PCI Express Slots (P3,P5) 1 JTAG connector (JP1) 8

Lane Good LEDs (D3,D4,D5,D6) 2 PEX8603 Chip (Chip not installed in

diagram) (U1)

9

Power-on Reset Button (S2) 3 PCIE Goldfinger (P2) 10

PERST# Button (S1) 4 Voltage Indicator LEDs (D9,D10,D11) 11

I2C Connector (JP2) 5 Configuration Module Socket (P2) 12

EEPROM Enable Jumper (JP3) 6 Configuration Dipswitches (SW1-SW4) 13

EEPROM Chip with Socket (U2) 7



3

4

5

6

7

8

10

11

12

13

1

9

2

Not used for 8603

PEX8603 RDK

Figure 4. RDK Component Locations



2.3 PEX8603 TQFP PCI Express Switch The PEX8603 is a 3-lane, 3-port PCIe Gen2 switch. It comes in a 14x14mm2 128-lead TQFP package.

2.4 PCI Express Upstream Port Connection The upstream x4 connector can be a x1 or x2 link connecting the PEX8603 to the add-in card male edge connector. The PEX8603 RDK can plug into x1 PCI Express slots by using a PCI Express lane converter, such as PCI Express X4-To-X1 Converter made by Adex Electronics.

2.5 PCI Express Downstream Port Connections The PEX8603 RDK has 2 x16 type PCIe connectors. Slot 3 can be connected to lane 1 in the x1x1x1x1 port configuration.

2.6 Hardware Strap Pin Dipswitches The PEX8603 has a number of strap pins which provide the capability to perform various types of hardware

initialization without the use of EEPROM. There are two main types of switches. The extended actuator dipswitches

contain the main configuration dipswitches and the recessed switches control more advanced and RESERVED

functions.

ON Position,

Strap Value

= ‘0’

OFF

Position,

Strap Value

= ‘1’Recessed

Actuators

Figure 5. Configuration Dipswitches



2.7 Dipswitch Setting Tables Dipswitches are designed such that the “ON” state selects a value of ‘0’ for that switch.

Table 3. SW1 Functions

SW1 Functional Description Switch Position Settings

PORTCFG0

Used to select the PEX8603’s Port configuration.

L = x1 x1 x1

H = X2 x1

Default Setting = L

SMBUS_EN#

System Management Bus Enable

L = Enables SMBUS Mode

H = Enables I2C Mode

Default Setting = H

UPCFG_TIMER_EN#

Link Upconfigure Timer Enable

L = If Link training sequence fails during the Configuration state, the next time the LTSSM exits the Detect state, TS Ordered-Sets advertise only the 2.5 GT/s (Gen 1) data rate and no Autonomous Change support. If Link training continues to fail when the LTSSM is in the Configuration state, the LTSSM continues to alternate between Gen 1 and Gen 2 advertisement every time

it exits the Detect state

H = The Data Rate Identifier symbol in the TS Ordered-Sets always advertises support for both the 5.0 GT/s (Gen 2) data rate and Autonomous Change.

Default Setting = H

DBGMODE

Factory Test Only

Default Setting = L





TESTMODE[3:0]

Factory Test only

Default Setting = HLHL

GPIO0

Factory Test Only

Default Setting = H

I2CADDR[2:0]

I2C Lower Slave Address Bits

Used to define the default value of the three least significant bits of the PEX8603 I2C/SMBus 7-bit Slave address.

Default Setting = LLL



PROBE_MODE#

Factory Test Only

Default Setting = H

SERDES_MODE_EN#

Factory Test Only

Default Setting = H

PLL_BYPASS#

Factory Test Only

Default Setting = H

FAST_BRINGUP#

Factory Test Only

Default Setting = H

DEBUG_SEL#

Factory Test Only

Default Setting = H

GPIO1-3

Factory Test Only

Default Setting = HHH



DBG_PRBSEL[3:0]

Factory Test Only

Default Setting = HHHH

DBG_SELBUS

Factory Test Only

Default Setting = H



2.8 Power Circuitry The PEX8603 RDK is a PCI Express add-in card. All power to the on-board components, including the downstream

ports, come directly from the male card edge +12VDC and +3.3VDC.

There are two DC/DC converters powering the 1.0V SerDes digital and Core Logic supply as well as the Auxiliary Core

supply voltages to the PEX8603 device. There are also two DC/DC converter powering the 2.5V SerDes analog and I/O

supply as well as the Auxiliary I/O supply voltages to the PEX8603 IO cells. and other onboard components for IO

voltage conversion.

Voltage monitoring circuits are placed close to the PEX8603 chip. If the supplies are off 10% of their normal values, red

LED(s) will be turned on to signal the potential voltage problem to the chip. Bypass capacitors, plane capacitors are

used to filter out the voltage noise.

2.9 Serial EEPROM Interface The PEX8603 RDK provides a socketed Serial EEPROM. The contents of the serial EEPROM are used to initialize the

PEX8603 after power-on reset. The RDK contains a Microchip 25AA128 128K serial EEPROM device.

Note the EEPROM device orientation as shown below.

Pin 1

Enable

Figure 6. EEPROM in Socket

2.10 JTAG Interface The PEX8603 RDK contains a dedicated 2x10 JTAG header (JP2). There is no “standard” JTAG header pin arrangement;

therefore, JTAG header type and pin assignments are somewhat arbitrary. The header and pin assignment chosen for

this board is compatible with the Scanworks USB-100 JTAG controller).



GND

GND

GND

GND

Key

TDI

TRST

TMS

TDO

TCK

NC

NC

NC

NC

NC

GND

GND

GND

GND

GND

Figure 7. Pin Assignment of JTAG Port Header, JP1

2.11 I2C/SMBUS Interface The PEX8603 provides a two-wire I2C/SMBus compatible slave mode interface with three bit addressing. Through this

out-of-band channel, the users can read, write, and configure the PEX8603 internal registers, run internal output probe

mode, monitor error counters, and monitor status of all ports.

The PEX8603 RDK provides a 10 pin I2C header (JP2). The pin header included is compatible with the Aardvark I2C/SPI

Host Adapter Part Number: TP240141 by TotalPhase.

Figure 8. I2C Plug Orientation



GND

NC

NC

NC

GND

SCL

SDA

NC

SCLK

NC

Figure 9. Pin Assignment of I2C Connector JP2

2.12 FATAL_ERR#, and INTA# The PEX8603 RDK device has a number of chip-specific side band signals that are intended for various uses. The FATAL_ERR# output is used to indicate that the PEX8603 device detected a fatal unrecoverable error. The INTA# output is used to be compatible with PCI. The FATAL_ERR# shall also drive a red LED indicator, and the INTA# signal shall drive an amber colored LED indicator.

Figure 10. Fatal Error and INTA# LEDs

2.13 Reference Clock Circuitry The PEX8603 RDK uses the RefClk provided at the male add-in card edge connector. This clock goes through a clock

fan-out buffer circuit and provides the Refclk to the 3 downstream connectors and the PEX8603.

2.14 Reset Circuitry The reset circuit of PEX8603 RDK contains a two input AND gate and a reset chip. The PERST# from the PCI Express

male connector and the manual reset from the pushbutton switch input to the AND gate and the output of the AND

gate is fed into the reset chip. The PERST# button (S1) and the PWRON_RST# button (S2) are shown below:



Figure 11. Manual PERST# button

2.15 Port Good Indicator LEDs Each PCIe port has a port status indicator associated with it. They are grouped in the upper-left corner of the

board for easily visibility. The port indicator LED is either on, off, or flashing to indicate the link status.

These states are shown in the table below. The RDK has a total of 3 LED indicators for Port 0-2.

The D6 LED is not used in the PEX8603 RDK.

Figure 12 Lane Good LEDs

Table 7. Port Indicator Blink Pattern

Link State LED Pattern

Link Down OFF

Link Up; GEN2 ON

Link Up; GEN1 Blinking: 0.5 sec ON, 0.5 sec OFF



2.16 PCIe Protocol Debug All PCIe Lanes pass through an Agilent soft touch midbus probe footprint in order to monitor PCIe traffic.

Figure 13: Midbus 2.0 Probe Footprint

2.17 WAKE# and Vaux Support The Wake# signals will be connected together and Vaux will be routed from the upstream port to all

downstream slots.



3 RDK Configurations The PEX8603 RDK can be configured to operate in one of several modes as described in this section. The modes can be entered by changing jumpers and configuration modules. The configuration modules control the routing of the PCIE lanes and Refclk, and the strap pin dipswitches configure the modes of the PEX8603.

3.1 Default Strap Pin Settings Diagram

RN6

8

54

RN5

54

8

RN4

54

8

RN3

54

8

RN2

4

8

5

16

9

ONSW2

8

16

ON

9

SW3

8

8

5

SW1

4

C6

C3

R13

R1

2

TP24

C69

C65

C94

C81

GPIO2

GPIO1

DEBUG_SEL#

FAST_BRINGUP#

PLL_BYPASS#

SERDES_MODE_EN#

PROBE_MODE#

TESTMODE0

TESTMODE1

TESTMODE2

TESTMODE3

DBGMODE

UPCFG_TIMER_EN#

SMBUS_EN#

PORTCFG0

GPIO3

I2C_ADDR0

I2C_ADDR1

GPIO0

I2C_ADDR2

Figure 14. Default Dipswitch Settings



3.2 Hardware Strap Pins The PEX8603 RDK has a number of strap pins which provide the capability to perform various types of

hardware initialization without the use of EEPROM. Table 9 shows the port configuration strap pin values.

Table 8. PEX8603 StrapPortCfg Settings

PEX8603 StrapPortCfg Options

StrapPortCfg port 0 port 1 port 2 0.default x1 x1 x1 1 x2 x1

3.3 Configuration Modules

Table 9. Configuration Module Description

Configuration Module

Goldfinger Slot1 Slot2

CM107 x2 x1 x1

CM108 x1 x1 x1



3.4 Hardware Jumpers The PEX8603 RDK has a few jumper settings for testing purposes. These can be left at their default settings,

as detailed below: Table 10. PEX8603 Jumper Settings

Jumper Default Setting Description

JP3 ON Connects the EE_CS# signal of the PEX8603 to the EEPROM.Can be used to disable the EEPROM for testing.

JP6 2-3 1-2 : Connects the 3.3Vaux power rail to the 3.3VCC power coming from the PCIE slot.

2-3: Connects the 3.3Vaux power rail to the 3.3Vaux power coming from the PCIE slot. (Default setting)

Documents

Hardware Reference Manual PEX8603 TQFP-AIC Rapid ... · s lo t_ p e r s t# dbg mo e s mbus _ e n# p o r tc f g 0 up c f g _tim er n# i2 c _ addr 2 i2 c _ addr 1 i2 c _ addr 0 g p