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HBD FEE test result summary+ production schedule
• 16mv test pulse result– 5X attenuator + 20:1 resistor divider at input
• (to reduce the noise on the test pulse input)
• Result on the digitized baseline noise• Large input pulse• Digital filter
– A nice, necessary, feature to remove the low frequency noise.
• First look of the production schedule
FEE testing block diagram
PreampTestJig
PulseGenerator
Clock Master
Pulse Generatortrigger
5x attenuator
scope
L1 trigger
FEM
receiver ADC+FPGA
data
computer
20:1 attenuator
Receiver
ADCTest point for receiver output
Signals from Preamp
Receiver/shaping
ADC
FPGA
HBD ADC board
Test stand
Preamp test jig
ADC module
16mv test pulse
0
50
100
150
200
250
1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46
channel
ad
c c
ou
nts
16MV test pulse on all the channels on FEM number 2
The test is done by moving test jigs cables (6 outputs) 8 times.
10mv, 100ns per division
Digital sum20mv/division
60Mhz noisekicks back from ADC
Preampoutput
Output of FEM
receiver
Digitized 16mv test pulse result
Reverse the signal cable
RMS
2 samples at rising edge
1-2 ns time jitter on the test pulse
RMS on the baseline in varies conditions
condition RMS ADC distribution on the baseline
Preamp + test jig 1.4 counts
Nothing connected to the FEM .34 counts
Cable connected to the FEM with two 50ohms termination
.31 counts
cable connected to the test jig with 2 50ohms termination without preamp
.43 counts
Preamp + test jig -- shielded
16mv test pulse generated about 210 ADC counts
Overflow pulse
Preamp pulse200mv, 20nsper division
Preamp pulse seen by channel 4 with noisy power line (100 events)
Digitized result
Baseline distributionSample # 4
ADC
samples
ADC
Digital filtered preamp pulse on channel 4 data with noisy power line (100 events)
pulse(n+2) –pulse(n)
sample
Baseline distributionSample # 4
ADC
First look at production• Assume RUN 7 electronics installation in Sept 06.
– One month contingency August• 2 months PCB production + assembly
– We only have to build 50 FEMs. This time could be shorten.– Schedule final design review on the electronics.
• chain test with detector– To understand ground, gain/shaping time of the FEM etc– Once the parts is solder to the PCB, it is final…
• 3 months parts procurements– 1 month to generate P.O. and 2 months to get the parts
• March is the time to buy parts.– Once we send out RFQ, we will know how good is the 3 months
estimate.• Risks
– March is the time to get ready for the RUN 6 test• Split manpower and attention