HDL+ 20154

ICHDLVerilog HDLVHDL**/86

IC

1. (C)MATLAB

2. RTL

3.

4. **/86

IC(TOP-DOWN)FPGAASIC

TOP-DOWN TOP-DOWN **/86

(/)HDLEDAHDL

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VHDLVerilog HDL2080IEEE

VHDL

Verilog HDLC **/86

Verilog HDLICEDANetlistASICFPGAVerilog HDLAlteraMAX+PLUS IIQuartus IIXilinxFoundation ISE**/86

1CC

2

3

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4Verilog HDL 5 **/86

Verilog HDL--**/86

Verilog HDL

module adder8 (cout, sum, ina,inb, cin);output [7:0] sum;output cout;input [7:0] ina,inb;input cin; assign {cout,sum}= ina+inb+cin;endmoduleVerilog HDL --**/86

.Verilog HDL

Verilog HDL

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module inputoutputinout // //wireregtaskfunction assign// alwaysinitial - // endmodule**/86

DFFinput, outputinout(pin)**/86

module DFF (d, clk, clr, q, qb); ....endmodule

module REG4( d, clk, clr, q, qb); output [3: 0] q, qb; input [3: 0] d; input clk, clr; DFF d0 (d[ 0], clk, clr, q[ 0], qb[ 0]); DFF d1 (d[ 1], clk, clr, q[ 1], qb[ 1]); DFF d2 (d[ 2], clk, clr, q[ 2], qb[ 2]); DFF d3 (d[ 3], clk, clr, q[ 3], qb[ 3]);endmoduleREG4DFF**/86

(d0, d1, d2, d3)(module instances):**/86

assign # 2 B = A B2A

`timescale 1ns /100pstimescale Verilog HDL 1ns 1ns100ps100ps #2 2ns**/86

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module MUX2_1 (out, a, b, sel); // Port declarations output out; input sel, // control input b, /* data inputs */ a;/* The netlist logic selects input a when sel = 0 and it selects b when sel = 1.*/ not (sel_, sel); and (a1, a, sel_), (b1, b, sel); or (out, a1, b1);endmoduleinput Ainput Binput A input BVerilog/* */**/86

0, Low, False, Logic Low, Ground,

1, High, True, Logic High, Power,VDD,

X Unknown: Occurs at Logic Which Cannot be Resolved Conflict

HiZ, High Impedance, Tri- Stated,**/86

5 O37 5 11111 4 'D2 4 00104 B1x_01 4 7 Hx 7x (x), xxxxxxx4 hZ 4 z (z) , zzzz 4 d-4 8 h 2A 3' b 001 ' b (2+3) 'b10

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%h%o%d%b%c%s%m%thexoctdecbinACSIIstringmoduletime

\t\n\\\\tabASCII representation of above

(a-z, A-Z)( _ )( $ )( _ )1023selSELmodule MUX2_1 (out, a, b, sel); output out; input a, b, sel; not not1 (sel_, sel); and and1 (a1, a, sel_); and and2 (b1, b, sel); or or1 (out, a1, b1);endmodule

Verilog**/86

shift_reg_a busa_index _bus3 34net // _ a*b_net // $ _ n@238 // $ _VerilogVerilog**/86

A Sum CPU_addrBCClk Clk_50Clk_CPU_n Enable_nD, RstEFGSIZE **/86

net : register parameters() : Verilog**/86

net net netoutorornet**/86

wirewireassign01xzwiretriwiretritrinetnet Z (hign-impedance)**/86

wire 12n

wire a,b,c//wireabcwire[7:0] databus//wirewire[20:1] addrbus //20wire

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reg_areg_breg_sel2:1

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reg (1) integer 32real integertime 64

reg a; //reg [3: 0] v; // MSBLSB4reg [7: 0] m, n; // 8tri [15: 0] busa; // 16wire [0: 31] w1, w2; // 32wireMSBbit0

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net/registernetnet/registernetin1in2OABYnet**/86

Verilog**/86

{ } {{}} ~ & | ^* / %+ ->> < >=

case == case===2b1x==2b0x 02b1x==2b1x x2b1x===2b0x 02b1x===2b1x 1

a = 2'b1x;b = 2'b1x;if (a == b) $display(" a is equal to b");else $display(" a is not equal to b");a = 2'b1x;b = 2'b1x;if (a === b) $display(" a is identical to b");else $display(" a is not identical to b");CaseRTL**/86

= =01xz010xx101xxxxxxxzxxxx

= =01xz0100010100x0010z0001

{ }module concatenation; reg [7: 0] rega, regb, regc, regd; reg [7: 0] new; initial begin rega = 8'b0000_0011; regb = 8'b0000_0100; regc = 8'b0001_1000; regd = 8'b1110_0000; end initial fork #10 new = {regc[ 4: 3], regd[ 7: 5], regb[ 2], rega[ 1: 0]}; // new = 8'b11111111 #20 $finish; joinendmodule**/86

1Verilog HDL`define`include`timescale ` Verilog HDL2 **/86

`timescale `timescale / `timescale 1 ns / 100 ps `timescale `timescale 1 ns / 10 ps// All time units are in multiples of 1 nanosecondmodule MUX2_1 (out, a, b, sel);output out;input a, b, sel;not #1 not1( sel_, sel);and #2 and1( a1, a, sel_);and #2 and2( b1, b, sel);or #1 or1( out, a1, b1);endmodule**/86

time_precisiontime_unitprecisionprecisiontime_unitprecision_unit`timescale 1s / 1ps11012`timescale 1s/1ms103timescalens**/86

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:

primitives() : Verilog(models)

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module rs_latch (y, yb, r, s); output y, yb; input r, s; nor n1( y, r, yb); nor n2( yb, s, y);endmodule**/86

VerilogVerilog Bottom Up**/86

andornotbufxornandnorxnor Logical And Logical Or Inverter Buffer Logical Exclusive Or Logical And Inverted Logical Or Inverted Logical Exclusive Or Inverted

(12)(12: ()

**/86

Verilogoutput, input, enableenable**/86

bufif1 1 bufif0 0 notif1 1 notif0 0

and (out, in1, in2, in3, in4); // unnamed instancebuf b1 (out1, out2, in); // named instance0 notif0 #3.1 n1 (out, in, cntrl); // delay specified**/86

xmodule comp (o1, o2, i1, i2); output o1, o2; input i1, i2; . . .endmodule

module test; comp c1 (Q, R, J, K); // Positional mapping comp c2 (.i2(K), .o1(Q), .o2(R), .i1(J)); // Named mapping comp c3 (Q, , J, K); // One port left unconnectedendmodule.**/86

Verilog wait, while, if then, caseforever**/86

initialalways**/86

1 initial initialbegin 12end2initialbegin#2 Stream = 1;#5 Stream = 0;#3 Stream = 1;#4 Stream = 0;#2 Stream = 1;#5 Stream = 0;end(3)0initial0initialinitial**/86

alwaysalways @()begin ////if//case//while,repeat,for //task,functionend always**/86

posedgenegedge clkclear0 //0 always @(posedge clk or posedge clear) Begin end//0always @(posedge clk or negedge clear) Begin end**/86

beginendforkjoinForkjointest bench**/86

begin #5 a = 3; #5 a = 5; #5 a = 4;endfork #5 a = 3; #15 a = 4; #10 a = 5;joinFork-joinfork-join **/86

repeat repeat ( while while ( forever forever for for( **/86

for ; ; (1)(2) ,(3) (3),2

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module mux2x1_df (A, B, select, OUT); input A, B, select; output OUT; assign OUT = select ? B : A; endmoduleassign**/86

assign always initial assign always initial

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module full_add5(a,b,cin,sum,cout);input a,b,cin;output sum,cout;reg cout,m1,m2,m3; //alwaysregwire s1;xor x1(s1,a,b); //always@(a or b or cin) //alwaysbegin m1=a&b; m2=b&cin; m3=a&cin; cout=(m1|m2)|m3;endassign sum=s1^cin; //assignendmodule**/86

Verilog HDLRTL

RTLRTLRTL**/86

123Verilog HDL45678

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910Integer111213foreverwhile14always15FPGA**/86

VHDL1. entity mux is generic(m:TIME:=1ns) port(A,B,T: in BITZ: out BIT)end mux;

T, A;T, BMUX**/86

architecture connect of mux is begin Caleprocess(ABT) variable tmpl,tmp2,tmp3BIT begin tmp1:=A and T tmp2:=B and (not T) tmp3:=tmp1 or tmp2 Z

-- The entity declarationentity Half_adder is port ( X Half_ SumX: in Bit ; Y adder CarryY: in Bit ; Sum : out Bit ;Carry : out Bit ) ; end Half_adder ;**/86

-- The architecture body :architecture Behavioral_description of Half_adder isbeginprocess begin Sum

entity Full_adder isport (A : in Bit ;B : in Bit ;Carry_in : in Bit ;S : out Bit ;Carry_out : out Bit ) ;end Full_adder ;**/86

architecture Structure of Full_adder is-- signal declarationssignal Temp_sum : Bit ;signal Temp_carry_1 : Bit ;signal Temp_carry_2 : Bit ;-- local component declarationscomponent Half_adderport ( X : in Bit ;Y : in Bit ;Sum : out Bit ;Carry : out Bit ) ;end component ;**/86

component Or_gate port (In1 : Bit : In2 : Bit ; Out1 : out Bit ) ; end component ;

-- component instantiation statementsU0 : Half_adderport map ( X => A, Y => B, Sum => Temp_sum, Carry => Temp_carry_1 ) ;U1 : Half_adderport map ( X => Temp_sum , Y => Carry_in Sum => S , Carry => Temp _Carry_2 ) ;U2 : Or_gateport map ( In1 => Temp_carry_1, In2 => Temp_carry_2 , Out1 => Carry_out ) ;end structure ;**/86

entity is [] [ begin ]end []

Architecture of is [] begin [] end [] **/86

entity Full_adder isarchitecture Structure of Full_adder isarchitecture Structure1 of Full_adder isentity mux isarchitecture Structure of mux is**/86

VHDL(Package)

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Package is { } end [] Package body is { }end []

, **/86

VHDLusePackage Logic is type Three_level_logic is (01z) function lnvert (inputThree_1evel_logic) return Three_1evel_logicend logic;**/86

package body Logic is function invert( input:Three_level_1ogic) return Three_level_logic is begin case lnput is when0 return1 when1 return0 whenz returnz end case; end invert;end Logic; **/86

use, use IEEE.STD_LOGlC_1164a11 IEEE STD_LOGIC_1164 use Logic.Three_level_logic Logic Three_level_logic**/86

configuration of is [ use] []end []**/86

architecture Structure_View of Processor is***end Structure_View;

library TTL.Workconfiguration V4_27_87 of processor is use WorkAll; for Structure_View ***end V4_27_87;**/86

VHDL VHDL- use**/86

VHDL5IEEE--IEEESTD--VHDLASIC----WORK--**/86

WORK4 LibraryLibraryLibrary use Library IEEE; Use IEEESTD_LOGIC_1164all;useuse**/86

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VHDL(signal),,

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-- **/86

FSK--564KHz564 KHzkbps14.5MHz(8)03.9MHz(7)

144.5MHz803.53.9MHz7

*/78

**Modelsim mkdir sim cd simModelsimsource /opt/demo/modelsim.envvsim&

**Modelsim

FileNewlibrary FileNewproject.vproject,testbench

*64*

64

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verilog

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**1616

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testbench

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testbench

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THE END**/86

*134*RTL

*134*134*

*134*134*HDL

*134*134*Amodule endmodule,.Top-Down[3]B module addr (a, b, cin, cout, sum); module addr pin I/OI/O input [2:0] a; input [2:0] b; input cin; output cout; inputoutputinout [n:0] assign d_out = d_en ? din :'bz;mytri u_mytri(din,d_en,d_out)HDLassign always CDVerilog HDL Eendmodule *134*134**134*134*Verilog HDL /**/ // // table

*134*134*( identifier Verilog HDL ( identifier)$_()*134*134**134*134*134*134*RTL

134*134*134