HDL Lab Manual

CONTENTS

PROGRAMMING (using VHDL and VERILOG) 1. Write HDL code to realize all the logic gates

2. Write a HDL program for the following combinational designs

A. 2 to 4 decoder

B. 8 to 3 (encoder without priority & with priority)

C. 8 to 1 multiplexer

D. 4 bit binary to gray converter

E. Multiplexer, demultiplexer, comparator

3. Write a HDL code to describe the functions of a full adder using following modeling styles,

4. Write a model for 32-bit ALU using the schematic diagram shown below.

a (31:0) b (31:0)

ALU should use combinational logic to calculate an output based on the four bit op-code input.

ALU should pass the result to the out bus when enable line in high, and tri-state the out bus when the

enable line is low.

ALU should decode the 4 bit op-code according to the given in example below

OPCODE ALU OPERATION

1 A + B

2 A - B

3 A Complement

4 A * B

5 A AND B

6 A OR B

7 A NAND B

8 A XOR B

5. Develop the HDL codes for the following flip-flops, SR, D, JK, T.

6. Design 4 bit binary, BCD counters (synchronous reset and asynchronous reset) and “any

sequence” counters.

Interfacing (At least four of the following must be covered using VHDL /VERILOG) 1. Write HDL code to display messages on the given seven segment display and LCD and accepting

hex key pad input data.

2. Write HDL code to control speed, direction of dc and stepper motor.

3. Write VHDL code to generate different waveforms (sine square triangle, ramp etc) using DAC

change the frequency and amplitude

4. Write VHDL code to control external lights using relays.

5. Write a HDL code to accept 8 channel analog signal, temperature sensors and display the data on

lcd panel or seven segment display

6. Write VHDL code to simulate elevator operations

OPCODE(3:0)

ENABLE

OUT

HDL LAB (06ECL48)

2 Department of Electronics & Communication, K.I.T, Tiptur

Extra program in HDL Lab 1) Write HDL code for full adder using structural design

2) Write HDL code for a carry look ahead adder

3) Write HDL code for 9bit parity generator using structural design

4) Design a ripple counter for given sequence 0-1-3-5-7-9-11-13-15-0 using JK flip flop

5) Write HDL code for the given mealy FSM state table

0 1

ST0 ST0

0

ST3

1

ST1 ST1

1

ST0

0

ST2 ST2

0

ST1

1

ST3 ST2

0

ST1

0

6) Write a HDL program for the given more FSM state diagram

Entries in table are

next state, input A

and output Z

ST1

ST1

ST1

ST1

A=’1’

A=’0’

Z<=’1’

A=’1’

A=’1’

A=’1’

A=’0’

A=’0’ Z<=’1’

Z<=’0’

HDL LAB (06ECL48)


1.a) VHDL CODE FOR ALL THE BASIC GATES.

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY GATES IS

PORT ( A : IN STD_LOGIC;

B : IN STD_LOGIC;

OP_NOT : OUT STD_LOGIC;

OP_OR : OUT STD_LOGIC;

OP_AND : OUT STD_LOGIC;

OP_NOR : OUT STD_LOGIC;

OP_NAND : OUT STD_LOGIC;

OP_XOR : OUT STD_LOGIC;

OP_XNOR : OUT STD_LOGIC);

END GATES;

ARCHITECTURE BEHAVIORAL OF GATES IS

BEGIN

OP_NOT <= NOT A;

OP_OR <= A OR B;

OP_AND <= A AND B;

OP_NOR <= A NOR B;

OP_NAND <= A NAND B;

OP_XOR <= A XOR B;

OP_XNOR <= A XNOR B;

END BEHAVIORAL;

1. b)VERILOG CODE FOR ALL BASIC GATES

module gates(A, B, OP_NOT, OP_OR,OP_NOR, OP_AND, OP_NAND, OP_XOR, OP_XNOR);

input A;

input B;

output OP_NOT;

output OP_OR;

output OP_AND;

output OP_NOR;

output OP_NAND;

output OP_XOR;

output OP_XNOR;

reg OP_NOT, OP_OR, OP_AND, OP_NOR,OP_NAND, OP_XOR, OP_XNOR;

always @ (A , B)

begin

OP_NOT= ~A;

OP_AND= A&B;

OP_NAND= ~(A&B);

OP_OR= A|B;

OP_NOR=~(A|B);

OP_XOR= A^B;

OP_XNOR = ~(A^B);

end

endmodule

Basic

Gates

A

B

OP_NOT

OP_OR OP_AND

OP_NOR

OP_NAND

OP_XOR

OP_XNOR

HDL LAB (06ECL48)


RESULT:

WAVEFORM

A B

0 0 1 0 0 1 1 0 1

0 1 1 1 0 0 1 1 0

1 0 0 0 0 0 1 1 0

1 1 0 1 1 0 0 0 1

A

OP_NOT

A

B OP_OR

A

B OP_AND

A

B

OP_ NOR

A

B OP_ NAND

A

B OP_ XOR

A

B OP_ EXNOR

HDL LAB (06ECL48)


2. a) VHDL CODE FOR 2 TO 4 DECODER.

ENTITY DECODER2_4 IS

PORT ( ENABLE: IN STD_LOGIC;

SEL: IN STD_LOGIC_VECTOR (1 DOWNTO 0);

D_OUT: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));

END DECODER2_4;

ARCHITECTURE DECODER_ARC OF DECODER2_4 IS

BEGIN

PROCESS (ENABLE,SEL)

BEGIN

IF (ENABLE = '1') THEN

D_OUT <= "0000";

ELSE

CASE SEL IS

WHEN "00" => D_OUT <= "0001";

WHEN "01" => D_OUT <= "0010";

WHEN "10" => D_OUT <= "0100";

WHEN "11" => D_OUT <= "1000";

WHEN OTHERS => NULL;

END CASE;

END IF;

END PROCESS;

END DECODER_ARC;

2. b) VERILOG CODE FOR 2 TO 4 DECODER

module DECODER (SEL,EN,D_OUT);

input [1:0] SEL;

input EN;

output [3:0] D_OUT;

reg [3:0] D_OUT;

always @(SEL , D_OUT)

if (EN==1)

D_OUT=4’b0000;

else

begin

case (SEL)

2'b00: D_OUT = 4'b0001;

2'b01: D_OUT = 4'b0010;

2'b10:D_OUT = 4'b0100;

2'b11: D_OUT = 4'b1000;

default: D_OUT

=4'bXXXX;

endcase

end

endmodule

RESULT:-

WAVEFORM

Enable Select

Lines

Outputs

E S1 S0 D_OUT(0) D_OUT(1) D_OUT(2) D_OUT(3)

1 X X 0 0 0 0

0 0 0 1 0 0 0

0 0 1 0 1 0 0

0 1 0 0 0 1 0

0 1 1 0 0 0 1

Sel (0)

Sel (1)

2-4

DECODER

ENABLE

D_OUT (0)

D_OUT (1)

D_OUT (2)

D_OUT (3)

HDL LAB (06ECL48)


3. a) VHDL CODE FOR 8 TO 3 ENCODER.

ENTITY ENCODER8_3 IS

PORT ( ENABLE: IN STD_LOGIC;

SEL: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

D_OUT: OUT STD_LOGIC_VECTOR(2 DOWNTO 0) );

END ENCODER8_3;

ARCHITECTURE ENCODER_ARCH OF ENCODER8_3 IS

BEGIN

PROCESS(ENABLE,SEL)

BEGIN

IF ( ENABLE = '1') THEN

D_OUT <= "000";

ELSE

CASE SEL IS

WHEN "00000001" => D_OUT <= "000";

WHEN "00000010" => D_OUT <= "001";

WHEN "00000100" => D_OUT <= "010";

WHEN "00001000" => D_OUT <= "011";

WHEN "00010000" => D_OUT <= "100";

WHEN "00100000" => D_OUT <= "101";

WHEN "01000000" => D_OUT <= "110";

WHEN "10000000" => D_OUT <= "111";


END CASE;

END IF;

END PROCESS;

END ENCODER_ARCH;

3 b).VERILOG CODE FOR 8TO 3 ENCODER

module ENCODER8_3(EN, SEL, D_OUT);

input EN;

input [7:0] SEL;

output [2:0] D_OUT;

reg [2:0] D_OUT;

always @ (SEL)

begin

if(EN==1)

D_OUT=3’B000;

else

begin

case(SEL)

8’b00000001: D_OUT=3'b000;

8’b00000010: D_OUT =3'b001;

8’b 00000100: D_OUT =3'b010;

8’b00001000: D_OUT =3'b011;

8’b00010000: D_OUT =3'b100;

8’b00100000: D_OUT =3'b101;

8’b01000000: D_OUT =3'b110;

8’b10000000:D_OUT =3'b111;

default: D_OUT=3’bxxx;

endcase

end

end

endmodule

SEL(0)

SEL(1)

SEL(2)

SEL(3)

SEL(4)

SEL(5)

SEL(6)

SEL(7)

8 : 3

ENCODER

ENABLE

D_OUT(0)

D_OUT(1)

D_OUT(2)

HDL LAB (06ECL48)


RESULT

INPUTS OUTPUTS

ENABLE SEL(0) SEL(1) SEL(2) SEL(3) SEL(4) SEL(5) SEL(6) SEL(7) D_OUT

(0)

D_OUT

(1)

D_OUT

(2)

1 X X X X X X X X 0 0 0

0 1 0 0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 0 0 0 1

0 0 0 1 0 0 0 0 0 0 1 0

0 0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 0 1 1 1 1

WAVEFORM

HDL LAB (06ECL48)


4 a). VHDL CODE FOR 8:1 MUX.

ENTITY MUX8_1 IS

PORT ( SEL: IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- SELECT LINES

A,B,C,D,E,F,G,H :IN STD_LOGIC;-- INPUTS OF THE MUX.

MUX_OUT: OUT STD_LOGIC ); -- OUTPUT OF THE MUX.

END MUX8_1;

ARCHITECTURE MUX4_1_ARCH OF MUX8_1 IS

BEGIN

PROCESS (SEL,A,B,C,D,E,F,G,H)

BEGIN

CASE SEL IS

WHEN "000" => MUX_OUT <= A;

WHEN "001" => MUX_OUT <= B;

WHEN "010" => MUX_OUT <= C;

WHEN "011" => MUX_OUT <= D;

WHEN "100" => MUX_OUT <= E;

WHEN "101" => MUX_OUT <= F;

WHEN "110" => MUX_OUT <= G;

WHEN "111" => MUX_OUT <= H;


END CASE;

END PROCESS;

END MUX4_1_ARCH;

4 b). VERILOG CODE FOR 8TO 1 MUX

module MUX8_1(A,B,C,D,E,F,G,H, SEL, D_OUT);

input A,B,C,D,E,F,G,H;

input [2:0] SEL;

output MUX_OUT;

reg D_OUT;

always @ (A , SEL )

case (SEL)

3'b000: MUX_OUT =A;

3'b001: MUX_OUT =B;

3'b010: MUX_OUT =C;

3'b011: MUX_OUT =D;

3'b100: MUX_OUT =E;

3'b101: MUX_OUT =F;

3'b110: MUX_OUT =G;

3'b111: MUX_OUT =H;

default: MUX_OUT =0;

endcase

endmodule

8 : 1

MUX

A

B

C

D

E

F

G

H

SEL SEL SEL

(0) (1) (2)

MUX_OUT

HDL LAB (06ECL48)


RESULT:

INPUTS OUTPUT

SEL[0] SEL[1] SEL[2] MUX_OUT

0 0 0 A

0 0 1 B

0 1 0 C

0 1 1 D

1 0 0 E

1 0 1 F

1 1 0 G

1 1 1 H

WAVE FORM

5 a). CODE 4 BIT BINARY TO GRAY CONVERTER.

ENTITY BINARY_GRAY IS

PORT( A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

B: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END BINARY_GRAY;

ARCHITECTURE BEHAVIORAL OF BINARY_GRAY IS

BEGIN

B(3)<= A(3);

B(2)<= A(3) XOR A(2);

B(1)<= A(2) XOR A(1);

B(0)<= A(1) XOR A(0);

END BEHAVIORAL;

B2 B1 B0

A1 A0 A1 A0 A1 A0

A(0)

A(1)

A(2)

A(3)

B(0)

B(1)

B(2)

B(3)

HDL LAB (06ECL48)


A3 A2 00 01 11 10 A3 A2 00 01 11 10 A3 A2 00 01 11 10

00 00 1 1 00 1 1

01 1 1 1 1 01 1 1 01 1 1

11 11 1 1 11 1 1

10 1 1 1 1 10 1 1 10 1 1

B3 = A3

B2 = A3 A2’ + A3 A2’

B2 = A3 ⊕ A2

B1 = A2 A1’ + A1 A2’

B1 = A1 ⊕ A2

B0 = A1’A0 + A1 A0’

B0 = A1 ⊕ A0

5 b).VERILOG CODE FOR BINARY TO GRAY CONVERTER

module BINARY_GRAY(A, B);

input [3:0] A;

output [3:0] B;

reg [3:0] B;

always @ (A , B)

begin

B[3] = A[3];

B[2] = A[3] ^ A[2];

B[1] = A[2] ^ A[1];

B[0] = A[1] ^ A[0];

end

endmodule

RESULT:

Binary inputs Gray Outputs

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

HDL LAB (06ECL48)


WAVE FORM

6 a). VHDL CODE FOR 1:4 DEMUX.

ENTITY DEMUX1_4 IS

PORT ( D_IN: IN STD_LOGIC; --INPUT FOR DEMULTIPLEXER

SEL: IN STD_LOGIC_VECTOR (1 DOWNTO 0); --SELECT LINE OF DEMUX

D_OUT: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); --OUTPUT LINES OF DEMUX

END DEMUX1_4;

ARCHITECTURE DEMUX1_4_ARCH OF DEMUX1_4 IS

BEGIN

PROCESS(D_IN,SEL)

BEGIN

D_OUT<="0000";

CASE SEL IS

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

D_IN

1:4

DEMUX

SEL[0] SEL[1]

D_OUT[0]

D_OUT[1]

D_OUT[2]

D_OUT[3]

HDL LAB (06ECL48)


WHEN "00" => D_OUT(0)<=D_IN;

WHEN "01" => D_OUT(1)<=D_IN;

WHEN "10" => D_OUT(2)<=D_IN;

WHEN OTHERS => D_OUT(3)<=D_IN;

END CASE;

END PROCESS;

END DEMUX1_4_ARCH;

===============================================================

UCF FILE(USER CONSTRAINT FILE)

NET "SEL<0>” LOC = "P74";

NET "SEL<1>” LOC = "P75";

NET "D_IN" LOC = "P76";

NET "D_OUT<0>" LOC = "P84";




===============================================================

6 b).VERILOG CODE FOR 1:4 DEMUX

module DEMUX1_4(D_IN, SEL, D_OUT);

input D_IN;

input [1:0] SEL;

output [3:0] D_OUT;

reg[3:0] D_OUT;

always @(D_IN ,SEL)

case (SEL)

2'b00:

begin

D_OUT [0]= D_IN;

D_OUT [1]=0;

D_OUT [2]=0;

D_OUT [3]=0;

end

2'b01:

begin

D_OUT [0]=0;

D_OUT [1]= D_IN;

D_OUT [2]=0;

D_OUT [3]=0;

end

2'b10:

begin

D_OUT [0]=0;

D_OUT [1]=0;

D_OUT [2]= D_IN;

D_OUT [3]=0;

end

2'b11:

begin

D_OUT [0]=0;

D_OUT [1]=0;

D_OUT [2]=0;

D_OUT [3]= D_IN;

HDL LAB (06ECL48)


end

default D_OUT =4'b0000;

endcase

endmodule

RESULT:-

SELECT INPUT OUTPUT

SEL[0] SEL[1] D_IN D_OUT[0] D_OUT[1] D_OUT[2] D_OUT[3]

0 0 1 1 0 0 0

0 1 1 0 1 0 0

1 0 1 0 0 1 0

1 1 1 0 0 0 1

WAVEFORM

7 a). COMBINATIONAL VHDL CODE FOR N BIT COMPARATOR.

ENTITY COMPARATOR IS

GENERIC (N: INTEGER := 3);

PORT( A,B: IN STD_LOGIC_VECTOR(N DOWNTO 0);

ALB,AGB,AEB: OUT STD_LOGIC);

END COMPARATOR;

ARCHITECTURE COMPARATOR_ARC OF COMPARATOR IS

BEGIN

PROCESS(A,B)

BEGIN

IF ( A < B ) THEN ALB <= '1';

4-BIT

COMPARATER

A

B

A<B

A>B

A=B

D_IN

D_OUT

HDL LAB (06ECL48)


ELSE ALB <= '0'; END IF;

IF ( A > B ) THEN AGB <= '1';

ELSE AGB <= '0'; END IF;

IF ( A = B ) THEN AEB <= '1';

ELSE AEB <= '0'; END IF;

END PROCESS;

END COMPARATOR_ARC;

7 b).COMBINATIONAL VERILOG CODE FOR 2-BIT COMPARATOR

module COMPARATER(A, B, ALB,AGB,AEB);

input [1:0] A;

input [1:0] B;

output ALB;

output AGB;

output AEB;

reg ALB,AGB,AEB;

always @ (A , B)

begin

if (A<B)

begin

ALB=1'b1;

AGB=1'b0;

AEB=1'b0;

end

else if (A>B)

begin

AGB=1'b1;

ALB=1'b0;

AEB=1'b0;

end

else if (A==B)

begin

AEB=1'b1;

ALB=1'b0;

AGB=1'b0;

end

end

endmodule

RESULT:

A B A=B A>B A<B

00 00 1 0 0

00 01 0 0 1

01 00 0 0 1

HDL LAB (06ECL48)


WAVEFORM

8a). VHDL CODE FOR THE IMPLEMENTATION OF HALF ADDER.

ENTITY HALFADDER IS

PORT ( A, B: IN STD_LOGIC; --2BIT INPUT

SUM, CARRY : OUT STD_LOGIC); --SUM& CARRY

END HALFADDER;

ARCHITECTURE BEHAVIORAL OF HALFADDER IS

HDL LAB (06ECL48)


BEGIN

SUM <= A XOR B;

CARRY<= A AND B;

END BEHAVIORAL;

8 b). VERILOG CODE FOR THE IMPLEMENTATION OF HALF ADDER.

module HALFADDER(A, B, SUM, CARRY);

input A;

input B;

output SUM;

output CARRY;

reg SUM;

reg CARRY;

always @ (A , B)

begin

SUM = A^B;

CARRY = A & B;

end

endmodule

RESULT

Inputs Outputs

A B Sum(S) Carry(C)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

WAVE FORM

8 c). VHDL CODE FOR FULL ADDER USING COMPONENT INSTANTIATION METHOD.

ENTITY FULLADDER IS


B : IN STD_LOGIC;

C : IN STD_LOGIC;

CARRY : OUT STD_LOGIC;

HA1

HA2

A

B

C

SUM

CARRY

Temp1

HDL LAB (06ECL48)


SUM : OUT STD_LOGIC);

END FULLADDER;

ARCHITECTURE BEHAVIORAL OF FULLADDER IS

COMPONENT HALFADDER


B : IN STD_LOGIC;

SUM : OUT STD_LOGIC;

CARRY : OUT STD_LOGIC);

END COMPONENT;

SIGNAL TEMP1,TEMP2, TEMP3: STD_LOGIC;

BEGIN

L1: HALFADDER PORT MAP( A, B,TEMP1,TEMP2);

L2: HALFADDER PORT MAP( TEMP1,C,SUM,TEMP3);

CARRY <= TEMP2 OR TEMP3;

END BEHAVIORAL;

8 d). VERILOG CODE FOR FULL ADDER USING TWO HALF ADDER.

module FULL_2HA(A, B, C, SUM, CARRY);

input A;

input B;

input C;

output SUM;

output CARRY;

wire S1,T1,T2;

xor

X1(S1,A,B),

X2(SUM,S1,C);

and

A1(T1,S1,C),

A2(T2,A,B);

or

O1(CARRY,T1,T2);

endmodule

8 e).VHDL CODE FOR FULLADDER

ENTITY FA IS

PORT (A,B,C:IN BIT;

SUM,CARRY:OUT BIT);

END FA;

ARCHITECTURE FA_ARCH OF FA IS

BEGIN

SUM <= A EXOR B EXOR C;

HDL LAB (06ECL48)


CARRY<=(A AND B )OR (B AND C) OR (C AND A);

END FA_ARCH;

Exercise: Write VHDL code in behaviour style

8 f). VERILOG CODE FOR FULL ADDER.

module FULLADDER(A, B, C, SUM, CARRY);

input A;

input B;

input C;

output SUM;

output CARRY;

reg SUM,CARRY;

reg T1, T2, T3;

always @ (A , B , C)

begin

SUM=A^B^C;

T1=A&B;

T2=B&C;

T3=C&A;

CARRY=(T1| T2) | T3;

end

endmodule

RESULT:-

Inputs Outputs

A B C Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

WAVEFORM

9 a). VHDL CODE FOR 8 BIT ALU MODEL. (16)

ENTITY ALU IS

PORT ( A,B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

OPCODE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

ENB : IN STD_LOGIC; -- ENABLE SIGNAL

OP : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

OPM : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));

HDL LAB (06ECL48)


END ALU;

ARCHITECTURE BEHAVIORAL OF ALU IS

BEGIN

PROCESS(A,B,OPCODE,ENB)

BEGIN

IF ENB= '1' THEN

CASE OPCODE IS

WHEN "000" => OP<= A+B;

WHEN "001" => OP<= A-B;

WHEN "010" => OP<= NOT A;

WHEN "011" => OPM<= A*B;

WHEN "100" => OP<= A AND B;

WHEN "101" => OP<= A OR B;

WHEN "110" => OP<= A NAND B;

WHEN OTHERS => OP<= A XOR B;

END CASE;

ELSE

OP <= (OTHERS =>'Z');

END IF;

END PROCESS;

END BEHAVIORAL;

9 b). VERILOG CODE FOR 8-BIT ALU MODEL. (16 BIT)

module ALU(A, B, SEL,EN,Y,Z);

input [7:0] A, B;

input EN;

input [2:0] SEL;

output [7:0] Y;

output [15:0] Z;

reg [7:0]Y; reg [15:0]Z;

always @(A ,B , SEL)

begin

if (EN==1)

begin

case (SEL)

3'b000:Y=A+B;

3'b001:Y=A-B;

3'b010:Y=~A;

3'b011:Z=A*B;

3'b100:Y=A&B;

3'b101:Y=A|B;

3'b110:Y=~(A|B);

3'b111:Y=A^B;

endcase

end

end

endmodule

10 a). VHDL CODE FOR S R F/F.

ENTITY SRFF IS

PORT (

S: IN BIT; -- S BIT INPUT

R: IN BIT; -- R BIT INPUT

CLK: IN BIT; -- GLOBAL CLOCK

Q: BUFFER STD_LOGIC );

S-R

FLIP-FLOP

S

CLK

R

Q

QBAR

RST

HDL LAB (06ECL48)


END SRFF;

ARCHITECTURE S_R_FF_ARCH OF SRFF IS

BEGIN

PROCESS(CLK)

BEGIN

IF CLK='1' AND CLK'EVENT THEN

IF(S='0' AND R='0')THEN Q<=Q;

ELSIF(S='0' AND R='1')THEN Q<='0';

ELSIF(S='1' AND R='0')THEN Q<='1';

ELSIF (S='1' AND R='1')THEN Q<='X';

END IF;

END IF;

END PROCESS;

END S_R_FF_ARCH;

10 b). VERILOG CODE FOR SR F/F

module sr_ff(s ,r ,clk , rst , q , qbar);

input s;

input r;

input clk;

input rst;

output q;

output qbar;

reg q,qbar;

always@(posedge clk ,rst , s , r)

begin

if(rst==0)

begin

q=0;

qbar=1;

end

else

begin

if(s==0&&r==0)

begin

q=q;

qbar=qbar;

end

if(s==1&&r==0)

begin

q=1;

qbar=0;

end

if(s==0&&r==1)

begin

q=0;

qbar=1;

end

if (s==1&&r==1)

begin

q=1'bx;

qbar=1'bx;

end

end

end

HDL LAB (06ECL48)


endmodule

RESULT:

INPUTS OUTPUTS

RST S R Q QBAR

0 0 1

1 0 0 0 1

1 0 1 0 1

1 1 0 1 0

1 1 1 ?

WAVEFORM

11 a). VHDL CODE FOR D F/F.

ENTITY DFF IS

PORT (CLK: IN STD_LOGIC;

D: IN STD_LOGIC;

Q: OUT STD_LOGIC );

END DFF;

ARCHITECTURE D_FF_ARCH OF DFF IS

D

FLIP-FLOP

D

CLK

RST

Q

QBAR

HDL LAB (06ECL48)


BEGIN

PROCESS(CLK)

BEGIN

IF(CLK'EVENT AND CLK='1')THEN

Q<=D;

END IF;

END PROCESS;

END D_FF_ARCH;

11 b). VERILOG CODE FOR D-FLIPFLOP.

module D_FF(D, RESET, CLK, Q, QBAR);

input D;

input RESET;

input CLK;

output Q,QBAR;

reg Q,QBAR;

always@(posedge CLK , posedge RESET)

begin

if (RESET==0)

begin

Q=0;

QBAR=1;

end

else

begin

Q=D;

QBAR=~D;

end

end

endmodule

RESULT:-

RESET D Q QBAR

0 0 1

1 0 0 1

1 1 1 0

WAVEFORM

12 a). VHDL CODE FOR JK F/F .

ENTITY JKFF IS

PORT (

CLK : IN BIT; .

J : IN BIT; .

K : IN BIT;

RESET :IN BIT;

Q : BUFFER BIT );

J-K

FLIP-FLOP

J

CLK

K

Q

QBAR

RST

HDL LAB (06ECL48)


END JKFF;

ARCHITECTURE JKFF_ARCH OF JKFF IS

BEGIN

PROCESS(CLK,RESET)

BEGIN

IF(RESET='1')THEN

Q<='0';

ELSIF(CLK'EVENT AND CLK='1')THEN

IF(J='0' AND K='0') THEN

Q<=Q;

ELSIF(J='0' AND K='1') THEN

Q<='0';


Q<='1';


Q<=NOT Q;

END IF;

END IF;

END PROCESS;

END JKFF_ARCH;

12 b). VERILOG CODE FOR JK-FLIPFLOP.

module JK_FF(J, K, CLK, RESET, Q, QBAR);

input J;

input K;

input CLK;

input RESET;

output Q;

output QBAR;

reg Q, QBAR;

always @ (posedge CLK , posedge RESET)

begin

if(RESET==0)

begin

Q=0;

QBAR=1;

end

else if (J==0 && K==0)

begin

Q=Q;

QBAR=QBAR;

end

else if (J==0 && K==1)

begin

Q=0;

QBAR=1;

end

else if (J==1 && K==0)

begin

Q=1;

QBAR=0;

end

else

begin

Q=~Q;

HDL LAB (06ECL48)


QBAR=~QBAR;

end

end

endmodule

RESULT:-

RESET J K Q QBAR

0 0 1

1 0 0 0 1

1 0 1 0 1

1 1 0 1 0

1 1 1 TOOGLE

WAVEFORM

13 a). VHDL CODE FOR T F/F.

ENTITY TFF IS

PORT ( T,RST: IN STD_LOGIC; -- INPUT T

CLK: IN STD_LOGIC; -- GLOBAL CLOCK SIGNAL

Q: INOUT STD_LOGIC ); -- Q OUTPUT

END TFF;

ARCHITECTURE T_FF_ARCH OF TFF IS

BEGIN

HDL LAB (06ECL48)


PROCESS(CLK)

BEGIN

IF(CLK'EVENT AND CLK='1')THEN

IF RST=’1’ THEN

Q<=’0’;

ELSE

IF (T=’0’) THEN

Q<=Q;

ELSE

Q<= NOT Q;

END IF;

END IF;

END IF;

END PROCESS;

END T_FF_ARCH;

13 b). VERILOG CODE FOR T-FLIPFLOP.

module T_FF(T, CLK, RESET, Q, QBAR);

input T, CLK,RESET;

output Q, QBAR;

reg Q,QBAR;

always @ (posedge CLK or RESET)

begin

if (RESET==1)

begin

Q=0;

QBAR=1;

end

else if (T==0) RESULT:

begin

Q=Q;

QBAR=QBAR;

end

else

begin

Q=~Q;

QBAR=~QBAR;

end

end

endmodule

WAVE FORM

14 a). VHDL CODE FOR 4-BIT SYNCHRONOUS COUNTER

ENTITY SYNC_COUNTER IS

PORT ( CLK : IN STD_LOGIC;

RESET : IN STD_LOGIC;

COUNT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END SYNC_COUNTER;

RESET T Q QBAR

1 X 0 1

0 0 0 1

0 1 TOGGLE

T

FLIP-FLOP

T

CLK

RST

Q

QBAR

HDL LAB (06ECL48)


ARCHITECTURE BEHAVIORAL OF SYNC_COUNTER IS

SIGNAL TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

PROCESS(CLK)

BEGIN


IF (RESET='1' )THEN --SYNCRONOUS RESET

TEMP<="0000";--RESET COUNT

ELSE

TEMP<=TEMP+1;

END IF;

END IF;

END PROCESS;

COUNT<=TEMP;

END BEHAVIORAL;

14 b). A VHDL CODE FOR 4-BIT SYNCHRONOUS COUNTER.(FOR HARDWARE

IMPLEMENTATION)

ENTITY SYNC_COUNTER IS

PORT( CLK: IN STD_LOGIC;

RESET: IN STD_LOGIC;

COUNT: OUT

STD_LOGIC_VECTOR( 3 DOWNTO 0));

END SYNC_COUNTER;

ARCHITECTURE COUNTER_ARCH OF SYNC_COUNTER IS

SIGNAL TEMP:STD_LOGIC_VECTOR( 3 DOWNTO 0);

SIGNAL DCLK:STD_LOGIC_VECTOR(20

DOWNTO 0);

BEGIN

PROCESS(CLK)

BEGIN

IF RISING_EDGE(CLK) THEN

DCLK<=DCLK+’1’;

END IF;

END PROCESS;

PROCESS (DCLK(18))

BEGIN

IF DCLK(18)='1' AND DCLK(18)'EVENT THEN

IF RESET='1' THEN –SYNCHRONOUS RESET

TEMP <= (OTHERS=>'0');

ELSE

TEMP <= TEMP + 1;

END IF;

END IF;

COUNT<= TEMP;

END PROCESS;

END COUNTER_ARCH;

14 c). VERILOG CODE FOR 4 BIT SYNCHRONOUS COUNTER

module sync2(clk, reset, count);

input clk;

input reset;

output [3:0] count;

reg[3:0]count;

HDL LAB (06ECL48)


always@(posedge clk , posedge reset)

begin

if(reset==1)

count=4'b0000;

else

count=count+1;

end

endmodule

14 d). VERILOG CODE FOR 4 BIT SYNCHRONOUS COUNTER.(FOR HARDWARE IMPLEMENTATION

module counter(clk, reset, count);

input clk;

input reset;

output [3:0] count;

reg[3:0] count;

integer timer_count1 = 0,timer_count2 = 0;

reg clk_msec,clk_sec;

always@(posedge clk)

begin

if(timer_count1==3999)

begin

timer_count1=0;

clk_msec=1'b1;

end

else

begin

timer_count1=timer_count1+1;

clk_msec=1'b0;

end

end

always@(posedge clk_msec)

begin

if(timer_count2==999)

begin

timer_count2=0;

clk_sec=1'b1;

end

else

begin

timer_count2=timer_count2+1;

clk_sec=1'b0;

end

end

always@(posedge clk_sec)

begin

if(~reset)

count = 4'b0000;

else

count = count+1;

end

endmodule

RESULT:-

Clock Q3 Q2 Q1 Q0

HDL LAB (06ECL48)


WAVEFORM

15 a). VHDL CODE FOR 4-BIT ASYNCHRONOUS BINARY COUNTER

ENTITY ASYNC_C IS




END ASYNC_C;

ARCHITECTURE BEHAVIORAL OF ASYNC_C IS


BEGIN

PROCESS(CLK,RESET)

BEGIN

IF RESET='1' THEN --ASYNCHRONOUS RESET

TEMP<=(OTHERS=>'0');

ELSIF CLK='1' AND CLK'EVENT THEN

TEMP<=TEMP+1;

END IF;

END PROCESS;

COUNT<=TEMP;

END BEHAVIORAL;

15 b). 4-BIT ASYNCHRONOUS BINARY COUNTER.(FOR HARDWARE IMPLEMENTATION)

LIBRARY IEEE;




ENTITY ASYNC_COUNTER IS

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

HDL LAB (06ECL48)


PORT( CLK: IN STD_LOGIC;

RESET: IN STD_LOGIC;

COUNT: OUT STD_LOGIC_VECTOR( 3 DOWNTO 0));

END ASYNC_COUNTER;

ARCHITECTURE COUNTER_ARCH OF ASYNC_COUNTER IS

SIGNAL DIV:STD_LOGIC_VECTOR(22 DOWNTO 0);

SIGNAL CLKDIV:STD_LOGIC;

BEGIN

PROCESS (CLK)--CLKDIVIDE

BEGIN


DIV<=DIV+1;

ENDIF;

END PROCESS;

CLKDIV<=DIV(22);

PROCESS(CLKDIV,RESET)

BEGIN

IF RESET='1' THEN

COUNT <= “0000”;

ELSIF (CLKDIV='1' AND CLKDIV' EVENT) THEN

COUNT <= COUNT + 1;

END IF;

END PROCESS;

END COUNTER_ARCH;

15 c). VERILOG CODE FOR ASYNCHRONOUS COUNTER

module synk(clk, reset, count);

input clk;

input reset;

output [3:0] count;

reg [3:0]count;


begin

if(reset==1)

count=4'b0000;

else

count=count+1;

end

endmodule

15 d). VERILOG CODE FOR 4-BIT ASYNCHRONOUS BINARY COUNTER.(FOR HARDWARE

IMPLEMENTATION)

------- ASSIGNMENT--------

RESULT:-

Clock Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

HDL LAB (06ECL48)


4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

16 a). VHDL CODE FOR 4-bit synchronous BCD counter ENTITY SYNC_COUNTER IS




END SYNC_COUNTER;

ARCHITECTURE BEHAVIORAL OF SYNC_COUNTER IS


BEGIN

PROCESS(CLK)

BEGIN


IF (RESET='1' OR TEMP =”1010” )THEN --SYNCRONOUS RESET

TEMP<="0000";--RESET COUNT

ELSE

TEMP<=TEMP+1;

END IF;

END IF;

END PROCESS;

COUNT<=TEMP;

END BEHAVIORAL;

16 b).VHDL CODE FOR 4-bit synchronous BCD counter.(FOR HARDWARE IMPLEMENTATION)

entity sync_counter is

port( CLK: in STD_LOGIC; -- GLOBAL CLOCK SIGNAL

RESET: in STD_LOGIC; -- Global Reset Signal

COUNT: out STD_LOGIC_VECTOR( 3 DOWNTO 0)); --Counter Output

end sync_counter;

architecture counter_arch of sync_counter is

HDL LAB (06ECL48)


begin

process (CLK)

begin

if CLK='1' and CLK'event then

if (RESET='1' or COUNT=”1010”) then --Synchronous reset

COUNT <= “0000”; --set intial value of COUNT for any sequence counter

ELSE

COUNT <= COUNT + 1;

end if;

end if;

end process;

end counter_arch;

16 c).verilog CODE FOR 4-bit synchronous BCD counter. module bcd (clk, reset, count);

input clk, reset;

output [3:0] count;

reg[3:0]count;


begin

if(reset==1 | count==4'b1010)

begin

count=4'b0000;

end

else

count=count+1;

end

endmodule

16 d).verilog CODE FOR 4-bit synchronous BCD counter(FOR HARDWARE

IMPLEMENTATION)

----- ASSIGNMENT------

RESULT:

INTERFACING

--Package for LCD Display (This Package must be added to display all the messages on

LCD)

-- Package File Template

-- Purpose: This package defines supplemental types, subtypes, constants, and functions

library IEEE;

Clock Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 0 0 0 0

HDL LAB (06ECL48)


use IEEE.STD_LOGIC_1164.all;

package LCD_GRAP is

-- THE NUMBERS

constant ONE : std_logic_vector(7 downto 0) := "00110001";

constant TWO : std_logic_vector(7 downto 0) := "00110010";

constant THREE : std_logic_vector(7 downto 0) := "00110011";

constant FOUR : std_logic_vector(7 downto 0) := "00110100";

constant FIVE : std_logic_vector(7 downto 0) := "00110101";

constant SIX : std_logic_vector(7 downto 0) := "00110110";

constant SEVEN : std_logic_vector(7 downto 0) := "00110111";

constant EIGHT : std_logic_vector(7 downto 0) := "00111000";

constant NINE : std_logic_vector(7 downto 0) := "00111001";

constant ZERO : std_logic_vector(7 downto 0) := "00110000";

-- THE CHARACTERS

constant A : std_logic_vector(7 downto 0) := "01000001";

constant B : std_logic_vector(7 downto 0) := "01000010";

constant C : std_logic_vector(7 downto 0) := "01000011";

constant D : std_logic_vector(7 downto 0) := "01000100";

constant E : std_logic_vector(7 downto 0) := "01000101";

constant F : std_logic_vector(7 downto 0) := "01000110";

constant G : std_logic_vector(7 downto 0) := "01000111";

constant H : std_logic_vector(7 downto 0) := "01001000";

constant I : std_logic_vector(7 downto 0) := "01001001";

constant J : std_logic_vector(7 downto 0) := "01001010";

constant K : std_logic_vector(7 downto 0) := "01001011";

constant L : std_logic_vector(7 downto 0) := "01001100";

constant M : std_logic_vector(7 downto 0) := "01001101";

constant N : std_logic_vector(7 downto 0) := "01001110";

constant O : std_logic_vector(7 downto 0) := "01001111";

constant P : std_logic_vector(7 downto 0) := "01010000";

constant Q: std_logic_vector(7 downto 0) := "01010001";

constant R : std_logic_vector(7 downto 0) := "01010010";

constant S : std_logic_vector(7 downto 0) := "01010011";

constant T : std_logic_vector(7 downto 0) := "01010100";

constant U : std_logic_vector(7 downto 0) := "01010101";

constant V : std_logic_vector(7 downto 0) := "01010110";

constant W : std_logic_vector(7 downto 0) := "01010111";

constant X : std_logic_vector(7 downto 0) := "01011000";

constant Y : std_logic_vector(7 downto 0) := "01011001";

constant Z : std_logic_vector(7 downto 0) := "01011010";

-- SMAL LETTERS

constant SA : std_logic_vector(7 downto 0) := "01100001";

constant SB : std_logic_vector(7 downto 0) := "01100010";

constant SC : std_logic_vector(7 downto 0) := "01100011";

constant SD : std_logic_vector(7 downto 0) := "01100100";

HDL LAB (06ECL48)


constant SE : std_logic_vector(7 downto 0) := "01100101";

constant SF : std_logic_vector(7 downto 0) := "01100110";

constant SG : std_logic_vector(7 downto 0) := "01100111";

constant SH : std_logic_vector(7 downto 0) := "01101000";

constant SI : std_logic_vector(7 downto 0) := "01101001";

constant SJ : std_logic_vector(7 downto 0) := "01101010";

constant SK : std_logic_vector(7 downto 0) := "01101011";

constant SL : std_logic_vector(7 downto 0) := "01101100";

constant SM : std_logic_vector(7 downto 0) := "01101101";

constant SN : std_logic_vector(7 downto 0) := "01101110";

constant SO : std_logic_vector(7 downto 0) := "01101111";

constant SP : std_logic_vector(7 downto 0) := "01110000";

constant SQ : std_logic_vector(7 downto 0) := "01110001";

constant SR : std_logic_vector(7 downto 0) := "01110010";

constant SS : std_logic_vector(7 downto 0) := "01110011";

constant ST : std_logic_vector(7 downto 0) := "01110100";

constant SU : std_logic_vector(7 downto 0) := "01110101";

constant SV : std_logic_vector(7 downto 0) := "01110110";

constant SW : std_logic_vector(7 downto 0) := "01110111";

constant SX : std_logic_vector(7 downto 0) := "01111000";

constant SY : std_logic_vector(7 downto 0) := "01111001";

constant SZ : std_logic_vector(7 downto 0) := "01111010";

---THE SYMBOLS

constant SPACE: std_logic_vector(7 downto 0) := "00100000";

constant SLASH: std_logic_vector(7 downto 0) := "00101111";

constant MINUS: std_logic_vector(7 downto 0) := "00101101";

constant EQUAL: std_logic_vector(7 downto 0) := "00111101";

constant PLUS : std_logic_vector(7 downto 0) := "00101011";

constant STAR : std_logic_vector(7 downto 0) := "00101010";

constant DOT : std_logic_vector(7 downto 0) := "00101110";

end LCD_GRAP;

1a.WRITE VHDL CODE TO DISPLAY MESSAGES ON THE GIVEN LCD ACCEPTING HEX KEY

PAD INPUT DATA.

AIM: TO DISPLAY THE MESSAGE ON THE LCD PANEL BY ACCEPTING HEX KEY BOARD DATA AS

INPUT.

PROCEDURE:

1. Make the connection between FRC5 of the FPGA board to the LCD display Connector of the VTU card1.

2. Make the connection between FRC 4 of the FPGA board to the keyboard Connector of the VTU card1.

3. Make the connection between FRC 6 of the FPGA board to the dipswitch Connector of the VTU card1.

4. Connect the downloading cable and power supply to the FPGA board

HDL LAB (06ECL48)


5. Then open the xilinx impact software (refer ISE flow) select the slave Serial mode and select the respective

bit file and click program.

6. Make the reset switch on (active low).

7. Press the hex keys and analyze the data.

VHDL CODE

LIBRARY IEEE;



USE WORK.LCD_GRAP.ALL;

ENTITY HEXKEY_LCD IS

PORT (

CLK: IN STD_LOGIC; -- 16 MHZ CLOCK

RESET: IN STD_LOGIC; -- MASTER RESET PIN

LCD_RW : OUT STD_LOGIC;

LCD_SELECT : OUT STD_LOGIC;

LCD_ENABLE : OUT STD_LOGIC;

ROW: IN STD_LOGIC_VECTOR(0 TO 3); -- THIS ARE THE ROW LINES

LCD_DATA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- GIVES REGISTERED DATA OUTPUT

COL: INOUT STD_LOGIC_VECTOR(0 TO 3));

END HEXKEY_LCD;

ARCHITECTURE HEXKEY_BEH OF HEXKEY_LCD IS

TYPE KEYPAD_STATE_TYPE IS (WAIT_R_0, C3, C2, C1, C0, FOUND, SAMPLE, WAIT_R_1); --

STATE NAMES

TYPE STATE_TYPE IS (INITIAL,DISPLAY,CLEAR,LOCATION,PUTCHAR);

SIGNAL STATE,NEXT_STATE: STATE_TYPE;

-- CLEAR SCREEN.

CONSTANT CLR: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000001";

-- DISPLAY ON, WITHOUT CURSOR.

CONSTANT DON: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00001100";

-- FUNCTION SET FOR 8-BIT DATA TRANSFER AND 2-LINE DISPLAY

CONSTANT SET: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00111000";

--FREQUENCY DIVIDER

CONSTANT BIG_DELAY: INTEGER :=16;

CONSTANT SMALL_DELAY: INTEGER :=2;

CONSTANT REG_SETUP: INTEGER :=1;

SIGNAL CS, NS: KEYPAD_STATE_TYPE; -- SIGNALS FOR CURRENT AND NEXT STATES

SIGNAL DIV_REG: STD_LOGIC_VECTOR (16 DOWNTO 0); -- CLOCK DIVIDE REGISTER

SIGNAL DCLK,DDCLK: STD_LOGIC; -- THIS HAS THE DIVIDED CLOCK.

SIGNAL COL_REG_VALUE: STD_LOGIC_VECTOR (0 TO 3);

SIGNAL R1: STD_LOGIC; -- ROW DETECTION SIGNAL

SIGNAL KEY_VALUE: STD_LOGIC_VECTOR (7 DOWNTO 0);

SIGNAL DATA: STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN

R1 <= ROW(3) OR ROW(2) OR ROW(1) OR ROW(0);

---------------------------- BEGINING OF FSM1 (KEYPAD SCANNER) -------------------------------

SYNC_PROC: PROCESS (DCLK, RESET, KEY_VALUE) -- THIS IS THE SYNCHRONOUS PART

BEGIN

IF (RESET = '0') THEN -- YOU MUST HAVE A RESET FOR FSM TO SYNTHESIZE PROPERLY

CS <= WAIT_R_0;

ELSIF (DCLK'EVENT AND DCLK = '1') THEN

CS <= NS;

END IF;

END PROCESS;

COMB_PROC: PROCESS (CS, R1, COL_REG_VALUE) -- THIS IS THE COMBINATIONAL PART

HDL LAB (06ECL48)


BEGIN

CASE CS IS

---------------------------------------------------------------------------------------------------

WHEN WAIT_R_0 => -- WAITS TILL A BUTTON IS PRESSED

COL <= "1111"; -- KEEP ALL COLUMNS ACTIVATED

IF R1 = '1' THEN -- A BUTTON WAS PRESSED. BUT WHICH ONE?

NS <= C3; -- LET'S FIND OUT

ELSE

NS <= WAIT_R_0;

END IF;

---------------------------------------------------------------------------------------------------

WHEN C3 => --

COL <= "0001"; -- ACTIVATE COLUMN 3

IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 3

NS <= C2; -- SO CHECK IF IT WAS IN COLUMN 2

ELSE NS <= FOUND; -- BUTTON WAS IN COLUMN 3

END IF;

---------------------------------------------------------------------------------------------------

WHEN C2 => --




ELSE

NS <= FOUND; -- BUTTON WAS IN COLUMN 2

END IF;

---------------------------------------------------------------------------------------------------

WHEN C1 => --




ELSE


END IF;

---------------------------------------------------------------------------------------------------

WHEN C0 => --


IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 0 ??

NS <= WAIT_R_0; -- SO THE BUTTON MUST HAVE BEEN DEPRESSED FAST

ELSE


END IF;

---------------------------------------------------------------------------------------------------

WHEN FOUND => --

COL <= COL_REG_VALUE;

IF R1 = '0' THEN -- THIS MEANS BUTTON IS DEPRESSED

NS <= WAIT_R_0; -- SO GO BACK TO INITIAL STATE

ELSE

NS <= SAMPLE; -- OTHERWISE WRITE THE KEY VALUE TO DATA REGISTER

END IF;

---------------------------------------------------------------------------------------------------

WHEN SAMPLE => -- THIS STATE WILL GENERATE A SIGNAL WITH ONE CLOCK PERIOD FOR

SAMPLING


NS <= WAIT_R_1; -- OTHERWISE WAIT TILL BUTTON IS PRESSED

---------------------------------------------------------------------------------------------------

WHEN WAIT_R_1 => --

HDL LAB (06ECL48)



IF R1 = '0' THEN -- THIS MEANS BUTTON WAS DEPRESSED


ELSE


END IF;

---------------------------------------------------------------------------------------------------

END CASE;

END PROCESS;

---------------------------------------------------------------------------------------------------

WRITE_DATA: PROCESS (DCLK, CS, KEY_VALUE) -- WRITE VALID DATA TO REGISTER

BEGIN

IF DCLK'EVENT AND DCLK = '0' THEN -- ON THE FALLING EDGE

IF CS = FOUND THEN

DATA <= KEY_VALUE;

END IF;

END IF;

END PROCESS; -- WRITE_DATA

---------------------------------------------------------------------------------------------------

COL_REG: PROCESS (DCLK, CS, COL) -- THIS IS THE COLUMN VALUE REGISTER

BEGIN

IF (DCLK'EVENT AND DCLK = '0') THEN -- REGISTER THE COL VALUE ON THE FALLING EDGE

IF (CS = C3 OR CS = C2 OR CS = C1 OR CS = C0) THEN -- PROVIDED WE'RE IN STATES C3 THRU C0

ONLY

COL_REG_VALUE <= COL; -- OTHERWISE THE COLUMN VALUE IS NOT VALID

END IF;

END IF;

END PROCESS; -- COL_REG

---------------------------------------------------------------------------------------------------

DECODER: PROCESS(ROW, COL_REG_VALUE) -- DECODES BINARY VALUE OF PRESSED KEY

FROM ROW AND

COLUMN

VARIABLE CODE: STD_LOGIC_VECTOR (0 TO 7);

BEGIN

CODE := (ROW & COL_REG_VALUE);

CASE CODE IS

-- COL

-- ROW 0 0123

WHEN "00010001" => KEY_VALUE <= ZERO;--KEY 0

WHEN "00010010" => KEY_VALUE <= ONE;--KEY 1

WHEN "00010100" => KEY_VALUE <= TWO;--KEY 2

WHEN "00011000" => KEY_VALUE <= THREE;--KEY 3

-- ROW 1

WHEN "00100001" => KEY_VALUE <= FOUR;--KEY 4

WHEN "00100010" => KEY_VALUE <= FIVE;--KEY 5

WHEN "00100100" => KEY_VALUE <= SIX;--KEY 6

WHEN "00101000" => KEY_VALUE <= SEVEN;--KEY 7

-- ROW 2

WHEN "01000001" => KEY_VALUE <= EIGHT;--KEY 8

WHEN "01000010" => KEY_VALUE <= NINE;--KEY 9

WHEN "01000100" => KEY_VALUE <= A;--KEY A

WHEN "01001000" => KEY_VALUE <= B;--KEY B

-- ROW 3

WHEN "10000001" => KEY_VALUE <= C;--KEY C

WHEN "10000010" => KEY_VALUE <= D;--KEY D

WHEN "10000100" => KEY_VALUE <= E;--KEY E

HDL LAB (06ECL48)


WHEN "10001000" => KEY_VALUE <= F;--KEY F

WHEN OTHERS => KEY_VALUE <= SPACE; -- JUST IN CASE

END CASE;

END PROCESS; -- DECODER

---------------------------- END OF FSM1 (KEYPAD SCANNER) ---------------------------------------

-- SELECT THE APPROPRIATE LINES FOR SETTING FREQUENCY

CLK_DIV: PROCESS (CLK, DIV_REG) -- CLOCK DIVIDER

BEGIN

IF (CLK'EVENT AND CLK='1') THEN

DIV_REG <= DIV_REG + 1;

END IF;

END PROCESS;

DCLK <= DIV_REG(8);

DDCLK<=DIV_REG(10);

---------------------------- END OF CLOCK DIVIDER -------------------------------------------------

LCD_RW<='0';

PROCESS (DDCLK,RESET)

VARIABLE COUNT: INTEGER RANGE 0 TO BIG_DELAY;

VARIABLE C1 : STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

IF RESET = '0' THEN

STATE<=INITIAL;

COUNT:=0;

LCD_ENABLE<='0';

LCD_SELECT<='0';

C1 := "01111111";

ELSIF DDCLK'EVENT AND DDCLK = '1' THEN

CASE STATE IS

WHEN INITIAL => -- TO SET THE FUNCTION

IF COUNT=REG_SETUP THEN

LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

LCD_DATA<=SET;

LCD_SELECT<='0';

IF COUNT=SMALL_DELAY THEN

STATE<=DISPLAY;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;

WHEN DISPLAY => -- TO SET DISPLAY ON


LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

LCD_DATA<=DON;

LCD_SELECT<='0';


STATE<=CLEAR;COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;

WHEN CLEAR => -- CLEAR THE SCREEN

HDL LAB (06ECL48)



LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

LCD_DATA<=CLR;

LCD_SELECT<='0';

IF COUNT=BIG_DELAY THEN

STATE<=LOCATION;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;

WHEN LOCATION => -- CLEAR THE SCREEN


LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

IF COUNT=0 THEN

IF C1="10001111" THEN

C1:="11000000";

ELSIF C1="11001111" THEN

C1:="10000000";

ELSE

C1:=C1+'1';

END IF;

END IF;

LCD_DATA <= C1 ;

LCD_SELECT<='0';


STATE<=PUTCHAR;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;

WHEN PUTCHAR=> -- DISPLAY THE CHARACTER ON THE LCD


LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

CASE C1 IS

WHEN "10000000" => LCD_DATA<= H ;--SIGLE LINE

WHEN "10000001" => LCD_DATA<= E ;--SIGLE LINE

WHEN "10000010" => LCD_DATA<= X ;--SIGLE LINE

WHEN "10000011" => LCD_DATA<= SPACE ;--SIGLE LINE


WHEN "10000101" => LCD_DATA<= K ;--SIGLE LINE


WHEN "10000111" => LCD_DATA<= Y ;--SIGLE LINE

WHEN "10001000" => LCD_DATA<= B ;

WHEN "10001001" => LCD_DATA<= O ;

WHEN "10001010" => LCD_DATA<= A ;

WHEN "10001011" => LCD_DATA<= R ;

WHEN "10001100" => LCD_DATA<= D ;

HDL LAB (06ECL48)


WHEN "10001101" => LCD_DATA<= SPACE ;


WHEN "10001111" => LCD_DATA<= SPACE;

WHEN "11000000" => LCD_DATA<= K ;--SIGLE LINE


WHEN "11000010" => LCD_DATA<= Y ;--SIGLE LINE

WHEN "11000011" => LCD_DATA<= P ;--SIGLE LINE

WHEN "11000100" => LCD_DATA<= R ;--SIGLE LINE


WHEN "11000110" => LCD_DATA<= S ;--SIGLE LINE


WHEN "11001000" => LCD_DATA<= E ;

WHEN "11001001" => LCD_DATA<= D ;


-- WHEN "11001011" => LCD_DATA<= RIGHT_ARROW ;


WHEN "11001101" => LCD_DATA<= DATA ;




END CASE ;

LCD_SELECT<='1';


STATE<=LOCATION;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;

END CASE;

END IF;

END PROCESS;

END HEXKEY_BEH;

===============================================================


NET "CLK" LOC = "P52" ;

NET "COL<0>" LOC = "P139" ;

NET "COL<1>" LOC = "P134" ;

NET "COL<2>" LOC = "P136" ;

NET "COL<3>" LOC = "P132" ;

NET "LCD_DATA<0>" LOC = "P21" ;





HDL LAB (06ECL48)





NET "LCD_ENABLE" LOC = "P19" ;

NET "LCD_RW" LOC = "P20" ;

NET "LCD_SELECT" LOC = "P4" ;

NET "RESET" LOC = "P41" ;

NET "ROW<0>" LOC = "P126" ;

NET "ROW<1>" LOC = "P129" ;

NET "ROW<2>" LOC = "P124" ;

NET "ROW<3>" LOC = "P122" ;

===============================================================

1b. WRITE VHDL CODE TO DISPLAY MESSAGES ON THE GIVEN SEVEN SEGMENT DISPLAY

ACCEPTING HEX KEY PAD INPUT DATA.

AIM: TO DISPLAY THE MESSAGE ON THE SEVEN SEGMENT DISPLAY BY ACCEPTING HEX KEY PAD

INPUT

DATA.

PROCEDURE:

1. Make the connection between FRC5 of the FPGA board to the seven-segment connector of the VTUcard1.

2. Make the connection between FRC 4 of the FPGA board to the keyboard connector of the VTU card1.

3. Make the connection between FRC 6 of the FPGA board to the dipswitch connector of the VTU card1.

4. Connect the downloading cable and power supply to the fpga board.

5. Then open the xilinx impact software (refer ISE flow) select the slave serial mode and select the respective


HDL LAB (06ECL48)




VHDL CODING

------------------------------------

--CODE FOR SIMULATING 16 KEYS USING

--KEYBOARD PROVIDED ON SPARTAN BOARD

------------------------------------

LIBRARY IEEE;




ENTITY KEY IS

PORT ( COLUMN : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0)=”0001”;

ROW_READ : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

CLK : IN STD_LOGIC;

DISP_SELECT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

SEVEN_SEG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));

END KEY;

ARCHITECTURE BEHAVIORAL OF KEY IS

BEGIN

---------------------------

--CLOCK DIVISION TO 4KHZ

--------------------------

PROCESS(CLK)

BEGIN


COLUMN <=COLUMN(2 DOWNTO 0)& COLUMN (3); --SHIFTING

END IF;

END PROCESS;

DISP_SELECT <=”1110”; ----TO SELECT DISPLAY

PROCESS(ROW_READ,COLUMN)

BEGIN

CASE COLUMN IS

WHEN "0001" => CASE ROW_READ IS

WHEN "0001" => SEVEN_SEG <= "1111110";

WHEN "0010" => SEVEN_SEG <= "0110011";

WHEN "0100" => SEVEN_SEG <= "1111111";

WHEN "1000" => SEVEN_SEG <= "1001110";

WHEN OTHERS=> SEVEN_SEG <= "0000000";

END CASE;


WHEN "0001" => SEVEN_SEG <= "0110000";

WHEN "0010" => SEVEN_SEG <= "1011011";

WHEN "0100" => SEVEN_SEG <= "1111011";

WHEN "1000" => SEVEN_SEG <= "0111101";


END CASE;


WHEN "0001" => SEVEN_SEG <= "1101101";

WHEN "0010" => SEVEN_SEG <= "1011111";

WHEN "0100" => SEVEN_SEG <= "1110111";

WHEN "1000" => SEVEN_SEG <= "1001111";


END CASE;


HDL LAB (06ECL48)


WHEN "0001" => SEVEN_SEG <= "1111001";

WHEN "0010" => SEVEN_SEG <= "1110000";

WHEN "0100" => SEVEN_SEG <= "0011111";

WHEN "1000" => SEVEN_SEG <= "1000111";


END CASE;

WHEN OTHERS=> NULL;

END CASE;

END PROCESS;

END BEHAVIORAL;

===============================================================


NET "CLK" LOC = "P52";

NET "DISP_CNT<0>" LOC = "P30";




NET "DISP<0>" LOC = "P26";







NET "READ_L_IN<0>" LOC = "P122";




NET "SCAN_L<0>" LOC = "P132";




===============================================================

2a. WRITE A VHDL CODE TO CONTROL SPEED, DIRECTION OF DC MOTOR.

AIM: TO CONTROL SPEED AND DIRECTION OF DC MOTOR.

PROCEDURE:

1. Make the connection between FRC9 of the FPGA board to the dc motor connector of the VTU card2.

2. Make the connection between FRC7 of the FPGA board to the keyboard connector of the VTUcard2.

3. Make the connection between frc1 of the FPGA board to the dip switch connector of the VTU card2.

4. Connect the downloading cable and power supply to the FPGA board.

5. Then open the xilinx impact software (refer ISE flow) select the slave serial mode and select the

respective bit file and click program.


7. Press the hex keys and analyze the speed changes.

HDL LAB (06ECL48)


VHDL CODE

LIBRARY IEEE;



LIBRARY UNISIM;

USE UNISIM.VCOMPONENTS.ALL;

ENTITY DCMOTOR IS

PORT ( M_ENABLE,MTR1,MTR2: OUT STD_LOGIC;

RESET,CLK: IN STD_LOGIC;

ROW: IN STD_LOGIC_VECTOR(3 DOWNTO 0) ); -- THIS ARE THE ROW LINES

END DCMOTOR;

ARCHITECTURE DCMOTOR1 OF DCMOTOR IS

SIGNAL COUNTER : STD_LOGIC_VECTOR(BITS - 7 DOWNTO 0):="11111110";

SIGNAL D_CLK : STD_LOGIC_VECTOR (20 DOWNTO 0); -- THIS HAS THE DIVIDED CLOCK.

SIGNAL DUTY_CYCLE: INTEGER RANGE 0 TO 255;

SIGNAL TICK : STD_LOGIC;

BEGIN


PROCESS (CLK) -- CLOCK DIVIDER

BEGIN


D_CLK <= D_CLK + 1;

END IF;

END PROCESS;

--------------------------- END OF CLOCK DIVIDER -------------------------------------------------

TICK <= ROW(0) AND ROW(1) AND ROW(2) AND ROW(3);

PROCESS(D_CLK(12))

BEGIN

IF RISING_EDGE(D_CLK(13)) THEN

COUNTER<= COUNTER +1;

END IF;

END PROCESS;

PROCESS(TICK)

BEGIN

IF FALLING_EDGE(TICK) THEN

CASE ROW IS

WHEN "1110" => DUTY_CYCLE <= 255 ; --MOTOR SPEED 1




WHEN OTHERS => DUTY_CYCLE <= 100;

END CASE;

END IF;

END PROCESS;

PROCESS(RESET)

BEGIN

IF RESET = '0' THEN

M_ENABLE<=’0’;

ELSE

HDL LAB (06ECL48)


M_ENABLE<=’1’;

MTR2 <= ‘0’;

IF COUNTER >= DUTY_CYCLE THEN

MTR1 <= '1';

ELSE

MTR1 <= '0';

END IF;

END IF;

END PROCESS;

END DCMOTOR1;

===============================================================



NET "PWM<0>" LOC = "P5" ;

NET "PWM<1>" LOC = "P141" ;


NET "RLY" LOC = "P3" ;

NET "ROW<0>" LOC = "P64" ;

NET "ROW<1>" LOC = "P63" ;

NET "ROW<2>" LOC = "P60" ;

NET "ROW<3>" LOC = "P58" ;

===============================================================

2b. WRITE A VHDL CODE TO CONTROL SPEED, DIRECTION OF STEPPER MOTOR.

AIM: TO CONTROL SPEED AND DIRECTION OF STEPPER MOTOR.

PROCEDURE:

1. Make the connection between FRC9 of the FPGA board to the stepper motor connector of the VTUcard2.


3. Make the connection between FRC1 of the FPGA board to the dip switch connector of the VTUcard2.





7. Press the hex keys and analyze the speed changes.

HDL LAB (06ECL48)


VHDL CODE

LIBRARY IEEE;




ENTITY STEPPER IS

PORT ( DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

CLK,RESET : IN STD_LOGIC

DIRE: IN STD_LOGIC);

END STEPPER;

ARCHITECTURE BEHAVIORAL OF STEPPER IS

SIGNAL CLK_DIV : STD_LOGIC_VECTOR(20 DOWNTO 0);

SIGNAL CLK_INT: STD_LOGIC;

SIGNAL SHIFT_REG : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

PROCESS(CLK)

BEGIN

IF RISING_EDGE (CLK) THEN

CLK_DIV <= CLK_DIV + '1';

END IF;

END PROCESS;

CLK_INT <= CLK_DIV(16);

PROCESS(RESET,CLK_INT)

BEGIN

IF RESET='0' THEN

SHIFT_REG <= "0001";

ELSIF RISING_EDGE(CLK_INT) THEN

CASE DIRE IS

WHEN ‘0’ =>SHIFT_REG <= SHIFT_REG(2 DOWNTO 0) & SHIFT_REG(3);

WHEN ‘1’ =>SHIFT_REG <= SHIFT_REG(0) & SHIFT_REG(3 DOWNTO 1);


END CASE;

END IF;

END PROCESS;

DOUT <= SHIFT_REG;

END BEHAVIORAL;

===============================================================


NET "CLK" LOC = "P18"; NET "DOUT<0>" LOC = "P7";

NET "DOUT<1>" LOC = "P5"; NET "DOUT<2>" LOC = "P3";

NET "DOUT<3>" LOC = "P141"; NET "RESET" LOC = "P74";

===============================================================

3.a. WRITE A VHDL CODE TO GENERATE SINE WAVEFORMS USING DAC CHANGE THE

FREQUENCY ANDAMPLITUDE.

AIM: TO GENERATE SINE WAVE USING DAC CHANGE THE FREQUENCY AND AMPLITUDE.

PROCEDURE:

1. Make the connection between FRC5 of the FPGA board to the DAC connector of the VTU card2.

2. Make the connection between FRC1 of the FPGAboard to the dip switch connector of the VTU card2.


4. Then open the xilinx impact software (refer ise flow) select the slave serial mode and select the respective bit

file and click program.

5. Make the reset switch on (active low) and analyze the data.

VHDL CODE

LIBRARY IEEE;

HDL LAB (06ECL48)





ENTITY DIGITAL_SINE_WAVE IS


RST : IN STD_LOGIC;

DAC_OUT : OUT STD_LOGIC_VECTOR(0 TO 7));

END DIGITAL_SINE_WAVE ;

ARCHITECTURE BEHAVIORAL OF DIGITAL_SINE_WAVE IS

SIGNAL i: INTEGER RANGE 0 TO 23;

TYPE LOOK_UP IS ARRAY(0 TO 23) OF STD_LOGIC_VECTOR(7 DOWNTO 0);

CONSTANTSINE_LOOKUP:LOOK_UP:=(“01111111”,”10100000”,10111110”,”11011001”,

”11101101”,”11111001”,”11111110”, --0 TO 90°°°°

“11111001”,”11101101”,”11011001”,”10111110”,”10100000”,”01111111”, --TILL 180°°°°

“01011110”,”00111111”,”00100101”,”00010001”,”00000100”,”00000000”, --TILL 270°°°°

“00000100”,”00010001”,”00100101”,”00111111”,”01011110”);

SIGNAL TEMP : STD_LOGIC_VECTOR(2 DOWNTO 0):=”000”;

BEGIN

PROCESS(CLK)

BEGIN


TEMP <= TEMP + '1' ;

END IF;

END PROCESS;

PROCESS(TEMP(2))

BEGIN

IF TEMP(2)= '1' AND TEMP(2)’EVENT THEN

IF RST='1' THEN

DAC <= "00000000";

ELSE

i <= i +1;

DAC<=SINE_LOOKUP(I);

IF i=23 THEN

i<=0;

END IF;

END IF;

END PROCESS;

END BEHAVIORAL;

3b. WRITE A VHDL CODE TO GENERATE SQUARE WAVEFORMS USING DAC CHANGE THE

FREQUENCY AND AMPLITUDE.

AIM: TO GENERATE SQUARE WAVE USING DAC. CHANGE THE FREQUENCY AND AMPLITUDE.

PROCEDURE:

1. Make the connection between FRC5 of the FPGA board to the DACconnector of the VTU card2.

2. Make the connection between FRC1 of the fpga board to the dip switch connector of the VTU card2.





VHDL CODE

LIBRARY IEEE;


========================================================



NET "DAC_OUT<0>" LOC = "P27" ;








NET "RST" LOC = "P74" ;

HDL LAB (06ECL48)




ENTITY SQUARE_WAVE IS


RST : IN STD_LOGIC;


END SQUARE_WAVE;

ARCHITECTURE BEHAVIORAL OF SQUARE_WAVE IS

SIGNAL TEMP : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL COUNTER : STD_LOGIC_VECTOR(0 TO 7);

SIGNAL EN :STD_LOGIC;

BEGIN

PROCESS(CLK)

BEGIN



END IF;

END PROCESS;

PROCESS(TEMP(3))

BEGIN

IF RST='1' THEN

COUNTER <= "00000000";

ELSIF RISING_EDGE(TEMP(3)) THEN

IF COUNTER<255 AND EN='0' THEN

COUNTER <= COUNTER + 1 ;

EN<='0';

DAC_OUT <="00000000"; --DAC_OUT<=COUNTER;(FOR TRIANGULAR WAVE)

ELSIF COUNTER=0 THEN

EN<='0';

ELSE

EN<='1';

COUNTER <= COUNTER-1;

DAC_OUT <="11111111"; --DAC_OUT<=COUNTER;(FOR TRIANGULAR WAVE)

END IF;

END IF;

END PROCESS;

END BEHAVIORAL;

===============================================================












===============================================================

HDL LAB (06ECL48)


3.c. WRITE A VHDL CODE TO GENERATE TRAINGULAR WAVEFORMS USING DAC CHANGE

THE FREQUENCY AND AMPLITUDE.

AIM: TO GENERATE TRIANGULAR WAVE USING DAC. CHANGE THE FREQUENCY AND AMPLITUDE.

PROCEDURE:

1. Make the connection between FRC5 of the fpga board to the DACconnector of the VTUcard2.

2. Make the connection between frc1 of the fpga board to the dip switch connector of the VTUcard2.





VHDL CODE

LIBRARY IEEE;


HDL LAB (06ECL48)




ENTITY TRIANGULAR_WAVE IS


RST : IN STD_LOGIC;


END TRIANGULAR_WAVE ;

ARCHITECTURE BEHAVIORAL OF TRIANGULAR_WAVE IS




BEGIN

PROCESS(CLK)

BEGIN



END IF;

END PROCESS;

PROCESS(TEMP(3))

BEGIN

IF RST='1' THEN

COUNTER <= "000000000";



IF COUNTER(0)='1' THEN

DAC_OUT <=COUNTER(1 TO 8);

ELSE

DAC_OUT <=NOT(COUNTER(1 TO 8));

END IF;

END IF;

END PROCESS;

END BEHAVIORAL;

3.d. WRITE A VHDL CODE TO GENERATE RAMP WAVEFORMS USING DAC CHANGE THE

FREQUENCY AND AMPLITUDE.

AIM: TO GENERATE RAMP WAVE USING DAC CHANGE THE FREQUENCY AND AMPLITUDE.

PROCEDURE:

1. Make the connection between FRC5 of the FPGA board to the DAC connector of the VTU card2.

2. Make the connection between FRC1 of the FPGA board to the dip switch connector of the VTU card2.





VHDL CODE

LIBRARY IEEE;




================================================












================================================

HDL LAB (06ECL48)


ENTITY RAMP_WAVE IS


RST : IN STD_LOGIC;


END RAMP_WAVE;

ARCHITECTURE BEHAVIORAL OF RAMP_WAVE IS




BEGIN

PROCESS(CLK)

BEGIN



END IF;

END PROCESS;

PROCESS(TEMP(3))

BEGIN

IF RST='1' THEN

COUNTER <= "00000000";



END IF;

END PROCESS;

DAC_OUT <=COUNTER;

END BEHAVIORAL;

===============================================================


NET "CLK" LOC = "P18" ; NET "DAC_OUT<0>" LOC = "P27" ;

NET "DAC_OUT<1>" LOC = "P26" ; NET "DAC_OUT<2>" LOC = "P22" ;



NET "DAC_OUT<7>" LOC = "P4" ; NET "RST" LOC = "P74" ;

===============================================================

3.e. WRITE A VHDL CODE TO GENERATE SAWTOOTH WAVEFORMS USING DAC CHANGE

THE FREQUENCY AND AMPLITUDE.

AIM: TO GENERATE SAWTOOTH WAVE USING DAC CHANGE THE FREQUENCY AND AMPLITUDE.

PROCEDURE:

1. Make the connection between frc5 of the FPGA board to the DAC connector of the vtu card2.

2. Make the connection between frc1 of the FPGA board to the dip switch connector of the vtu card2.





VHDL CODE

LIBRARY IEEE;




ENTITY SWATOOTH_WAVE IS

HDL LAB (06ECL48)



RST : IN STD_LOGIC;


END SWATOOTH_WAVE;

ARCHITECTURE BEHAVIORAL OF SWATOOTH_WAVE IS




BEGIN

PROCESS(CLK)

BEGIN



END IF;

END PROCESS;

PROCESS(TEMP(3))

BEGIN

IF RST='1' THEN

COUNTER <= "00000000";



END IF;

END PROCESS;

DAC_OUT <=COUNTER;

END BEHAVIORAL;

===============================================================


NET "CLK" LOC = "P18" ; NET "DAC_OUT<0>" LOC = "P27" ;




===============================================================

4. WRITE A VHDL CODE TO CONTROL EXTERNAL LIGHTS USING RELAYS.

AIM: TO CONTROL EXTERNAL LIGHTS USING RELAYS.

PROCEDURE:

1. Make the connection between frc9 of theFPGAboard to the external light connector of the VTU card2.






VHDL CODE

LIBRARY IEEE;




ENTITY EXTLIGHT IS

PORT ( CNTRL1,CNTRL2 : IN STD_LOGIC;

LIGHT : OUT STD_LOGIC);

HDL LAB (06ECL48)


END EXTLIGHT;

ARCHITECTURE BEHAVIORAL OF EXTLIGHT IS

BEGIN

LIGHT<= CNTRL1 OR CNTRL2 ;

END BEHAVIORAL;

===============================================================

UCF FILE(USER CONSTRAINT

NET "CNTRL1" LOC = "P74";

NET "CNTRL2" LOC = "P75";

NET "LIGHT" LOC = "P7";

5a. WRITE A VHDL CODE TO ACCEPT 8 CHANNEL ANALOG SIGNAL, TEMPERATURE

SENSORS AND DISPLAY THE DATA ON LCD PANEL OR SEVEN SEGMENT DISPLAY.

AIM: TO ACCEPT 8 CHANNEL ANALOG SIGNAL, AND DISPLAY THE DATA ON LCD PANEL DISPLAY.

PROCEDURE:

1. Make the connection between frc5 of the FPGA board to the LCD display connector of the VTU card1.

2. Make the connection between frc10 of the FPGA board to the ADC connector of the VTU card1.


4. Short the jumper j1 to the vin to get the analog signal.






VHDL CODING

LIBRARY IEEE;




HDL LAB (06ECL48)


LIBRARY UNISIM;


ENTITY ADC_LCD IS

PORT ( CLK: IN STD_LOGIC; -- 4 MHZ CLOCK


INTR: IN STD_LOGIC;

ADC_OUT: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

CS,RD,WR:OUT STD_LOGIC;




LCD_DATA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); -- GIVES REGISTERED DATA OUTPUT

END ADC_LCD;

ARCHITECTURE ADC_BEH OF ADC_LCD IS



-- CLEAR SCREEN.






--FREQUENCY DIVIDER

SIGNAL COUNTER : STD_LOGIC_VECTOR(18 DOWNTO 0);

SIGNAL CLK_DIV :STD_LOGIC;




SIGNAL DIGITAL_DATA1,DATA1,DATA2: STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL DIGITAL_DATA : INTEGER RANGE 0 TO 255;

SIGNAL NTR :STD_LOGIC;

BEGIN

IBUF_INST : IBUF

-- EDIT THE FOLLOWING GENERIC TO SPECIFY THE I/O STANDARD FOR THIS PORT.

GENERIC MAP (

IOSTANDARD => "LVCMOS25")

PORT MAP (

O => NTR, -- BUFFER OUTPUT

I => INTR -- BUFFER INPUT (CONNECT DIRECTLY TO TOP-LEVEL PORT));

PROCESS(CLK)

BEGIN


COUNTER<=COUNTER+'1';

END IF;

END PROCESS;

CLK_DIV<=COUNTER(7);

CS <='0';

WR <=NTR;

DIGITAL_DATA1 <= ADC_OUT ;

RD <='0';

DIGITAL_DATA<=CONV_INTEGER(DIGITAL_DATA1) ;

PROCESS(DIGITAL_DATA)

BEGIN

CASE (DIGITAL_DATA) IS

WHEN 0 TO 100 => DATA1 <= ONE ; DATA2 <= NINE ;

WHEN 101 TO 110 => DATA1 <= TWO ; DATA2 <= ZERO ;

HDL LAB (06ECL48)


WHEN 111 TO 120 => DATA1 <= TWO ; DATA2 <= ONE ;

WHEN 121 TO 130 => DATA1 <= TWO ; DATA2 <= TWO ;

WHEN 131 TO 140 => DATA1 <= TWO ; DATA2 <= THREE ;

WHEN 141 TO 150 => DATA1 <= TWO ; DATA2 <= FOUR ;

WHEN 151 TO 160 => DATA1 <= TWO ; DATA2 <= FIVE ;

WHEN 161 TO 170 => DATA1 <= TWO ; DATA2 <= SIX ;

WHEN 171 TO 180 => DATA1 <= TWO ; DATA2 <= SEVEN ;

WHEN 181 TO 190 => DATA1 <= TWO ; DATA2 <= EIGHT ;

WHEN 191 TO 200 => DATA1 <= TWO ; DATA2 <= NINE ;

WHEN 201 TO 205 => DATA1 <= THREE ; DATA2 <= ZERO ;

WHEN 206 TO 210 => DATA1 <= THREE ; DATA2 <= ONE ;

WHEN 211 TO 215 => DATA1 <= THREE ; DATA2 <= TWO ;

WHEN 216 TO 220 => DATA1 <= THREE ; DATA2 <= THREE ;

WHEN 221 TO 225 => DATA1 <= THREE ; DATA2 <= FOUR ;

WHEN 226 TO 230 => DATA1 <= THREE ; DATA2 <= FIVE ;

WHEN 231 TO 235 => DATA1 <= THREE ; DATA2 <= SIX ;

WHEN 236 TO 240 => DATA1 <= THREE ; DATA2 <= SEVEN ;

WHEN 241 TO 245 => DATA1 <= THREE ; DATA2 <= EIGHT ;

WHEN 246 TO 250 => DATA1 <= THREE ; DATA2 <= NINE ;

WHEN OTHERS => DATA1 <= FOUR ; DATA2 <= ZERO ;

END CASE;

END PROCESS;

LCD_RW<='0';

PROCESS (CLK_DIV,RESET)



BEGIN

IF RESET = '1' THEN

STATE<=INITIAL;

COUNT:=0;

LCD_ENABLE<='0';

LCD_SELECT<='0';

C1 := "01111111";

ELSIF CLK_DIV'EVENT AND CLK_DIV = '1' THEN

CASE STATE IS



LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

LCD_DATA<=SET;

LCD_SELECT<='0';


STATE<=DISPLAY;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;



LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

LCD_DATA<=DON;

HDL LAB (06ECL48)


LCD_SELECT<='0';


STATE<=CLEAR;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;



LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

LCD_DATA<=CLR;

LCD_SELECT<='0';


STATE<=LOCATION;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;



LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

IF COUNT=0 THEN

IF C1="10001111" THEN

C1:="10000000";

ELSE

C1:=C1+'1';

END IF;

END IF;

LCD_DATA <= C1 ;

LCD_SELECT<='0';


STATE<=PUTCHAR;

COUNT:=0; ELSE

COUNT:=COUNT+1;

END IF;



LCD_ENABLE<='1';

ELSE LCD_ENABLE<='0';

END IF;

CASE C1 IS

WHEN "10000000" => LCD_DATA<= A ;

WHEN "10000001" => LCD_DATA<= D ;

WHEN "10000010" => LCD_DATA<= C ;


WHEN "10000100" => LCD_DATA<= V ;

WHEN "10000101" => LCD_DATA<= O ;

WHEN "10000110" => LCD_DATA<= L ;

WHEN "10000111" => LCD_DATA<= T ;

WHEN "10001000" => LCD_DATA<= A ;

HDL LAB (06ECL48)


WHEN "10001001" => LCD_DATA<= G ;

WHEN "10001010" => LCD_DATA<= E ;


WHEN "10001100" => LCD_DATA<= EQUAL ;

WHEN "10001101" => LCD_DATA<= DATA1 ;

WHEN "10001110" => LCD_DATA<= DOT ;

WHEN "10001111" => LCD_DATA<= DATA2;


















END CASE ;

LCD_SELECT<='1';


STATE<=LOCATION;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;

END CASE;

END IF;

END PROCESS;

END ADC_BEH;

===============================================================




NET "CS" LOC = "P6" ;

NET "INTR" LOC = "P12" ;

NET "ADC_OUT<0>" LOC = "P13" ;








NET "WR" LOC = "P11";

NET "RD" LOC = "P10";

NET "LCD_RW" LOC = "P20";

NET "LCD_SELECT" LOC = "P4";



HDL LAB (06ECL48)









===============================================================

5b.WRITE A VHDL CODE TO ACCEPT 8 CHANNEL ANALOG SIGNAL, TEMPERATURE

SENSORS AND DISPLAY THE DATA ON LCD PANEL OR SEVEN SEGMENT DISPLAY.

AIM: TO ACCEPT TEMPERATURE SENSORS, AND DISPLAY THE DATA ON LCD PANEL DISPLAY.

PROCEDURE:

1. Make the connection between FRC of the FPGA board to the LCD display connector of the VTU card1.

2. Make the connection between FRC10 of the FPGA board to the ADC connector of the VTU card1.

3. Make the connection between FRC6 of the fpga board to the dip switch connector of the VTU card1.

4. Short the jumper j1 to the tc to sense the temperature.






VHDL CODE

LIBRARY IEEE;




LIBRARY UNISIM;


HDL LAB (06ECL48)


ENTITY TEMP_LCD IS



INTR: IN STD_LOGIC;

ADC_OUT: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

CS,RD,WR:OUT STD_LOGIC;




LCD_DATA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); -- GIVES REGISTERED DATA OUTPUT

END TEMP_LCD;

ARCHITECTURE TEMP_BEH OF TEMP_LCD IS



-- CLEAR SCREEN.






--FREQUENCY DIVIDER

SIGNAL COUNTER : STD_LOGIC_VECTOR(18 DOWNTO 0);

SIGNAL CLK_DIV :STD_LOGIC;

--SIGNAL C: STD_LOGIC_VECTOR(7 DOWNTO 0);




SIGNAL DIGITAL_DATA1,DATA1,DATA2: STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL DIGITAL_DATA : INTEGER RANGE 0 TO 255;

SIGNAL NTR :STD_LOGIC;

BEGIN

IBUF_INST : IBUF

-- EDIT THE FOLLOWING GENERIC TO SPECIFY THE I/O STANDARD FOR THIS PORT.

GENERIC MAP (

IOSTANDARD => "LVCMOS25")

PORT MAP (

O => NTR, -- BUFFER OUTPUT

I => INTR -- BUFFER INPUT (CONNECT DIRECTLY TO TOP-LEVEL PORT));

PROCESS(CLK)

BEGIN


COUNTER<=COUNTER+'1';

END IF;

END PROCESS;

CLK_DIV<=COUNTER(7);

CS <='0';

WR <=NTR;

DIGITAL_DATA1 <= ADC_OUT ;

RD <='0';

DIGITAL_DATA<=CONV_INTEGER(DIGITAL_DATA1) ;

PROCESS(DIGITAL_DATA)

BEGIN

CASE (DIGITAL_DATA) IS

WHEN 0 TO 60 => DATA1 <= ZERO ; DATA2 <= NINE ;

WHEN 61 TO 65 => DATA1 <= ONE ; DATA2 <= ZERO ;

WHEN 66 TO 70 => DATA1 <= ONE ; DATA2 <= ONE ;

HDL LAB (06ECL48)


WHEN 71 TO 75 => DATA1 <= ONE ; DATA2 <= TWO ;

WHEN 76 TO 80 => DATA1 <= ONE ; DATA2 <= THREE ;

WHEN 81 TO 85 => DATA1 <= ONE ; DATA2 <= FOUR ;

WHEN 86 TO 90 => DATA1 <= ONE ; DATA2 <= FIVE ;

WHEN 91 TO 95 => DATA1 <= ONE; DATA2 <= SIX ;

WHEN 96 TO 100 => DATA1 <= ONE ; DATA2 <= SEVEN ;

WHEN 101 TO 105 => DATA1 <= ONE ; DATA2 <= EIGHT ;

WHEN 106 TO 110 => DATA1 <= ONE ; DATA2 <= NINE ;

WHEN 111 TO 115 => DATA1 <= TWO ; DATA2 <= ZERO ;

WHEN 116 TO 120 => DATA1 <= TWO ; DATA2 <= ONE ;

WHEN 121 TO 125 => DATA1 <= TWO ; DATA2 <= TWO ;

WHEN 126 TO 130 => DATA1 <= TWO ; DATA2 <= THREE ;

WHEN 131 TO 135 => DATA1 <= TWO ; DATA2 <= FOUR ;

WHEN 136 TO 140 => DATA1 <= TWO ; DATA2 <= FIVE ;

WHEN 141 TO 145 => DATA1 <= TWO ; DATA2 <= SIX ;

WHEN 146 TO 150 => DATA1 <= TWO ; DATA2 <= SEVEN ;

WHEN 151 TO 155 => DATA1 <= TWO ; DATA2 <= EIGHT ;

WHEN 156 TO 160 => DATA1 <= TWO ; DATA2 <= NINE ;

WHEN 161 TO 165 => DATA1 <= THREE ; DATA2 <= ZERO ;

WHEN 166 TO 170 => DATA1 <= THREE ; DATA2 <= TWO ;

WHEN 171 TO 175 => DATA1 <= THREE ; DATA2 <= THREE ;

WHEN 176 TO 180 => DATA1 <= THREE ; DATA2 <= FOUR ;

WHEN 181 TO 185 => DATA1 <= THREE ; DATA2 <= FIVE ;

WHEN 186 TO 190 => DATA1 <= THREE ; DATA2 <= SIX ;

WHEN 191 TO 195 => DATA1 <= THREE ; DATA2 <= SEVEN ;

WHEN 196 TO 200 => DATA1 <= THREE ; DATA2 <= EIGHT ;

WHEN 201 TO 205 => DATA1 <= THREE ; DATA2 <= NINE ;

WHEN 206 TO 210 => DATA1 <= FOUR ; DATA2 <= ZERO ;

WHEN 211 TO 214 => DATA1 <= FOUR ; DATA2 <= ONE ;

WHEN 215 TO 219 => DATA1 <= FOUR ; DATA2 <= TWO ;

WHEN 220 TO 224 => DATA1 <= FOUR ; DATA2 <= THREE ;

WHEN 225 TO 229 => DATA1 <= FOUR ; DATA2 <= FOUR ;

WHEN 230 TO 234 => DATA1 <= FOUR ; DATA2 <= FIVE;

WHEN 235 TO 239 => DATA1 <= FOUR ; DATA2 <= SIX ;

WHEN 240 TO 244 => DATA1 <= FOUR ; DATA2 <= SEVEN ;

WHEN 245 TO 249 => DATA1 <= FOUR ; DATA2 <= EIGHT;

WHEN 250 TO 255 => DATA1 <= FOUR; DATA2 <= NINE ;

WHEN OTHERS => DATA1 <= FIVE ; DATA2 <= ZERO ;

END CASE;

END PROCESS;

LCD_RW<='0';

PROCESS (CLK_DIV,RESET)



BEGIN

IF RESET = '1' THEN

STATE<=INITIAL;

COUNT:=0;

LCD_ENABLE<='0';

LCD_SELECT<='0';

C1 := "01111111";

ELSIF CLK_DIV'EVENT AND CLK_DIV = '1' THEN

CASE STATE IS



LCD_ENABLE<='1';

HDL LAB (06ECL48)


ELSE

LCD_ENABLE<='0';

END IF;

LCD_DATA<=SET;

LCD_SELECT<='0';


STATE<=DISPLAY;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;



LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

LCD_DATA<=DON;

LCD_SELECT<='0';


STATE<=CLEAR;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;



LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

LCD_DATA<=CLR;

LCD_SELECT<='0';


STATE<=LOCATION;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;



LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

IF COUNT=0 THEN

IF C1="10001111" THEN

C1:="10000000";

ELSE

C1:=C1+'1';

END IF;

END IF;

LCD_DATA <= C1 ;

LCD_SELECT<='0';


STATE<=PUTCHAR;

HDL LAB (06ECL48)


COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;



LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

CASE C1 IS

WHEN "10000000" => LCD_DATA<= T ;

WHEN "10000001" => LCD_DATA<= E ;

WHEN "10000010" => LCD_DATA<= M ;

WHEN "10000011" => LCD_DATA<= P ;

WHEN "10000100" => LCD_DATA<= E ;

WHEN "10000101" => LCD_DATA<= R ;

WHEN "10000110" => LCD_DATA<= A ;

WHEN "10000111" => LCD_DATA<= T ;

WHEN "10001000" => LCD_DATA<= U ;

WHEN "10001001" => LCD_DATA<= R ;

WHEN "10001010" => LCD_DATA<= E ;





WHEN "10001111" => LCD_DATA<= C;


















END CASE;

LCD_SELECT<='1';


STATE<=LOCATION;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;

END CASE;

END IF;

END PROCESS;

END TEMP_BEH;

HDL LAB (06ECL48)


===============================================================




NET "CS" LOC = "P6" ;

NET "INTR" LOC = "P12" ;









NET "WR" LOC = "P11";

NET "RD" LOC = "P10";

NET "LCD_RW" LOC = "P20";

NET "LCD_SELECT" LOC = "P4";










===============================================================

6. WRITE A VHDL CODE TO SIMULATE ELEVATOR OPERATIONS.

AIM: TO OPERATE ELEVATOR AND OBSERVE THE SIMULATION RESULTS ON LCD.

PROCEDURE:

1. Make the connection between FRC5 of the FPGA board to the LCD display connector of the VTU card1.


3. make the connection between FRC6 of the FPGA board to the dip switch connector of the VTU card1.






VHDL CODE

LIBRARY IEEE;




ENTITY ELEVATOR IS

GENERIC(BITS : INTEGER := 8 ); -- NUMBER OF BITS USED FOR DUTY CYCLE.

-- ALSO DETERMINES PWM PERIOD.


RESET,EN: IN STD_LOGIC; -- MASTER RESET PIN

HDL LAB (06ECL48)



PWM : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);



ROW: IN STD_LOGIC_VECTOR(0 TO 3); -- THIS ARE THE ROW LINES

LCD_DATA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- GIVES REGISTERED DATA OUTPUT

COL: INOUT STD_LOGIC_VECTOR(0 TO 3));

END ELEVATOR;

ARCHITECTURE RTL OF ELEVATOR IS

SIGNAL COUNTER : STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0):="00000000";

TYPE KEYPAD_STATE_TYPE IS (WAIT_R_0, C3, C2, C1, C0, FOUND, SAMPLE, WAIT_R_1);

-- STATE NAMES



-- CLEAR SCREEN.






--FREQUENCY DIVIDER




SIGNAL CS, NS: KEYPAD_STATE_TYPE; -- SIGNALS FOR CURRENT AND NEXT STATES

SIGNAL DUTY_CYCLE,DUTY_CYCLE1 : STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0);

SIGNAL DIV_REG: STD_LOGIC_VECTOR (22 DOWNTO 0); -- CLOCK DIVIDE REGISTER

SIGNAL DCLK,DDCLK: STD_LOGIC; -- THIS HAS THE DIVIDED CLOCK.

SIGNAL COL_REG_VALUE: STD_LOGIC_VECTOR (0 TO 3);

SIGNAL R1,CLK_D,START,STOP: STD_LOGIC; -- ROW DETECTION SIGNAL

SIGNAL KEY_VALUE1,FLOOR,KEY_VALUE: INTEGER RANGE 0 TO 15;

SIGNAL DATA,DATA1,FLOOR_NUM: STD_LOGIC_VECTOR (7 DOWNTO 0);

SIGNAL TEMP1,TEMP2,TEMP3,TEMP4: STD_LOGIC_VECTOR (7 DOWNTO 0);

SIGNAL TEMP5,TEMP6,TEMP7,TEMP8: STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN

--CLK_OUT <= DCLK;

R1 <= ROW(3) OR ROW(2) OR ROW(1) OR ROW(0);

---------------------------- BEGINING OF FSM1 (KEYPAD SCANNER) -------------------------------

SYNC_PROC: PROCESS (DCLK, RESET, KEY_VALUE) -- THIS IS THE SYNCHRONOUS PART

BEGIN

IF (RESET = '0') THEN -- YOU MUST HAVE A RESET FOR FSM TO SYNTHESIZE PROPERLY

CS <= WAIT_R_0;

ELSIF (DCLK'EVENT AND DCLK = '1') THEN

CS <= NS;

END IF; END PROCESS;

COMB_PROC: PROCESS (CS, R1, COL_REG_VALUE) -- THIS IS THE COMBINATIONAL PART

BEGIN

CASE CS IS

WHEN WAIT_R_0 => -- WAITS TILL A BUTTON IS PRESSED

COL <= "1111"; -- KEEP ALL COLUMNS ACTIVATED

IF R1 = '1' THEN -- A BUTTON WAS PRESSED. BUT WHICH ONE?

NS <= C3; -- LET'S FIND OUT

ELSE

NS <= WAIT_R_0;

END IF;

---------------------------------------------------------------------------------------------------

HDL LAB (06ECL48)


WHEN C3 => --




ELSE NS <= FOUND; -- BUTTON WAS IN COLUMN 3

END IF;

---------------------------------------------------------------------------------------------------

WHEN C2 => --




ELSE


END IF;

---------------------------------------------------------------------------------------------------

WHEN C1 => --




ELSE


END IF;

---------------------------------------------------------------------------------------------------

WHEN C0 => --


IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 0 ??

NS <= WAIT_R_0; -- SO THE BUTTON MUST HAVE BEEN DEPRESSED FAST

ELSE


END IF;

---------------------------------------------------------------------------------------------------

WHEN FOUND => --


IF R1 = '0' THEN -- THIS MEANS BUTTON IS DEPRESSED


ELSE

NS <= SAMPLE; -- OTHERWISE WRITE THE KEY VALUE TO DATA REGISTER

END IF;

---------------------------------------------------------------------------------------------------

WHEN SAMPLE => -- THIS STATE WILL GENERATE A SIGNAL WITH ONE CLOCK PERIOD FOR

SAMPLING



---------------------------------------------------------------------------------------------------

WHEN WAIT_R_1 => --


IF R1 = '0' THEN -- THIS MEANS BUTTON WAS DEPRESSED


ELSE


END IF;

---------------------------------------------------------------------------------------------------

END CASE;

END PROCESS;

---------------------------------------------------------------------------------------------------

WRITE_DATA: PROCESS (DCLK, CS, KEY_VALUE) -- WRITE VALID DATA TO REGISTER

HDL LAB (06ECL48)


BEGIN

IF DCLK'EVENT AND DCLK = '0' THEN -- ON THE FALLING EDGE

IF CS = FOUND THEN

KEY_VALUE <= KEY_VALUE1;

END IF;

END IF;

END PROCESS; -- WRITE_DATA

---------------------------------------------------------------------------------------------------

COL_REG: PROCESS (DCLK, CS, COL) -- THIS IS THE COLUMN VALUE REGISTER

BEGIN

IF (DCLK'EVENT AND DCLK = '0') THEN -- REGISTER THE COL VALUE ON THE FALLING EDGE

IF (CS = C3 OR CS = C2 OR CS = C1 OR CS = C0) THEN -- PROVIDED WE'RE IN STATES C3 THRU C0

ONLY

COL_REG_VALUE <= COL; -- OTHERWISE THE COLUMN VALUE IS NOT VALID

END IF;

END IF;

END PROCESS; -- COL_REG

---------------------------------------------------------------------------------------------------

DECODER: PROCESS(ROW, COL_REG_VALUE) -- DECODES BINARY VALUE OF PRESSED KEY

FROM ROW AND

COLUMN

VARIABLE CODE: STD_LOGIC_VECTOR (0 TO 7);

BEGIN

CODE := (ROW & COL_REG_VALUE);

CASE CODE IS

-- COL

-- ROW 0 0123

WHEN "00010001" => KEY_VALUE1 <= 0;

WHEN "00010010" => KEY_VALUE1 <= 1;

WHEN "00010100" => KEY_VALUE1 <= 2;

WHEN "00011000" => KEY_VALUE1 <= 3;

-- ROW 1

WHEN "00100001" => KEY_VALUE1 <= 4;

WHEN "00100010" => KEY_VALUE1 <= 5;

WHEN "00100100" => KEY_VALUE1 <= 6;

WHEN "00101000" => KEY_VALUE1 <= 7;

-- ROW 2

WHEN "01000001" => KEY_VALUE1 <= 8;

WHEN "01000010" => KEY_VALUE1 <= 9;

WHEN "01000100" => KEY_VALUE1 <= 10;

WHEN "01001000" => KEY_VALUE1 <= 11;

-- ROW 3

WHEN "10000001" => KEY_VALUE1 <= 12;

WHEN "10000010" => KEY_VALUE1 <= 13;

WHEN "10000100" => KEY_VALUE1 <= 14;

WHEN "10001000" => KEY_VALUE1 <= 15;

WHEN OTHERS => KEY_VALUE1 <= 0;

END CASE;

END PROCESS; -- DECODER

---------------------------- END OF FSM1 (KEYPAD SCANNER) ---------------------------------------


CLK_DIV: PROCESS (CLK, DIV_REG) -- CLOCK DIVIDER

BEGIN


DIV_REG <= DIV_REG + 1;

END IF;

HDL LAB (06ECL48)


END PROCESS;

DCLK <= DIV_REG(8);

DDCLK<=DIV_REG(10);

CLK_D<=DIV_REG(22);

---------------------------- END OF CLOCK DIVIDER -------------------------------------------------

LCD_RW<='0';

PROCESS (DDCLK,RESET)



BEGIN

IF RESET = '0' THEN

STATE<=INITIAL;

COUNT:=0;

LCD_ENABLE<='0';

LCD_SELECT<='0';

C1 := "01111111";

ELSIF DDCLK'EVENT AND DDCLK = '1' THEN

CASE STATE IS



LCD_ENABLE<='1';


END IF;

LCD_DATA<=SET;

LCD_SELECT<='0';


STATE<=DISPLAY;

COUNT:=0;

ELSE COUNT:=COUNT+1;

END IF;



LCD_ENABLE<='1';


END IF;

LCD_DATA<=DON;

LCD_SELECT<='0';


STATE<=CLEAR;

COUNT:=0;


END IF;



LCD_ENABLE<='1';


END IF;

LCD_DATA<=CLR;

LCD_SELECT<='0';


STATE<=LOCATION;

COUNT:=0;


END IF;



HDL LAB (06ECL48)


LCD_ENABLE<='1';


END IF;

IF COUNT=0 THEN

IF C1="10001111" THEN

C1:="11000000";

ELSIF C1="11001111" THEN

C1:="10000000";

ELSE C1:=C1+'1';

END IF;

END IF;

LCD_DATA <= C1;

LCD_SELECT<='0';


STATE<=PUTCHAR;

COUNT:=0;


END IF;



LCD_ENABLE<='1';


END IF;

CASE C1 IS

WHEN "10000000" => LCD_DATA<= F ;--SIGLE LINE

WHEN "10000001" => LCD_DATA<= L ;--SIGLE LINE

WHEN "10000010" => LCD_DATA<= O ;--SIGLE LINE

WHEN "10000011" => LCD_DATA<= O ;--SIGLE LINE

WHEN "10000100" => LCD_DATA<= R ;--SIGLE LINE


WHEN "10000110" => LCD_DATA<= N ;--SIGLE LINE

WHEN "10000111" => LCD_DATA<= U ;--SIGLE LINE

WHEN "10001000" => LCD_DATA<= M ;

WHEN "10001001" => LCD_DATA<= B ;

WHEN "10001010" => LCD_DATA<= E ;

WHEN "10001011" => LCD_DATA<= R ;



WHEN "10001110" => LCD_DATA<= FLOOR_NUM ;



WHEN "11000001" => LCD_DATA<= T ;--SIGLE LINE

WHEN "11000010" => LCD_DATA<= A ;--SIGLE LINE

WHEN "11000011" => LCD_DATA<= T ;--SIGLE LINE

WHEN "11000100" => LCD_DATA<= U ;--SIGLE LINE



WHEN "11000111" => LCD_DATA<= TEMP1 ;--SIGLE LINE

WHEN "11001000" => LCD_DATA<= TEMP2 ;








HDL LAB (06ECL48)



END CASE ;

LCD_SELECT<='1';


STATE<=LOCATION;

COUNT:=0;


END IF; END CASE; END IF; END PROCESS;

PROCESS(CLK_D,RESET)

VARIABLE COU : STD_LOGIC_VECTOR(1 DOWNTO 0);

VARIABLE START,STOP: STD_LOGIC; -- ROW DETECTION SIGNAL

BEGIN

IF RESET='0' THEN

COU:="00";

TEMP1 <= L ;

TEMP2 <= I ;

TEMP3 <= F ;

TEMP4 <= T ;

TEMP5 <= I ;

TEMP6 <= D ;

TEMP7 <= L ;

TEMP8 <= E ;

FLOOR_NUM <= ZERO ;

ELSIF RISING_EDGE(CLK_D) THEN

CASE KEY_VALUE IS

WHEN 0 => FLOOR_NUM <= ZERO ;

FLOOR <=0;

WHEN 1 => FLOOR_NUM <= ONE ;

FLOOR <=1;

WHEN 2 => FLOOR_NUM <= TWO ;

FLOOR <=2;

WHEN 3 => FLOOR_NUM <= THREE ;

FLOOR <=3;

WHEN 4 =>

TEMP1 <= D ;

TEMP2 <= O ;

TEMP3 <= O ;

TEMP4 <= R ;

TEMP5 <= O ;

TEMP6 <= P ;

TEMP7 <= E ;

TEMP8 <= N ;

WHEN 5 =>

TEMP1 <= D ;

TEMP2 <= O ;

TEMP3 <= O ;

TEMP4 <= R ;

TEMP5 <= C ;

TEMP6 <= L ;

TEMP7 <= O ;

TEMP8 <= S ;

WHEN 6 =>

START:='1';

STOP:='0';

WHEN 7 =>

STOP:='1';

HDL LAB (06ECL48)


START:='0';

WHEN OTHERS =>

TEMP1 <= I ;

TEMP2 <= D ;

TEMP3 <= L ;

TEMP4 <= E ;

TEMP5 <= K ;

TEMP6 <= E ;

TEMP7 <= Y ;

TEMP8 <= SPACE ;

END CASE;

IF START='1' THEN

IF COU=FLOOR THEN

START := '0';

COU:=COU;

TEMP7 <= "001100" & COU ;

ELSIF COU<=FLOOR THEN

COU:=COU + '1';

TEMP1 <= U ;

TEMP2 <= P ;

TEMP3 <= SPACE ;

TEMP4 <= SPACE ;

TEMP5 <= SPACE ;

TEMP6 <= "01111110" ;

TEMP7 <= "001100" & COU ;

TEMP8 <= SPACE ;

ELSIF COU>=FLOOR THEN

COU:=COU-'1';

TEMP1 <= D ;

TEMP2 <= O ;

TEMP3 <= W ;

TEMP4 <= N ;

TEMP5 <= SPACE ;

TEMP6 <= "01111111" ;

TEMP7 <= "001100" & COU ;

TEMP8 <= SPACE ;

END IF; END IF; END IF;

END PROCESS;

END RTL;

===============================================================




NET "COL<0>" LOC = "P83" ;

NET "COL<1>" LOC = "P79" ;

NET "COL<2>" LOC = "P80" ;

NET "COL<3>" LOC = "P77" ;

NET "ROW<0>" LOC = "P78" ;

NET "ROW<1>" LOC = "P76" ;

NET "ROW<2>" LOC = "P75" ;

NET "ROW<3>" LOC = "P74" ;


NET "LCD_RW" LOC = "P20" ;

NET "LCD_SELECT" LOC = "P4" ;


HDL LAB (06ECL48)









===============================================================

HDL LAB (06ECL48)


HDL LAB (06ECL48)


HDL LAB (06ECL48)


HDL LAB (06ECL48)


VIVA QUESTIONS

1) Differences between D-Latch and D flip-flop?

2) What is setup time and hold time?

3) What is racing condition?

4) What do you mean by comparator and write the truth table?

5) What is decoder and write the truth table?

6) What is encoder and write the truth table?

7) What is priority encoder, and what is the difference between encoder and priority

encoder?

8) What is the difference between decoder and encoder?

9) What is multiplexer and write the truth table?

10) Give the applications of mux?

11) What is the difference between decoder and multiplexer?

12) What do you mean by sequential circuits and combinational circuits?

13) Give the comparison between combinational and sequential circuits.

HDL LAB (06ECL48)


14) Give the comparison between synchronous and asynchronous circuits.

15) Draw and explain the working of basic bistable element.

16) Draw and explain the working of a) SR latch b) gated SR latch c) Gated D latch.

17) Draw and explain the working of all flip-flops.

18) Explain the working of 4-bit asynchronous counter.

19) What is the difference between synchronous and asynchronous counters?

20) Explain Synchronous and Asynchronous reset.

21) How can you convert a JK flip-flop to a D flip-flop?

22) Define Clock skew , Negative Clock Skew, Positive Clock Skew.

23) Define Metastability.

24) Give the characteristic tables of RS, JK, D and T flip-flops

25) Mention and explain fundamental VHDL units

26) Comparison between VHDL and Verilog

27) Explain compilation, Simulation and synthesis

28) Explain design flow or design process for implementation of hardware

29) Why is it called VHDL code rather than VHDL program

30) Explain all the library packages in VHDL

31) Mention the design units of VHDL

32) Explain VHDL and Verilog codes

33) Explain difference between signal and variable with an example

34) Classify and explain data types in HDL

35) Explain syntax of generic statement

36) Explain structure of data type description

37) Write the syntax of sequential stamens in HDL

38) Explain CASEX and CASEZ statement

39) Explain the highlight of structural description

40) Explain

(a) Binding between entity and architecture in VHDL

(b) Binding between library and module in VHDL

(c) Binding between library and component in VHDL

(d) Binding between two modules in Verilog

41) Explain procedure, task and function in HDL with an Example

42) Difference between task and function?

43) Differences between Functions and Procedures in VHDL?

44) What is delta simulation time?

45) What is sensitivity list?

46) What is the difference between wire and reg data type?

47) What is the difference between = = = and = =?

48) What is the difference between unary and logical operators?

49) Difference between blocking and non-blocking?

50) Explain VHDL file processing

51) Explain highlight of mixed language description

52) How to invoke one language from the other

53) Mention the limitation of mixed language disruption

54) Expand the following: PLA, PAL, CPLD, and FPGA.

55) Mention difference between FPGA and CPLD

HDL LAB (06ECL48)


56) What is LUT?

57) What is the significance of FPGAs in modern day electronics?

58) Give True or False.

(a) CPLD consumes less power per gate when compared to FPGA.

(b) CPLD has more complexity than FPGA

(c) FPGA design is slower than corresponding ASIC design.

(d) FPGA can be used to verify the design before making an ASIC.

(e) PALs have programmable OR plane.

(f) FPGA designs are cheaper than corresponding ASIC, irrespective of design

complexity.

59) What are different types of FPGA? What are you currently using and what is its clock

frequency?

60) Can you draw general structure of FPGA?

61) Why cannot initial statement be synthesizable?

62) Explain the Various steps in Synthesis?

63) Give detail about pattern generator and logic analyzer?

64) Expand XST, ISE, IDE, RTL,xc3s400-5tq144

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HDL Lab Manual