Heterogeneous FPGA architecture and CAD

Peter Jamieson

Supervisor: Jonathan Rose

Motivation

• FPGAs are a popular technology for implementing digital circuits

• Consist of programmable logic and routing Fabric

Modern FPGA

• Add hard circuit structures to improve speed, area efficiency, and power consumption– Flip-flop– Memory– Multiplier

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

SOFTLOGIC

ME

MO

RY

BL

OC

K

ME

MO

RY

BL

OC

K

High-level Goals of our Research

• To improve the speed, area, and power consumption of an FPGA by architecting a better specific circuit

• To understand and develop algorithms needed to synthesize designs to these types of FPGAs

Past Research

Quartus - Logic optimization

Quartus - Technology map

Quartus - Pack blocks

Quartus - Place blocks

Quartus - Route blocks

FPGA programming file

HDL Description

Odin - Elaborate

Odin - Partial Map

module small (a, b, c, out);input a, b, c;output out;

assign out = (a * b) + (b & ~c));endmodule

Quartus - Logic optimization

Quartus - Technology map

Quartus - Pack blocks

Quartus - Place blocks

Quartus - Route blocks

FPGA programming file

HDL Description

Odin - Elaborate

Odin - Partial Map *

!&

+

a

b

c

outQuartus - Logic optimization

Quartus - Technology map

Quartus - Pack blocks

Quartus - Place blocks

Quartus - Route blocks

FPGA programming file

HDL Description

Odin - Elaborate

Odin - Partial Map

HE

TE

RO

GE

NE

OU

SS

TR

UC

TU

RE

(X)

!&

+

a

b

c

out

Quartus - Logic optimization

Quartus - Technology map

Quartus - Pack blocks

Quartus - Place blocks

Quartus - Route blocks

FPGA programming file

HDL Description

Odin - Elaborate

Odin - Partial Map

HE

TE

RO

GE

NE

OU

SS

TR

UC

TU

RE

(X)

4-LUT

4-LUT

a

b

cout

• Odin – Front-end Verilog Synthesis Tool for Heterogeneous FPGAs

• Used flow to implement Multiplexer to Multiplier mapping

a1

a2

a3

a0

out

es0 es1

AND

AND

AND

AND

AND

AND

AND

AND

ds0

ds1

ds2

ds3

OR

AND

AND

AND

AND

AND

AND

AND

AND

ds0

ds1

ds2

ds3

OR

Latest Research

• What if hard structures are not used?• Wasted silicon and routing resources (70-

90% of FPGA area from routing)!!!

• Looking into architecting new heterogeneous FPGA tiles to improve area efficiency